Chris Lattner | 62ed6b9 | 2008-01-01 01:12:31 +0000 | [diff] [blame] | 1 | //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===// |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // Implementation of the MachineRegisterInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Evan Cheng | f48023b | 2010-04-26 19:16:00 +0000 | [diff] [blame] | 15 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Dan Gohman | 9870826 | 2010-04-14 16:51:49 +0000 | [diff] [blame] | 16 | #include "llvm/Target/TargetInstrInfo.h" |
Jakob Stoklund Olesen | 6d1fd0b | 2011-08-09 16:46:27 +0000 | [diff] [blame] | 17 | #include "llvm/Target/TargetMachine.h" |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 18 | using namespace llvm; |
| 19 | |
Jakob Stoklund Olesen | 73e7dce | 2011-07-29 22:51:22 +0000 | [diff] [blame] | 20 | MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) |
Jakob Stoklund Olesen | e27e1ca | 2011-09-30 22:18:51 +0000 | [diff] [blame] | 21 | : TRI(&TRI), IsSSA(true) { |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 22 | VRegInfo.reserve(256); |
Evan Cheng | 90f95f8 | 2009-06-14 20:22:55 +0000 | [diff] [blame] | 23 | RegAllocHints.reserve(256); |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 24 | UsedPhysRegs.resize(TRI.getNumRegs()); |
Chris Lattner | 62ed6b9 | 2008-01-01 01:12:31 +0000 | [diff] [blame] | 25 | |
| 26 | // Create the physreg use/def lists. |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 27 | PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; |
| 28 | memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); |
Chris Lattner | 62ed6b9 | 2008-01-01 01:12:31 +0000 | [diff] [blame] | 29 | } |
| 30 | |
| 31 | MachineRegisterInfo::~MachineRegisterInfo() { |
| 32 | #ifndef NDEBUG |
Jakob Stoklund Olesen | 994c727 | 2011-01-09 03:05:46 +0000 | [diff] [blame] | 33 | for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) |
| 34 | assert(VRegInfo[TargetRegisterInfo::index2VirtReg(i)].second == 0 && |
| 35 | "Vreg use list non-empty still?"); |
Dan Gohman | 03bafaf | 2008-07-07 19:55:35 +0000 | [diff] [blame] | 36 | for (unsigned i = 0, e = UsedPhysRegs.size(); i != e; ++i) |
| 37 | assert(!PhysRegUseDefLists[i] && |
| 38 | "PhysRegUseDefLists has entries after all instructions are deleted"); |
Chris Lattner | 62ed6b9 | 2008-01-01 01:12:31 +0000 | [diff] [blame] | 39 | #endif |
| 40 | delete [] PhysRegUseDefLists; |
| 41 | } |
| 42 | |
Dan Gohman | 33f1c68 | 2009-04-15 01:19:35 +0000 | [diff] [blame] | 43 | /// setRegClass - Set the register class of the specified virtual register. |
| 44 | /// |
| 45 | void |
| 46 | MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { |
Dan Gohman | 33f1c68 | 2009-04-15 01:19:35 +0000 | [diff] [blame] | 47 | VRegInfo[Reg].first = RC; |
Dan Gohman | 33f1c68 | 2009-04-15 01:19:35 +0000 | [diff] [blame] | 48 | } |
| 49 | |
Jakob Stoklund Olesen | bf4699c | 2010-10-06 23:54:39 +0000 | [diff] [blame] | 50 | const TargetRegisterClass * |
| 51 | MachineRegisterInfo::constrainRegClass(unsigned Reg, |
Jakob Stoklund Olesen | 91fb536 | 2011-09-22 21:39:31 +0000 | [diff] [blame] | 52 | const TargetRegisterClass *RC, |
| 53 | unsigned MinNumRegs) { |
Jakob Stoklund Olesen | bf4699c | 2010-10-06 23:54:39 +0000 | [diff] [blame] | 54 | const TargetRegisterClass *OldRC = getRegClass(Reg); |
| 55 | if (OldRC == RC) |
| 56 | return RC; |
Jakob Stoklund Olesen | e27e1ca | 2011-09-30 22:18:51 +0000 | [diff] [blame] | 57 | const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); |
Jakob Stoklund Olesen | 91fb536 | 2011-09-22 21:39:31 +0000 | [diff] [blame] | 58 | if (!NewRC || NewRC == OldRC) |
| 59 | return NewRC; |
| 60 | if (NewRC->getNumRegs() < MinNumRegs) |
Jakob Stoklund Olesen | bf4699c | 2010-10-06 23:54:39 +0000 | [diff] [blame] | 61 | return 0; |
Jakob Stoklund Olesen | 91fb536 | 2011-09-22 21:39:31 +0000 | [diff] [blame] | 62 | setRegClass(Reg, NewRC); |
Jakob Stoklund Olesen | bf4699c | 2010-10-06 23:54:39 +0000 | [diff] [blame] | 63 | return NewRC; |
| 64 | } |
| 65 | |
Jakob Stoklund Olesen | 6d1fd0b | 2011-08-09 16:46:27 +0000 | [diff] [blame] | 66 | bool |
| 67 | MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { |
| 68 | const TargetInstrInfo *TII = TM.getInstrInfo(); |
Jakob Stoklund Olesen | 6d1fd0b | 2011-08-09 16:46:27 +0000 | [diff] [blame] | 69 | const TargetRegisterClass *OldRC = getRegClass(Reg); |
| 70 | const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); |
| 71 | |
| 72 | // Stop early if there is no room to grow. |
| 73 | if (NewRC == OldRC) |
| 74 | return false; |
| 75 | |
| 76 | // Accumulate constraints from all uses. |
| 77 | for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; |
| 78 | ++I) { |
| 79 | // TRI doesn't have accurate enough information to model this yet. |
| 80 | if (I.getOperand().getSubReg()) |
| 81 | return false; |
Jakob Stoklund Olesen | 6d1fd0b | 2011-08-09 16:46:27 +0000 | [diff] [blame] | 82 | const TargetRegisterClass *OpRC = |
Jakob Stoklund Olesen | dee83c9 | 2011-10-12 23:37:40 +0000 | [diff] [blame] | 83 | I->getRegClassConstraint(I.getOperandNo(), TII, TRI); |
Jakob Stoklund Olesen | 6d1fd0b | 2011-08-09 16:46:27 +0000 | [diff] [blame] | 84 | if (OpRC) |
Jakob Stoklund Olesen | e27e1ca | 2011-09-30 22:18:51 +0000 | [diff] [blame] | 85 | NewRC = TRI->getCommonSubClass(NewRC, OpRC); |
Jakob Stoklund Olesen | 6d1fd0b | 2011-08-09 16:46:27 +0000 | [diff] [blame] | 86 | if (!NewRC || NewRC == OldRC) |
| 87 | return false; |
| 88 | } |
| 89 | setRegClass(Reg, NewRC); |
| 90 | return true; |
| 91 | } |
| 92 | |
Dan Gohman | 2e3e5bf | 2008-12-08 04:54:11 +0000 | [diff] [blame] | 93 | /// createVirtualRegister - Create and return a new virtual register in the |
| 94 | /// function with the specified register class. |
| 95 | /// |
| 96 | unsigned |
| 97 | MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ |
| 98 | assert(RegClass && "Cannot create register without RegClass!"); |
Jakob Stoklund Olesen | f462e3f | 2011-06-02 23:07:20 +0000 | [diff] [blame] | 99 | assert(RegClass->isAllocatable() && |
| 100 | "Virtual register RegClass must be allocatable."); |
Dan Gohman | 2e3e5bf | 2008-12-08 04:54:11 +0000 | [diff] [blame] | 101 | |
Jakob Stoklund Olesen | 994c727 | 2011-01-09 03:05:46 +0000 | [diff] [blame] | 102 | // New virtual register number. |
| 103 | unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); |
| 104 | |
| 105 | // Add a reg, but keep track of whether the vector reallocated or not. |
| 106 | const unsigned FirstVirtReg = TargetRegisterInfo::index2VirtReg(0); |
| 107 | void *ArrayBase = getNumVirtRegs() == 0 ? 0 : &VRegInfo[FirstVirtReg]; |
| 108 | VRegInfo.grow(Reg); |
| 109 | VRegInfo[Reg].first = RegClass; |
| 110 | RegAllocHints.grow(Reg); |
| 111 | |
| 112 | if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase) |
Dan Gohman | 2e3e5bf | 2008-12-08 04:54:11 +0000 | [diff] [blame] | 113 | // The vector reallocated, handle this now. |
| 114 | HandleVRegListReallocation(); |
Jakob Stoklund Olesen | 994c727 | 2011-01-09 03:05:46 +0000 | [diff] [blame] | 115 | return Reg; |
Dan Gohman | 2e3e5bf | 2008-12-08 04:54:11 +0000 | [diff] [blame] | 116 | } |
| 117 | |
Chris Lattner | 62ed6b9 | 2008-01-01 01:12:31 +0000 | [diff] [blame] | 118 | /// HandleVRegListReallocation - We just added a virtual register to the |
| 119 | /// VRegInfo info list and it reallocated. Update the use/def lists info |
| 120 | /// pointers. |
| 121 | void MachineRegisterInfo::HandleVRegListReallocation() { |
| 122 | // The back pointers for the vreg lists point into the previous vector. |
| 123 | // Update them to point to their correct slots. |
Jakob Stoklund Olesen | 994c727 | 2011-01-09 03:05:46 +0000 | [diff] [blame] | 124 | for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) { |
| 125 | unsigned Reg = TargetRegisterInfo::index2VirtReg(i); |
| 126 | MachineOperand *List = VRegInfo[Reg].second; |
Chris Lattner | 62ed6b9 | 2008-01-01 01:12:31 +0000 | [diff] [blame] | 127 | if (!List) continue; |
| 128 | // Update the back-pointer to be accurate once more. |
Jakob Stoklund Olesen | 994c727 | 2011-01-09 03:05:46 +0000 | [diff] [blame] | 129 | List->Contents.Reg.Prev = &VRegInfo[Reg].second; |
Chris Lattner | 62ed6b9 | 2008-01-01 01:12:31 +0000 | [diff] [blame] | 130 | } |
Chris Lattner | 84bc542 | 2007-12-31 04:13:23 +0000 | [diff] [blame] | 131 | } |
Chris Lattner | a91a7d5 | 2008-01-01 03:07:29 +0000 | [diff] [blame] | 132 | |
Chris Lattner | e138b3d | 2008-01-01 20:36:19 +0000 | [diff] [blame] | 133 | /// replaceRegWith - Replace all instances of FromReg with ToReg in the |
| 134 | /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), |
| 135 | /// except that it also changes any definitions of the register as well. |
| 136 | void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { |
| 137 | assert(FromReg != ToReg && "Cannot replace a reg with itself"); |
| 138 | |
| 139 | // TODO: This could be more efficient by bulk changing the operands. |
| 140 | for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) { |
| 141 | MachineOperand &O = I.getOperand(); |
| 142 | ++I; |
| 143 | O.setReg(ToReg); |
| 144 | } |
| 145 | } |
| 146 | |
Chris Lattner | a91a7d5 | 2008-01-01 03:07:29 +0000 | [diff] [blame] | 147 | |
| 148 | /// getVRegDef - Return the machine instr that defines the specified virtual |
| 149 | /// register or null if none is found. This assumes that the code is in SSA |
| 150 | /// form, so there should only be one definition. |
| 151 | MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { |
Dan Gohman | 2bf0649 | 2009-09-25 22:26:13 +0000 | [diff] [blame] | 152 | // Since we are in SSA form, we can use the first definition. |
| 153 | if (!def_empty(Reg)) |
| 154 | return &*def_begin(Reg); |
Chris Lattner | a91a7d5 | 2008-01-01 03:07:29 +0000 | [diff] [blame] | 155 | return 0; |
| 156 | } |
Evan Cheng | 1eb5cf9 | 2008-02-13 02:45:38 +0000 | [diff] [blame] | 157 | |
Evan Cheng | 1423c70 | 2010-03-03 21:18:38 +0000 | [diff] [blame] | 158 | bool MachineRegisterInfo::hasOneUse(unsigned RegNo) const { |
| 159 | use_iterator UI = use_begin(RegNo); |
| 160 | if (UI == use_end()) |
| 161 | return false; |
| 162 | return ++UI == use_end(); |
| 163 | } |
| 164 | |
| 165 | bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const { |
| 166 | use_nodbg_iterator UI = use_nodbg_begin(RegNo); |
| 167 | if (UI == use_nodbg_end()) |
| 168 | return false; |
| 169 | return ++UI == use_nodbg_end(); |
| 170 | } |
Evan Cheng | 1eb5cf9 | 2008-02-13 02:45:38 +0000 | [diff] [blame] | 171 | |
Dan Gohman | 49b4589 | 2010-05-13 19:24:00 +0000 | [diff] [blame] | 172 | /// clearKillFlags - Iterate over all the uses of the given register and |
| 173 | /// clear the kill flag from the MachineOperand. This function is used by |
| 174 | /// optimization passes which extend register lifetimes and need only |
| 175 | /// preserve conservative kill flag information. |
| 176 | void MachineRegisterInfo::clearKillFlags(unsigned Reg) const { |
| 177 | for (use_iterator UI = use_begin(Reg), UE = use_end(); UI != UE; ++UI) |
| 178 | UI.getOperand().setIsKill(false); |
| 179 | } |
| 180 | |
Dan Gohman | 13e73f4 | 2010-04-13 16:55:37 +0000 | [diff] [blame] | 181 | bool MachineRegisterInfo::isLiveIn(unsigned Reg) const { |
| 182 | for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) |
| 183 | if (I->first == Reg || I->second == Reg) |
| 184 | return true; |
| 185 | return false; |
| 186 | } |
| 187 | |
| 188 | bool MachineRegisterInfo::isLiveOut(unsigned Reg) const { |
| 189 | for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I) |
| 190 | if (*I == Reg) |
| 191 | return true; |
| 192 | return false; |
| 193 | } |
| 194 | |
Evan Cheng | 2ad0fcf | 2010-04-28 23:08:54 +0000 | [diff] [blame] | 195 | /// getLiveInPhysReg - If VReg is a live-in virtual register, return the |
| 196 | /// corresponding live-in physical register. |
| 197 | unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const { |
| 198 | for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) |
| 199 | if (I->second == VReg) |
| 200 | return I->first; |
| 201 | return 0; |
| 202 | } |
| 203 | |
Evan Cheng | 3946043 | 2010-05-24 21:33:37 +0000 | [diff] [blame] | 204 | /// getLiveInVirtReg - If PReg is a live-in physical register, return the |
| 205 | /// corresponding live-in physical register. |
| 206 | unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const { |
| 207 | for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) |
| 208 | if (I->first == PReg) |
| 209 | return I->second; |
| 210 | return 0; |
| 211 | } |
| 212 | |
Dan Gohman | 9870826 | 2010-04-14 16:51:49 +0000 | [diff] [blame] | 213 | /// EmitLiveInCopies - Emit copies to initialize livein virtual registers |
| 214 | /// into the given entry block. |
| 215 | void |
| 216 | MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB, |
| 217 | const TargetRegisterInfo &TRI, |
| 218 | const TargetInstrInfo &TII) { |
Evan Cheng | 701d4d3 | 2010-05-29 02:23:39 +0000 | [diff] [blame] | 219 | // Emit the copies into the top of the block. |
Dan Gohman | fe5e4da | 2010-06-24 22:23:02 +0000 | [diff] [blame] | 220 | for (unsigned i = 0, e = LiveIns.size(); i != e; ++i) |
| 221 | if (LiveIns[i].second) { |
| 222 | if (use_empty(LiveIns[i].second)) { |
| 223 | // The livein has no uses. Drop it. |
| 224 | // |
| 225 | // It would be preferable to have isel avoid creating live-in |
| 226 | // records for unused arguments in the first place, but it's |
| 227 | // complicated by the debug info code for arguments. |
| 228 | LiveIns.erase(LiveIns.begin() + i); |
| 229 | --i; --e; |
| 230 | } else { |
| 231 | // Emit a copy. |
Devang Patel | 68e6bee | 2011-02-21 23:21:26 +0000 | [diff] [blame] | 232 | BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(), |
Jakob Stoklund Olesen | 1e1098c | 2010-07-10 22:42:59 +0000 | [diff] [blame] | 233 | TII.get(TargetOpcode::COPY), LiveIns[i].second) |
| 234 | .addReg(LiveIns[i].first); |
Dan Gohman | b13033f | 2010-04-14 17:05:00 +0000 | [diff] [blame] | 235 | |
Dan Gohman | fe5e4da | 2010-06-24 22:23:02 +0000 | [diff] [blame] | 236 | // Add the register to the entry block live-in set. |
| 237 | EntryMBB->addLiveIn(LiveIns[i].first); |
| 238 | } |
| 239 | } else { |
| 240 | // Add the register to the entry block live-in set. |
| 241 | EntryMBB->addLiveIn(LiveIns[i].first); |
| 242 | } |
Dan Gohman | 9870826 | 2010-04-14 16:51:49 +0000 | [diff] [blame] | 243 | } |
| 244 | |
Jakob Stoklund Olesen | 82b07dc | 2010-05-11 20:30:28 +0000 | [diff] [blame] | 245 | void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) { |
| 246 | for (int i = UsedPhysRegs.find_first(); i >= 0; |
| 247 | i = UsedPhysRegs.find_next(i)) |
| 248 | for (const unsigned *SS = TRI.getSubRegisters(i); |
| 249 | unsigned SubReg = *SS; ++SS) |
Jakob Stoklund Olesen | 8e8b3cb | 2010-05-11 20:51:04 +0000 | [diff] [blame] | 250 | if (SubReg > unsigned(i)) |
Jakob Stoklund Olesen | 82b07dc | 2010-05-11 20:30:28 +0000 | [diff] [blame] | 251 | UsedPhysRegs.set(SubReg); |
| 252 | } |
| 253 | |
Evan Cheng | 1eb5cf9 | 2008-02-13 02:45:38 +0000 | [diff] [blame] | 254 | #ifndef NDEBUG |
| 255 | void MachineRegisterInfo::dumpUses(unsigned Reg) const { |
| 256 | for (use_iterator I = use_begin(Reg), E = use_end(); I != E; ++I) |
| 257 | I.getOperand().getParent()->dump(); |
| 258 | } |
| 259 | #endif |