| Evan Cheng | 8557c2b | 2009-06-19 01:51:50 +0000 | [diff] [blame^] | 1 | //===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | //===----------------------------------------------------------------------===// |
| 11 | // Functional units across ARM processors |
| 12 | // |
| 13 | def FU_iALU : FuncUnit; // Integer alu unit |
| 14 | def FU_iLdSt : FuncUnit; // Integer load / store unit |
| 15 | def FU_FpALU : FuncUnit; // FP alu unit |
| 16 | def FU_FpLdSt : FuncUnit; // FP load / store unit |
| 17 | def FU_Br : FuncUnit; // Branch unit |
| 18 | |
| 19 | //===----------------------------------------------------------------------===// |
| 20 | // Instruction Itinerary classes used for ARM |
| 21 | // |
| 22 | def IIC_iALU : InstrItinClass; |
| 23 | def IIC_iLoad : InstrItinClass; |
| 24 | def IIC_iStore : InstrItinClass; |
| 25 | def IIC_fpALU : InstrItinClass; |
| 26 | def IIC_fpLoad : InstrItinClass; |
| 27 | def IIC_fpStore : InstrItinClass; |
| 28 | def IIC_Br : InstrItinClass; |
| 29 | |
| 30 | //===----------------------------------------------------------------------===// |
| 31 | // Processor instruction itineraries. |
| 32 | |
| 33 | def GenericItineraries : ProcessorItineraries<[]>; |
| 34 | |
| 35 | include "ARMScheduleV6.td" |