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Jim Grosbach31c24bf2009-11-07 22:00:39 +00001//===-- Thumb2ITBlockPass.cpp - Insert Thumb IT blocks ----------*- C++ -*-===//
Evan Cheng06e16582009-07-10 01:54:42 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#define DEBUG_TYPE "thumb2-it"
11#include "ARM.h"
Evan Cheng06e16582009-07-10 01:54:42 +000012#include "ARMMachineFunctionInfo.h"
Evan Chenged338e82009-07-11 07:26:20 +000013#include "Thumb2InstrInfo.h"
Evan Cheng06e16582009-07-10 01:54:42 +000014#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/CodeGen/MachineInstrBuilder.h"
16#include "llvm/CodeGen/MachineFunctionPass.h"
Evan Chengd8471242010-06-09 01:46:50 +000017#include "llvm/ADT/SmallSet.h"
Evan Cheng06e16582009-07-10 01:54:42 +000018#include "llvm/ADT/Statistic.h"
19using namespace llvm;
20
Evan Chengd8471242010-06-09 01:46:50 +000021STATISTIC(NumITs, "Number of IT blocks inserted");
22STATISTIC(NumMovedInsts, "Number of predicated instructions moved");
Evan Cheng06e16582009-07-10 01:54:42 +000023
24namespace {
Evan Chengd8471242010-06-09 01:46:50 +000025 class Thumb2ITBlockPass : public MachineFunctionPass {
26 bool PreRegAlloc;
27
28 public:
Evan Cheng06e16582009-07-10 01:54:42 +000029 static char ID;
Owen Anderson90c579d2010-08-06 18:33:48 +000030 Thumb2ITBlockPass() : MachineFunctionPass(ID) {}
Evan Cheng06e16582009-07-10 01:54:42 +000031
Evan Chenged338e82009-07-11 07:26:20 +000032 const Thumb2InstrInfo *TII;
Evan Cheng86050dc2010-06-18 23:09:54 +000033 const TargetRegisterInfo *TRI;
Evan Cheng06e16582009-07-10 01:54:42 +000034 ARMFunctionInfo *AFI;
35
36 virtual bool runOnMachineFunction(MachineFunction &Fn);
37
38 virtual const char *getPassName() const {
39 return "Thumb IT blocks insertion pass";
40 }
41
42 private:
Evan Cheng86050dc2010-06-18 23:09:54 +000043 bool MoveCopyOutOfITBlock(MachineInstr *MI,
44 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
45 SmallSet<unsigned, 4> &Defs,
46 SmallSet<unsigned, 4> &Uses);
Evan Chengd8471242010-06-09 01:46:50 +000047 bool InsertITInstructions(MachineBasicBlock &MBB);
Evan Cheng06e16582009-07-10 01:54:42 +000048 };
49 char Thumb2ITBlockPass::ID = 0;
50}
51
Evan Cheng86050dc2010-06-18 23:09:54 +000052/// TrackDefUses - Tracking what registers are being defined and used by
53/// instructions in the IT block. This also tracks "dependencies", i.e. uses
54/// in the IT block that are defined before the IT instruction.
55static void TrackDefUses(MachineInstr *MI,
56 SmallSet<unsigned, 4> &Defs,
57 SmallSet<unsigned, 4> &Uses,
58 const TargetRegisterInfo *TRI) {
59 SmallVector<unsigned, 4> LocalDefs;
60 SmallVector<unsigned, 4> LocalUses;
61
Evan Chengd8471242010-06-09 01:46:50 +000062 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
63 MachineOperand &MO = MI->getOperand(i);
64 if (!MO.isReg())
65 continue;
66 unsigned Reg = MO.getReg();
Evan Cheng86050dc2010-06-18 23:09:54 +000067 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
Evan Chengd8471242010-06-09 01:46:50 +000068 continue;
Evan Cheng86050dc2010-06-18 23:09:54 +000069 if (MO.isUse())
70 LocalUses.push_back(Reg);
Evan Chengd8471242010-06-09 01:46:50 +000071 else
Evan Cheng86050dc2010-06-18 23:09:54 +000072 LocalDefs.push_back(Reg);
Evan Chengd8471242010-06-09 01:46:50 +000073 }
Evan Cheng86050dc2010-06-18 23:09:54 +000074
75 for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) {
76 unsigned Reg = LocalUses[i];
77 Uses.insert(Reg);
78 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
79 *Subreg; ++Subreg)
80 Uses.insert(*Subreg);
81 }
82
83 for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
84 unsigned Reg = LocalDefs[i];
85 Defs.insert(Reg);
86 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
87 *Subreg; ++Subreg)
88 Defs.insert(*Subreg);
89 if (Reg == ARM::CPSR)
90 continue;
91 }
92}
93
Jakob Stoklund Olesenc66756b2010-07-16 22:35:32 +000094static bool isCopy(MachineInstr *MI) {
95 switch (MI->getOpcode()) {
96 default:
97 return false;
98 case ARM::MOVr:
99 case ARM::MOVr_TC:
100 case ARM::tMOVr:
Jakob Stoklund Olesenc66756b2010-07-16 22:35:32 +0000101 case ARM::t2MOVr:
102 return true;
103 }
104}
105
Evan Cheng86050dc2010-06-18 23:09:54 +0000106bool
107Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI,
108 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
109 SmallSet<unsigned, 4> &Defs,
110 SmallSet<unsigned, 4> &Uses) {
Jakob Stoklund Olesenc66756b2010-07-16 22:35:32 +0000111 if (!isCopy(MI))
112 return false;
113 // llvm models select's as two-address instructions. That means a copy
114 // is inserted before a t2MOVccr, etc. If the copy is scheduled in
115 // between selects we would end up creating multiple IT blocks.
116 assert(MI->getOperand(0).getSubReg() == 0 &&
117 MI->getOperand(1).getSubReg() == 0 &&
118 "Sub-register indices still around?");
Evan Cheng86050dc2010-06-18 23:09:54 +0000119
Jakob Stoklund Olesenc66756b2010-07-16 22:35:32 +0000120 unsigned DstReg = MI->getOperand(0).getReg();
121 unsigned SrcReg = MI->getOperand(1).getReg();
Evan Cheng86050dc2010-06-18 23:09:54 +0000122
Jakob Stoklund Olesenc66756b2010-07-16 22:35:32 +0000123 // First check if it's safe to move it.
124 if (Uses.count(DstReg) || Defs.count(SrcReg))
125 return false;
126
Bill Wendling721e1d22011-10-10 22:52:53 +0000127 // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
128 // if we have:
129 //
130 // movs r1, r1
131 // rsb r1, 0
132 // movs r2, r2
133 // rsb r2, 0
134 //
135 // we don't want this to be converted to:
136 //
137 // movs r1, r1
138 // movs r2, r2
139 // itt mi
140 // rsb r1, 0
141 // rsb r2, 0
142 //
Bill Wendling3f56d4b2011-10-11 00:10:41 +0000143 const MCInstrDesc &MCID = MI->getDesc();
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000144 if (MI->hasOptionalDef() &&
Bill Wendling3f56d4b2011-10-11 00:10:41 +0000145 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
146 return false;
Bill Wendling721e1d22011-10-10 22:52:53 +0000147
Jakob Stoklund Olesenc66756b2010-07-16 22:35:32 +0000148 // Then peek at the next instruction to see if it's predicated on CC or OCC.
149 // If not, then there is nothing to be gained by moving the copy.
150 MachineBasicBlock::iterator I = MI; ++I;
151 MachineBasicBlock::iterator E = MI->getParent()->end();
152 while (I != E && I->isDebugValue())
153 ++I;
154 if (I != E) {
155 unsigned NPredReg = 0;
156 ARMCC::CondCodes NCC = llvm::getITInstrPredicate(I, NPredReg);
157 if (NCC == CC || NCC == OCC)
158 return true;
Evan Cheng86050dc2010-06-18 23:09:54 +0000159 }
160 return false;
Evan Chengd8471242010-06-09 01:46:50 +0000161}
162
163bool Thumb2ITBlockPass::InsertITInstructions(MachineBasicBlock &MBB) {
Evan Cheng06e16582009-07-10 01:54:42 +0000164 bool Modified = false;
165
Evan Chengd8471242010-06-09 01:46:50 +0000166 SmallSet<unsigned, 4> Defs;
167 SmallSet<unsigned, 4> Uses;
Evan Cheng06e16582009-07-10 01:54:42 +0000168 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
169 while (MBBI != E) {
170 MachineInstr *MI = &*MBBI;
Evan Cheng5adb66a2009-09-28 09:14:39 +0000171 DebugLoc dl = MI->getDebugLoc();
172 unsigned PredReg = 0;
Evan Cheng4d54e5b2010-06-22 01:18:16 +0000173 ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg);
Evan Cheng06e16582009-07-10 01:54:42 +0000174 if (CC == ARMCC::AL) {
175 ++MBBI;
176 continue;
177 }
178
Evan Chengd8471242010-06-09 01:46:50 +0000179 Defs.clear();
180 Uses.clear();
Evan Cheng86050dc2010-06-18 23:09:54 +0000181 TrackDefUses(MI, Defs, Uses, TRI);
Evan Chengd8471242010-06-09 01:46:50 +0000182
Evan Cheng06e16582009-07-10 01:54:42 +0000183 // Insert an IT instruction.
Evan Cheng06e16582009-07-10 01:54:42 +0000184 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
185 .addImm(CC);
Evan Cheng86050dc2010-06-18 23:09:54 +0000186
187 // Add implicit use of ITSTATE to IT block instructions.
188 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
189 true/*isImp*/, false/*isKill*/));
190
191 MachineInstr *LastITMI = MI;
Evan Chengd8471242010-06-09 01:46:50 +0000192 MachineBasicBlock::iterator InsertPos = MIB;
Evan Cheng06e16582009-07-10 01:54:42 +0000193 ++MBBI;
194
Evan Cheng86050dc2010-06-18 23:09:54 +0000195 // Form IT block.
Evan Cheng06e16582009-07-10 01:54:42 +0000196 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
Evan Chengbc9b7542009-08-15 07:59:10 +0000197 unsigned Mask = 0, Pos = 3;
Sandeep Patel452b54a2009-10-15 22:25:32 +0000198 // Branches, including tricky ones like LDM_RET, need to end an IT
199 // block so check the instruction we just put in the block.
Jim Grosbach8077e762010-06-07 21:48:47 +0000200 for (; MBBI != E && Pos &&
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000201 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) {
Jim Grosbach8077e762010-06-07 21:48:47 +0000202 if (MBBI->isDebugValue())
203 continue;
Evan Chengd8471242010-06-09 01:46:50 +0000204
Evan Chengfd847112009-09-28 20:47:15 +0000205 MachineInstr *NMI = &*MBBI;
Sandeep Patel452b54a2009-10-15 22:25:32 +0000206 MI = NMI;
Evan Chengd8471242010-06-09 01:46:50 +0000207
Evan Chengfd847112009-09-28 20:47:15 +0000208 unsigned NPredReg = 0;
Evan Cheng4d54e5b2010-06-22 01:18:16 +0000209 ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg);
Evan Cheng86050dc2010-06-18 23:09:54 +0000210 if (NCC == CC || NCC == OCC) {
Johnny Chenb675e252010-03-17 23:14:23 +0000211 Mask |= (NCC & 1) << Pos;
Evan Cheng86050dc2010-06-18 23:09:54 +0000212 // Add implicit use of ITSTATE.
213 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
Jim Grosbache9e3f202010-06-28 04:27:01 +0000214 true/*isImp*/, false/*isKill*/));
Evan Cheng86050dc2010-06-18 23:09:54 +0000215 LastITMI = NMI;
216 } else {
Evan Chengd8471242010-06-09 01:46:50 +0000217 if (NCC == ARMCC::AL &&
Evan Cheng86050dc2010-06-18 23:09:54 +0000218 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) {
219 --MBBI;
220 MBB.remove(NMI);
221 MBB.insert(InsertPos, NMI);
222 ++NumMovedInsts;
223 continue;
Evan Chengd8471242010-06-09 01:46:50 +0000224 }
Evan Cheng06e16582009-07-10 01:54:42 +0000225 break;
Evan Chengd8471242010-06-09 01:46:50 +0000226 }
Evan Cheng86050dc2010-06-18 23:09:54 +0000227 TrackDefUses(NMI, Defs, Uses, TRI);
Evan Chengbc9b7542009-08-15 07:59:10 +0000228 --Pos;
Evan Cheng06e16582009-07-10 01:54:42 +0000229 }
Evan Chengd8471242010-06-09 01:46:50 +0000230
Evan Cheng86050dc2010-06-18 23:09:54 +0000231 // Finalize IT mask.
Evan Chengbc9b7542009-08-15 07:59:10 +0000232 Mask |= (1 << Pos);
Johnny Chenb675e252010-03-17 23:14:23 +0000233 // Tag along (firstcond[0] << 4) with the mask.
234 Mask |= (CC & 1) << 4;
Evan Cheng06e16582009-07-10 01:54:42 +0000235 MIB.addImm(Mask);
Evan Cheng86050dc2010-06-18 23:09:54 +0000236
237 // Last instruction in IT block kills ITSTATE.
238 LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
239
Evan Cheng06e16582009-07-10 01:54:42 +0000240 Modified = true;
241 ++NumITs;
242 }
243
244 return Modified;
245}
246
247bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) {
248 const TargetMachine &TM = Fn.getTarget();
249 AFI = Fn.getInfo<ARMFunctionInfo>();
Evan Chenged338e82009-07-11 07:26:20 +0000250 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
Evan Cheng86050dc2010-06-18 23:09:54 +0000251 TRI = TM.getRegisterInfo();
Evan Cheng06e16582009-07-10 01:54:42 +0000252
253 if (!AFI->isThumbFunction())
254 return false;
255
256 bool Modified = false;
Evan Chengd8471242010-06-09 01:46:50 +0000257 for (MachineFunction::iterator MFI = Fn.begin(), E = Fn.end(); MFI != E; ) {
Evan Cheng06e16582009-07-10 01:54:42 +0000258 MachineBasicBlock &MBB = *MFI;
Evan Chengd8471242010-06-09 01:46:50 +0000259 ++MFI;
Evan Chengdca65392010-07-02 21:07:09 +0000260 Modified |= InsertITInstructions(MBB);
Evan Cheng06e16582009-07-10 01:54:42 +0000261 }
262
Evan Chengdca65392010-07-02 21:07:09 +0000263 if (Modified)
Evan Cheng86050dc2010-06-18 23:09:54 +0000264 AFI->setHasITBlocks(true);
265
Evan Cheng06e16582009-07-10 01:54:42 +0000266 return Modified;
267}
268
Evan Cheng34f8a022009-08-08 02:54:37 +0000269/// createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks
Evan Cheng06e16582009-07-10 01:54:42 +0000270/// insertion pass.
Evan Chengdca65392010-07-02 21:07:09 +0000271FunctionPass *llvm::createThumb2ITBlockPass() {
272 return new Thumb2ITBlockPass();
Evan Cheng06e16582009-07-10 01:54:42 +0000273}