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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 8fc760cbe8d42e788f29b4a21537bc5e25d5ffa3 / . / test / CodeGen / ARM / fast-isel-fold.ll
blob: c920f9b5e705c10ca7d62044f7337e1516e9486c [file] [log] [blame]
Chad Rosier0a63b6a2012-11-17 00:42:06 +0000[diff] [blame]1; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM
2; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB
Chad Rosierb29b9502011-11-13 02:23:59 +0000[diff] [blame]3
4@a = global i8 1, align 1
5@b = global i16 2, align 2
6
7define void @t1() nounwind uwtable ssp {
8; ARM: t1
9; ARM: ldrb
10; ARM-NOT: uxtb
JF Bastien8fc760c2013-06-07 20:10:37 +0000[diff] [blame^]11; ARM-NOT: and{{.*}}, #255
Chad Rosierb29b9502011-11-13 02:23:59 +0000[diff] [blame]12; THUMB: t1
13; THUMB: ldrb
14; THUMB-NOT: uxtb
JF Bastien8fc760c2013-06-07 20:10:37 +0000[diff] [blame^]15; THUMB-NOT: and{{.*}}, #255
Chad Rosierb29b9502011-11-13 02:23:59 +0000[diff] [blame]16 %1 = load i8* @a, align 1
17 call void @foo1(i8 zeroext %1)
18 ret void
19}
20
21define void @t2() nounwind uwtable ssp {
22; ARM: t2
23; ARM: ldrh
24; ARM-NOT: uxth
25; THUMB: t2
26; THUMB: ldrh
27; THUMB-NOT: uxth
28 %1 = load i16* @b, align 2
29 call void @foo2(i16 zeroext %1)
30 ret void
31}
32
33declare void @foo1(i8 zeroext)
34declare void @foo2(i16 zeroext)
35
36define i32 @t3() nounwind uwtable ssp {
37; ARM: t3
38; ARM: ldrb
39; ARM-NOT: uxtb
JF Bastien8fc760c2013-06-07 20:10:37 +0000[diff] [blame^]40; ARM-NOT: and{{.*}}, #255
Chad Rosierb29b9502011-11-13 02:23:59 +0000[diff] [blame]41; THUMB: t3
42; THUMB: ldrb
43; THUMB-NOT: uxtb
JF Bastien8fc760c2013-06-07 20:10:37 +0000[diff] [blame^]44; THUMB-NOT: and{{.*}}, #255
Chad Rosierb29b9502011-11-13 02:23:59 +0000[diff] [blame]45 %1 = load i8* @a, align 1
46 %2 = zext i8 %1 to i32
47 ret i32 %2
48}
49
50define i32 @t4() nounwind uwtable ssp {
51; ARM: t4
52; ARM: ldrh
53; ARM-NOT: uxth
54; THUMB: t4
55; THUMB: ldrh
56; THUMB-NOT: uxth
57 %1 = load i16* @b, align 2
58 %2 = zext i16 %1 to i32
59 ret i32 %2
60}
61
62define i32 @t5() nounwind uwtable ssp {
63; ARM: t5
64; ARM: ldrsh
65; ARM-NOT: sxth
66; THUMB: t5
67; THUMB: ldrsh
68; THUMB-NOT: sxth
69 %1 = load i16* @b, align 2
70 %2 = sext i16 %1 to i32
71 ret i32 %2
72}
73
74define i32 @t6() nounwind uwtable ssp {
75; ARM: t6
76; ARM: ldrsb
77; ARM-NOT: sxtb
78; THUMB: t6
79; THUMB: ldrsb
80; THUMB-NOT: sxtb
81 %1 = load i8* @a, align 2
82 %2 = sext i8 %1 to i32
83 ret i32 %2
84}