| Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 1 | //===- Alpha.td - Describe the Alpha Target Machine --------*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| Chris Lattner | 081ce94 | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | // Get the target-independent interfaces which we are implementing... |
| 14 | // |
| 15 | include "../Target.td" |
| 16 | |
| 17 | //Alpha is little endian |
| 18 | |
| 19 | //===----------------------------------------------------------------------===// |
| 20 | // Subtarget Features |
| 21 | //===----------------------------------------------------------------------===// |
| 22 | |
| 23 | def FeatureCIX : SubtargetFeature<"cix", "HasCT", "true", |
| 24 | "Enable CIX extentions">; |
| 25 | |
| 26 | //===----------------------------------------------------------------------===// |
| 27 | // Register File Description |
| 28 | //===----------------------------------------------------------------------===// |
| 29 | |
| 30 | include "AlphaRegisterInfo.td" |
| 31 | |
| 32 | //===----------------------------------------------------------------------===// |
| 33 | // Schedule Description |
| 34 | //===----------------------------------------------------------------------===// |
| 35 | |
| 36 | include "AlphaSchedule.td" |
| 37 | |
| 38 | //===----------------------------------------------------------------------===// |
| 39 | // Instruction Descriptions |
| 40 | //===----------------------------------------------------------------------===// |
| 41 | |
| 42 | include "AlphaInstrInfo.td" |
| 43 | |
| 44 | def AlphaInstrInfo : InstrInfo { |
| 45 | // Define how we want to layout our target-specific information field. |
| 46 | // let TSFlagsFields = []; |
| 47 | // let TSFlagsShifts = []; |
| 48 | } |
| 49 | |
| 50 | //===----------------------------------------------------------------------===// |
| 51 | // Alpha Processor Definitions |
| 52 | //===----------------------------------------------------------------------===// |
| 53 | |
| 54 | def : Processor<"generic", Alpha21264Itineraries, []>; |
| 55 | def : Processor<"ev6" , Alpha21264Itineraries, []>; |
| 56 | def : Processor<"ev67" , Alpha21264Itineraries, [FeatureCIX]>; |
| 57 | |
| 58 | //===----------------------------------------------------------------------===// |
| 59 | // The Alpha Target |
| 60 | //===----------------------------------------------------------------------===// |
| 61 | |
| 62 | |
| 63 | def Alpha : Target { |
| 64 | // Pull in Instruction Info: |
| 65 | let InstructionSet = AlphaInstrInfo; |
| 66 | } |