Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 1 | ///===-- FastISel.cpp - Implementation of the FastISel class --------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the implementation of the FastISel class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Dan Gohman | 6f2766d | 2008-08-19 22:31:46 +0000 | [diff] [blame] | 14 | #include "llvm/Instructions.h" |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 15 | #include "llvm/CodeGen/FastISel.h" |
| 16 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 17 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 18 | #include "llvm/Target/TargetData.h" |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 19 | #include "llvm/Target/TargetInstrInfo.h" |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 20 | #include "llvm/Target/TargetLowering.h" |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 21 | #include "llvm/Target/TargetMachine.h" |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 22 | using namespace llvm; |
| 23 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 24 | unsigned FastISel::getRegForValue(Value *V) { |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 25 | // Look up the value to see if we already have a register for it. We |
| 26 | // cache values defined by Instructions across blocks, and other values |
| 27 | // only locally. This is because Instructions already have the SSA |
| 28 | // def-dominatess-use requirement enforced. |
Owen Anderson | 99aaf10 | 2008-09-03 17:37:03 +0000 | [diff] [blame] | 29 | if (ValueMap.count(V)) |
| 30 | return ValueMap[V]; |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 31 | unsigned Reg = LocalValueMap[V]; |
| 32 | if (Reg != 0) |
| 33 | return Reg; |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 34 | |
| 35 | MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT(); |
| 36 | if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { |
| 37 | if (CI->getValue().getActiveBits() > 64) |
| 38 | return 0; |
Owen Anderson | 99aaf10 | 2008-09-03 17:37:03 +0000 | [diff] [blame] | 39 | // Don't cache constant materializations. To do so would require |
| 40 | // tracking what uses they dominate. |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 41 | Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); |
Dan Gohman | 205d925 | 2008-08-28 21:19:07 +0000 | [diff] [blame] | 42 | } else if (isa<ConstantPointerNull>(V)) { |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 43 | Reg = FastEmit_i(VT, VT, ISD::Constant, 0); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 44 | } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) { |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 45 | Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 46 | |
| 47 | if (!Reg) { |
| 48 | const APFloat &Flt = CF->getValueAPF(); |
| 49 | MVT IntVT = TLI.getPointerTy(); |
| 50 | |
| 51 | uint64_t x[2]; |
| 52 | uint32_t IntBitWidth = IntVT.getSizeInBits(); |
| 53 | if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, |
| 54 | APFloat::rmTowardZero) != APFloat::opOK) |
| 55 | return 0; |
| 56 | APInt IntVal(IntBitWidth, 2, x); |
| 57 | |
| 58 | unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), |
| 59 | ISD::Constant, IntVal.getZExtValue()); |
| 60 | if (IntegerReg == 0) |
| 61 | return 0; |
| 62 | Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg); |
| 63 | if (Reg == 0) |
| 64 | return 0; |
| 65 | } |
Dan Gohman | 205d925 | 2008-08-28 21:19:07 +0000 | [diff] [blame] | 66 | } else if (isa<UndefValue>(V)) { |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 67 | Reg = createResultReg(TLI.getRegClassFor(VT)); |
Dan Gohman | 205d925 | 2008-08-28 21:19:07 +0000 | [diff] [blame] | 68 | BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg); |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 69 | } else { |
| 70 | return 0; |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 71 | } |
Owen Anderson | d5d81a4 | 2008-09-03 17:51:57 +0000 | [diff] [blame] | 72 | |
Dan Gohman | 104e4ce | 2008-09-03 23:32:19 +0000 | [diff] [blame] | 73 | LocalValueMap[V] = Reg; |
| 74 | return Reg; |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 75 | } |
| 76 | |
Owen Anderson | cc54e76 | 2008-08-30 00:38:46 +0000 | [diff] [blame] | 77 | /// UpdateValueMap - Update the value map to include the new mapping for this |
| 78 | /// instruction, or insert an extra copy to get the result in a previous |
| 79 | /// determined register. |
| 80 | /// NOTE: This is only necessary because we might select a block that uses |
| 81 | /// a value before we select the block that defines the value. It might be |
| 82 | /// possible to fix this by selecting blocks in reverse postorder. |
Owen Anderson | 95267a1 | 2008-09-05 00:06:23 +0000 | [diff] [blame^] | 83 | void FastISel::UpdateValueMap(Value* I, unsigned Reg) { |
Owen Anderson | cc54e76 | 2008-08-30 00:38:46 +0000 | [diff] [blame] | 84 | if (!ValueMap.count(I)) |
| 85 | ValueMap[I] = Reg; |
| 86 | else |
| 87 | TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I], |
| 88 | Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg)); |
| 89 | } |
| 90 | |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 91 | /// SelectBinaryOp - Select and emit code for a binary operator instruction, |
| 92 | /// which has an opcode which directly corresponds to the given ISD opcode. |
| 93 | /// |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 94 | bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode) { |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 95 | MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); |
| 96 | if (VT == MVT::Other || !VT.isSimple()) |
| 97 | // Unhandled type. Halt "fast" selection and bail. |
| 98 | return false; |
Dan Gohman | b71fea2 | 2008-08-26 20:52:40 +0000 | [diff] [blame] | 99 | // We only handle legal types. For example, on x86-32 the instruction |
| 100 | // selector contains all of the 64-bit instructions from x86-64, |
| 101 | // under the assumption that i64 won't be used if the target doesn't |
| 102 | // support it. |
| 103 | if (!TLI.isTypeLegal(VT)) |
| 104 | return false; |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 105 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 106 | unsigned Op0 = getRegForValue(I->getOperand(0)); |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 107 | if (Op0 == 0) |
| 108 | // Unhandled operand. Halt "fast" selection and bail. |
| 109 | return false; |
| 110 | |
| 111 | // Check if the second operand is a constant and handle it appropriately. |
| 112 | if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 113 | unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(), |
| 114 | ISDOpcode, Op0, CI->getZExtValue()); |
| 115 | if (ResultReg != 0) { |
| 116 | // We successfully emitted code for the given LLVM Instruction. |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 117 | UpdateValueMap(I, ResultReg); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 118 | return true; |
| 119 | } |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 120 | } |
| 121 | |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 122 | // Check if the second operand is a constant float. |
| 123 | if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) { |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 124 | unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), |
| 125 | ISDOpcode, Op0, CF); |
| 126 | if (ResultReg != 0) { |
| 127 | // We successfully emitted code for the given LLVM Instruction. |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 128 | UpdateValueMap(I, ResultReg); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 129 | return true; |
| 130 | } |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 131 | } |
| 132 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 133 | unsigned Op1 = getRegForValue(I->getOperand(1)); |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 134 | if (Op1 == 0) |
| 135 | // Unhandled operand. Halt "fast" selection and bail. |
| 136 | return false; |
| 137 | |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 138 | // Now we have both operands in registers. Emit the instruction. |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 139 | unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), |
| 140 | ISDOpcode, Op0, Op1); |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 141 | if (ResultReg == 0) |
| 142 | // Target-specific code wasn't able to find a machine opcode for |
| 143 | // the given ISD opcode and type. Halt "fast" selection and bail. |
| 144 | return false; |
| 145 | |
Dan Gohman | 8014e86 | 2008-08-20 00:23:20 +0000 | [diff] [blame] | 146 | // We successfully emitted code for the given LLVM Instruction. |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 147 | UpdateValueMap(I, ResultReg); |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 148 | return true; |
| 149 | } |
| 150 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 151 | bool FastISel::SelectGetElementPtr(Instruction *I) { |
| 152 | unsigned N = getRegForValue(I->getOperand(0)); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 153 | if (N == 0) |
| 154 | // Unhandled operand. Halt "fast" selection and bail. |
| 155 | return false; |
| 156 | |
| 157 | const Type *Ty = I->getOperand(0)->getType(); |
Dan Gohman | 7a0e659 | 2008-08-21 17:25:26 +0000 | [diff] [blame] | 158 | MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 159 | for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); |
| 160 | OI != E; ++OI) { |
| 161 | Value *Idx = *OI; |
| 162 | if (const StructType *StTy = dyn_cast<StructType>(Ty)) { |
| 163 | unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); |
| 164 | if (Field) { |
| 165 | // N = N + Offset |
| 166 | uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); |
| 167 | // FIXME: This can be optimized by combining the add with a |
| 168 | // subsequent one. |
Dan Gohman | 7a0e659 | 2008-08-21 17:25:26 +0000 | [diff] [blame] | 169 | N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 170 | if (N == 0) |
| 171 | // Unhandled operand. Halt "fast" selection and bail. |
| 172 | return false; |
| 173 | } |
| 174 | Ty = StTy->getElementType(Field); |
| 175 | } else { |
| 176 | Ty = cast<SequentialType>(Ty)->getElementType(); |
| 177 | |
| 178 | // If this is a constant subscript, handle it quickly. |
| 179 | if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { |
| 180 | if (CI->getZExtValue() == 0) continue; |
| 181 | uint64_t Offs = |
| 182 | TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); |
Dan Gohman | 7a0e659 | 2008-08-21 17:25:26 +0000 | [diff] [blame] | 183 | N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 184 | if (N == 0) |
| 185 | // Unhandled operand. Halt "fast" selection and bail. |
| 186 | return false; |
| 187 | continue; |
| 188 | } |
| 189 | |
| 190 | // N = N + Idx * ElementSize; |
| 191 | uint64_t ElementSize = TD.getABITypeSize(Ty); |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 192 | unsigned IdxN = getRegForValue(Idx); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 193 | if (IdxN == 0) |
| 194 | // Unhandled operand. Halt "fast" selection and bail. |
| 195 | return false; |
| 196 | |
| 197 | // If the index is smaller or larger than intptr_t, truncate or extend |
| 198 | // it. |
Evan Cheng | 2076aa8 | 2008-08-21 01:19:11 +0000 | [diff] [blame] | 199 | MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 200 | if (IdxVT.bitsLT(VT)) |
Dan Gohman | 80bc6e2 | 2008-08-26 20:57:08 +0000 | [diff] [blame] | 201 | IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 202 | else if (IdxVT.bitsGT(VT)) |
Dan Gohman | 80bc6e2 | 2008-08-26 20:57:08 +0000 | [diff] [blame] | 203 | IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 204 | if (IdxN == 0) |
| 205 | // Unhandled operand. Halt "fast" selection and bail. |
| 206 | return false; |
| 207 | |
Dan Gohman | 80bc6e2 | 2008-08-26 20:57:08 +0000 | [diff] [blame] | 208 | if (ElementSize != 1) { |
Dan Gohman | f93cf79 | 2008-08-21 17:37:05 +0000 | [diff] [blame] | 209 | IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); |
Dan Gohman | 80bc6e2 | 2008-08-26 20:57:08 +0000 | [diff] [blame] | 210 | if (IdxN == 0) |
| 211 | // Unhandled operand. Halt "fast" selection and bail. |
| 212 | return false; |
| 213 | } |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 214 | N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 215 | if (N == 0) |
| 216 | // Unhandled operand. Halt "fast" selection and bail. |
| 217 | return false; |
| 218 | } |
| 219 | } |
| 220 | |
| 221 | // We successfully emitted code for the given LLVM Instruction. |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 222 | UpdateValueMap(I, N); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 223 | return true; |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 224 | } |
| 225 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 226 | bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode) { |
Owen Anderson | 6336b70 | 2008-08-27 18:58:30 +0000 | [diff] [blame] | 227 | MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); |
| 228 | MVT DstVT = TLI.getValueType(I->getType()); |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 229 | |
| 230 | if (SrcVT == MVT::Other || !SrcVT.isSimple() || |
| 231 | DstVT == MVT::Other || !DstVT.isSimple() || |
| 232 | !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) |
| 233 | // Unhandled type. Halt "fast" selection and bail. |
| 234 | return false; |
| 235 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 236 | unsigned InputReg = getRegForValue(I->getOperand(0)); |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 237 | if (!InputReg) |
| 238 | // Unhandled operand. Halt "fast" selection and bail. |
| 239 | return false; |
| 240 | |
| 241 | unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), |
| 242 | DstVT.getSimpleVT(), |
| 243 | Opcode, |
| 244 | InputReg); |
| 245 | if (!ResultReg) |
| 246 | return false; |
| 247 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 248 | UpdateValueMap(I, ResultReg); |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 249 | return true; |
| 250 | } |
| 251 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 252 | bool FastISel::SelectBitCast(Instruction *I) { |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 253 | // If the bitcast doesn't change the type, just use the operand value. |
| 254 | if (I->getType() == I->getOperand(0)->getType()) { |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 255 | unsigned Reg = getRegForValue(I->getOperand(0)); |
Dan Gohman | a318dab | 2008-08-27 20:41:38 +0000 | [diff] [blame] | 256 | if (Reg == 0) |
| 257 | return false; |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 258 | UpdateValueMap(I, Reg); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 259 | return true; |
| 260 | } |
| 261 | |
| 262 | // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. |
Owen Anderson | 6336b70 | 2008-08-27 18:58:30 +0000 | [diff] [blame] | 263 | MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); |
| 264 | MVT DstVT = TLI.getValueType(I->getType()); |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 265 | |
| 266 | if (SrcVT == MVT::Other || !SrcVT.isSimple() || |
| 267 | DstVT == MVT::Other || !DstVT.isSimple() || |
| 268 | !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) |
| 269 | // Unhandled type. Halt "fast" selection and bail. |
| 270 | return false; |
| 271 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 272 | unsigned Op0 = getRegForValue(I->getOperand(0)); |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 273 | if (Op0 == 0) |
| 274 | // Unhandled operand. Halt "fast" selection and bail. |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 275 | return false; |
| 276 | |
Dan Gohman | ad368ac | 2008-08-27 18:10:19 +0000 | [diff] [blame] | 277 | // First, try to perform the bitcast by inserting a reg-reg copy. |
| 278 | unsigned ResultReg = 0; |
| 279 | if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) { |
| 280 | TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); |
| 281 | TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); |
| 282 | ResultReg = createResultReg(DstClass); |
| 283 | |
| 284 | bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, |
| 285 | Op0, DstClass, SrcClass); |
| 286 | if (!InsertedCopy) |
| 287 | ResultReg = 0; |
| 288 | } |
| 289 | |
| 290 | // If the reg-reg copy failed, select a BIT_CONVERT opcode. |
| 291 | if (!ResultReg) |
| 292 | ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), |
| 293 | ISD::BIT_CONVERT, Op0); |
| 294 | |
| 295 | if (!ResultReg) |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 296 | return false; |
| 297 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 298 | UpdateValueMap(I, ResultReg); |
Owen Anderson | d0533c9 | 2008-08-26 23:46:32 +0000 | [diff] [blame] | 299 | return true; |
| 300 | } |
| 301 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 302 | bool |
| 303 | FastISel::SelectInstruction(Instruction *I) { |
| 304 | switch (I->getOpcode()) { |
| 305 | case Instruction::Add: { |
| 306 | ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; |
| 307 | return SelectBinaryOp(I, Opc); |
| 308 | } |
| 309 | case Instruction::Sub: { |
| 310 | ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; |
| 311 | return SelectBinaryOp(I, Opc); |
| 312 | } |
| 313 | case Instruction::Mul: { |
| 314 | ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; |
| 315 | return SelectBinaryOp(I, Opc); |
| 316 | } |
| 317 | case Instruction::SDiv: |
| 318 | return SelectBinaryOp(I, ISD::SDIV); |
| 319 | case Instruction::UDiv: |
| 320 | return SelectBinaryOp(I, ISD::UDIV); |
| 321 | case Instruction::FDiv: |
| 322 | return SelectBinaryOp(I, ISD::FDIV); |
| 323 | case Instruction::SRem: |
| 324 | return SelectBinaryOp(I, ISD::SREM); |
| 325 | case Instruction::URem: |
| 326 | return SelectBinaryOp(I, ISD::UREM); |
| 327 | case Instruction::FRem: |
| 328 | return SelectBinaryOp(I, ISD::FREM); |
| 329 | case Instruction::Shl: |
| 330 | return SelectBinaryOp(I, ISD::SHL); |
| 331 | case Instruction::LShr: |
| 332 | return SelectBinaryOp(I, ISD::SRL); |
| 333 | case Instruction::AShr: |
| 334 | return SelectBinaryOp(I, ISD::SRA); |
| 335 | case Instruction::And: |
| 336 | return SelectBinaryOp(I, ISD::AND); |
| 337 | case Instruction::Or: |
| 338 | return SelectBinaryOp(I, ISD::OR); |
| 339 | case Instruction::Xor: |
| 340 | return SelectBinaryOp(I, ISD::XOR); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 341 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 342 | case Instruction::GetElementPtr: |
| 343 | return SelectGetElementPtr(I); |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 344 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 345 | case Instruction::Br: { |
| 346 | BranchInst *BI = cast<BranchInst>(I); |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 347 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 348 | if (BI->isUnconditional()) { |
| 349 | MachineFunction::iterator NextMBB = |
| 350 | next(MachineFunction::iterator(MBB)); |
| 351 | BasicBlock *LLVMSucc = BI->getSuccessor(0); |
| 352 | MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; |
Dan Gohman | 6f2766d | 2008-08-19 22:31:46 +0000 | [diff] [blame] | 353 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 354 | if (NextMBB != MF.end() && MSucc == NextMBB) { |
| 355 | // The unconditional fall-through case, which needs no instructions. |
Owen Anderson | 9d5b416 | 2008-08-27 00:31:01 +0000 | [diff] [blame] | 356 | } else { |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 357 | // The unconditional branch case. |
| 358 | TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); |
Owen Anderson | 9d5b416 | 2008-08-27 00:31:01 +0000 | [diff] [blame] | 359 | } |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 360 | MBB->addSuccessor(MSucc); |
| 361 | return true; |
Owen Anderson | 9d5b416 | 2008-08-27 00:31:01 +0000 | [diff] [blame] | 362 | } |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 363 | |
| 364 | // Conditional branches are not handed yet. |
| 365 | // Halt "fast" selection and bail. |
| 366 | return false; |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 367 | } |
| 368 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 369 | case Instruction::PHI: |
| 370 | // PHI nodes are already emitted. |
| 371 | return true; |
| 372 | |
| 373 | case Instruction::BitCast: |
| 374 | return SelectBitCast(I); |
| 375 | |
| 376 | case Instruction::FPToSI: |
| 377 | return SelectCast(I, ISD::FP_TO_SINT); |
| 378 | case Instruction::ZExt: |
| 379 | return SelectCast(I, ISD::ZERO_EXTEND); |
| 380 | case Instruction::SExt: |
| 381 | return SelectCast(I, ISD::SIGN_EXTEND); |
| 382 | case Instruction::Trunc: |
| 383 | return SelectCast(I, ISD::TRUNCATE); |
| 384 | case Instruction::SIToFP: |
| 385 | return SelectCast(I, ISD::SINT_TO_FP); |
| 386 | |
| 387 | case Instruction::IntToPtr: // Deliberate fall-through. |
| 388 | case Instruction::PtrToInt: { |
| 389 | MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); |
| 390 | MVT DstVT = TLI.getValueType(I->getType()); |
| 391 | if (DstVT.bitsGT(SrcVT)) |
| 392 | return SelectCast(I, ISD::ZERO_EXTEND); |
| 393 | if (DstVT.bitsLT(SrcVT)) |
| 394 | return SelectCast(I, ISD::TRUNCATE); |
| 395 | unsigned Reg = getRegForValue(I->getOperand(0)); |
| 396 | if (Reg == 0) return false; |
| 397 | UpdateValueMap(I, Reg); |
| 398 | return true; |
| 399 | } |
| 400 | |
| 401 | default: |
| 402 | // Unhandled instruction. Halt "fast" selection and bail. |
| 403 | return false; |
| 404 | } |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 405 | } |
| 406 | |
Dan Gohman | 3df24e6 | 2008-09-03 23:12:08 +0000 | [diff] [blame] | 407 | FastISel::FastISel(MachineFunction &mf, |
| 408 | DenseMap<const Value *, unsigned> &vm, |
| 409 | DenseMap<const BasicBlock *, MachineBasicBlock *> &bm) |
| 410 | : MBB(0), |
| 411 | ValueMap(vm), |
| 412 | MBBMap(bm), |
| 413 | MF(mf), |
| 414 | MRI(MF.getRegInfo()), |
| 415 | TM(MF.getTarget()), |
Dan Gohman | 22bb311 | 2008-08-22 00:20:26 +0000 | [diff] [blame] | 416 | TD(*TM.getTargetData()), |
| 417 | TII(*TM.getInstrInfo()), |
| 418 | TLI(*TM.getTargetLowering()) { |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 419 | } |
| 420 | |
Dan Gohman | e285a74 | 2008-08-14 21:51:29 +0000 | [diff] [blame] | 421 | FastISel::~FastISel() {} |
| 422 | |
Evan Cheng | 36fd941 | 2008-09-02 21:59:13 +0000 | [diff] [blame] | 423 | unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, |
| 424 | ISD::NodeType) { |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 425 | return 0; |
| 426 | } |
| 427 | |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 428 | unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, |
| 429 | ISD::NodeType, unsigned /*Op0*/) { |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 430 | return 0; |
| 431 | } |
| 432 | |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 433 | unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, |
| 434 | ISD::NodeType, unsigned /*Op0*/, |
| 435 | unsigned /*Op0*/) { |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 436 | return 0; |
| 437 | } |
| 438 | |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 439 | unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, |
| 440 | ISD::NodeType, uint64_t /*Imm*/) { |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 441 | return 0; |
| 442 | } |
| 443 | |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 444 | unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, |
| 445 | ISD::NodeType, ConstantFP * /*FPImm*/) { |
| 446 | return 0; |
| 447 | } |
| 448 | |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 449 | unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, |
| 450 | ISD::NodeType, unsigned /*Op0*/, |
| 451 | uint64_t /*Imm*/) { |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 452 | return 0; |
| 453 | } |
| 454 | |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 455 | unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, |
| 456 | ISD::NodeType, unsigned /*Op0*/, |
| 457 | ConstantFP * /*FPImm*/) { |
| 458 | return 0; |
| 459 | } |
| 460 | |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 461 | unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, |
| 462 | ISD::NodeType, |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 463 | unsigned /*Op0*/, unsigned /*Op1*/, |
| 464 | uint64_t /*Imm*/) { |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 465 | return 0; |
| 466 | } |
| 467 | |
| 468 | /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries |
| 469 | /// to emit an instruction with an immediate operand using FastEmit_ri. |
| 470 | /// If that fails, it materializes the immediate into a register and try |
| 471 | /// FastEmit_rr instead. |
| 472 | unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 473 | unsigned Op0, uint64_t Imm, |
| 474 | MVT::SimpleValueType ImmType) { |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 475 | // First check if immediate type is legal. If not, we can't use the ri form. |
Dan Gohman | 151ed61 | 2008-08-27 18:15:05 +0000 | [diff] [blame] | 476 | unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 477 | if (ResultReg != 0) |
| 478 | return ResultReg; |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 479 | unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm); |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 480 | if (MaterialReg == 0) |
| 481 | return 0; |
Owen Anderson | 0f84e4e | 2008-08-25 23:58:18 +0000 | [diff] [blame] | 482 | return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 483 | } |
| 484 | |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 485 | /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries |
| 486 | /// to emit an instruction with a floating-point immediate operand using |
| 487 | /// FastEmit_rf. If that fails, it materializes the immediate into a register |
| 488 | /// and try FastEmit_rr instead. |
| 489 | unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, |
| 490 | unsigned Op0, ConstantFP *FPImm, |
| 491 | MVT::SimpleValueType ImmType) { |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 492 | // First check if immediate type is legal. If not, we can't use the rf form. |
Dan Gohman | 151ed61 | 2008-08-27 18:15:05 +0000 | [diff] [blame] | 493 | unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 494 | if (ResultReg != 0) |
| 495 | return ResultReg; |
| 496 | |
| 497 | // Materialize the constant in a register. |
| 498 | unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm); |
| 499 | if (MaterialReg == 0) { |
Dan Gohman | 96a9999 | 2008-08-27 18:01:42 +0000 | [diff] [blame] | 500 | // If the target doesn't have a way to directly enter a floating-point |
| 501 | // value into a register, use an alternate approach. |
| 502 | // TODO: The current approach only supports floating-point constants |
| 503 | // that can be constructed by conversion from integer values. This should |
| 504 | // be replaced by code that creates a load from a constant-pool entry, |
| 505 | // which will require some target-specific work. |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 506 | const APFloat &Flt = FPImm->getValueAPF(); |
| 507 | MVT IntVT = TLI.getPointerTy(); |
| 508 | |
| 509 | uint64_t x[2]; |
| 510 | uint32_t IntBitWidth = IntVT.getSizeInBits(); |
| 511 | if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true, |
| 512 | APFloat::rmTowardZero) != APFloat::opOK) |
| 513 | return 0; |
| 514 | APInt IntVal(IntBitWidth, 2, x); |
| 515 | |
| 516 | unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(), |
| 517 | ISD::Constant, IntVal.getZExtValue()); |
| 518 | if (IntegerReg == 0) |
| 519 | return 0; |
| 520 | MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT, |
| 521 | ISD::SINT_TO_FP, IntegerReg); |
| 522 | if (MaterialReg == 0) |
| 523 | return 0; |
| 524 | } |
| 525 | return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg); |
| 526 | } |
| 527 | |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 528 | unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { |
| 529 | return MRI.createVirtualRegister(RC); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 530 | } |
| 531 | |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 532 | unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, |
Dan Gohman | 77ad796 | 2008-08-20 18:09:38 +0000 | [diff] [blame] | 533 | const TargetRegisterClass* RC) { |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 534 | unsigned ResultReg = createResultReg(RC); |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 535 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 536 | |
Dan Gohman | fd90394 | 2008-08-20 23:53:10 +0000 | [diff] [blame] | 537 | BuildMI(MBB, II, ResultReg); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 538 | return ResultReg; |
| 539 | } |
| 540 | |
| 541 | unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, |
| 542 | const TargetRegisterClass *RC, |
| 543 | unsigned Op0) { |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 544 | unsigned ResultReg = createResultReg(RC); |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 545 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 546 | |
Dan Gohman | fd90394 | 2008-08-20 23:53:10 +0000 | [diff] [blame] | 547 | BuildMI(MBB, II, ResultReg).addReg(Op0); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 548 | return ResultReg; |
| 549 | } |
| 550 | |
| 551 | unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, |
| 552 | const TargetRegisterClass *RC, |
| 553 | unsigned Op0, unsigned Op1) { |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 554 | unsigned ResultReg = createResultReg(RC); |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 555 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 556 | |
Dan Gohman | fd90394 | 2008-08-20 23:53:10 +0000 | [diff] [blame] | 557 | BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 558 | return ResultReg; |
| 559 | } |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 560 | |
| 561 | unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, |
| 562 | const TargetRegisterClass *RC, |
| 563 | unsigned Op0, uint64_t Imm) { |
| 564 | unsigned ResultReg = createResultReg(RC); |
| 565 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
| 566 | |
| 567 | BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm); |
| 568 | return ResultReg; |
| 569 | } |
| 570 | |
Dan Gohman | 10df0fa | 2008-08-27 01:09:54 +0000 | [diff] [blame] | 571 | unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode, |
| 572 | const TargetRegisterClass *RC, |
| 573 | unsigned Op0, ConstantFP *FPImm) { |
| 574 | unsigned ResultReg = createResultReg(RC); |
| 575 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
| 576 | |
| 577 | BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm); |
| 578 | return ResultReg; |
| 579 | } |
| 580 | |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 581 | unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, |
| 582 | const TargetRegisterClass *RC, |
| 583 | unsigned Op0, unsigned Op1, uint64_t Imm) { |
| 584 | unsigned ResultReg = createResultReg(RC); |
| 585 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
| 586 | |
| 587 | BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); |
| 588 | return ResultReg; |
| 589 | } |
Owen Anderson | 6d0c25e | 2008-08-25 20:20:32 +0000 | [diff] [blame] | 590 | |
| 591 | unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, |
| 592 | const TargetRegisterClass *RC, |
| 593 | uint64_t Imm) { |
| 594 | unsigned ResultReg = createResultReg(RC); |
| 595 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
| 596 | |
| 597 | BuildMI(MBB, II, ResultReg).addImm(Imm); |
| 598 | return ResultReg; |
Evan Cheng | b41aec5 | 2008-08-25 22:20:39 +0000 | [diff] [blame] | 599 | } |
Owen Anderson | 8970f00 | 2008-08-27 22:30:02 +0000 | [diff] [blame] | 600 | |
Owen Anderson | 40a468f | 2008-08-28 17:47:37 +0000 | [diff] [blame] | 601 | unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) { |
| 602 | const TargetRegisterClass* RC = MRI.getRegClass(Op0); |
Owen Anderson | 8970f00 | 2008-08-27 22:30:02 +0000 | [diff] [blame] | 603 | const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1); |
| 604 | |
| 605 | unsigned ResultReg = createResultReg(SRC); |
| 606 | const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG); |
| 607 | |
Owen Anderson | c0bb68b | 2008-08-28 18:26:01 +0000 | [diff] [blame] | 608 | BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx); |
Owen Anderson | 8970f00 | 2008-08-27 22:30:02 +0000 | [diff] [blame] | 609 | return ResultReg; |
| 610 | } |