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David Goodwin2e7be612009-10-26 16:59:04 +00001//=- llvm/CodeGen/CriticalAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the CriticalAntiDepBreaker class, which
11// implements register anti-dependence breaking along a blocks
12// critical path during post-RA scheduler.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_CODEGEN_CRITICALANTIDEPBREAKER_H
17#define LLVM_CODEGEN_CRITICALANTIDEPBREAKER_H
18
David Goodwin82c72482009-10-28 18:29:54 +000019#include "AntiDepBreaker.h"
David Goodwin2e7be612009-10-26 16:59:04 +000020#include "llvm/CodeGen/MachineBasicBlock.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/ScheduleDAG.h"
25#include "llvm/Target/TargetRegisterInfo.h"
26#include "llvm/ADT/BitVector.h"
27#include "llvm/ADT/SmallSet.h"
David Goodwin557bbe62009-11-20 19:32:48 +000028#include <map>
David Goodwin2e7be612009-10-26 16:59:04 +000029
30namespace llvm {
31 class CriticalAntiDepBreaker : public AntiDepBreaker {
32 MachineFunction& MF;
33 MachineRegisterInfo &MRI;
34 const TargetRegisterInfo *TRI;
35
36 /// AllocatableSet - The set of allocatable registers.
37 /// We'll be ignoring anti-dependencies on non-allocatable registers,
38 /// because they may not be safe to break.
39 const BitVector AllocatableSet;
40
41 /// Classes - For live regs that are only used in one register class in a
42 /// live range, the register class. If the register is not live, the
43 /// corresponding value is null. If the register is live but used in
44 /// multiple register classes, the corresponding value is -1 casted to a
45 /// pointer.
46 const TargetRegisterClass *
47 Classes[TargetRegisterInfo::FirstVirtualRegister];
48
49 /// RegRegs - Map registers to all their references within a live range.
50 std::multimap<unsigned, MachineOperand *> RegRefs;
51
52 /// KillIndices - The index of the most recent kill (proceding bottom-up),
53 /// or ~0u if the register is not live.
54 unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
55
56 /// DefIndices - The index of the most recent complete def (proceding bottom
57 /// up), or ~0u if the register is live.
58 unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
59
60 /// KeepRegs - A set of registers which are live and cannot be changed to
61 /// break anti-dependencies.
62 SmallSet<unsigned, 4> KeepRegs;
63
64 public:
65 CriticalAntiDepBreaker(MachineFunction& MFi);
66 ~CriticalAntiDepBreaker();
Jim Grosbach2973b572010-01-06 16:48:02 +000067
David Goodwin2e7be612009-10-26 16:59:04 +000068 /// Start - Initialize anti-dep breaking for a new basic block.
69 void StartBlock(MachineBasicBlock *BB);
70
Jim Grosbach2973b572010-01-06 16:48:02 +000071 /// BreakAntiDependencies - Identifiy anti-dependencies along the critical
72 /// path
David Goodwin2e7be612009-10-26 16:59:04 +000073 /// of the ScheduleDAG and break them by renaming registers.
74 ///
Dan Gohman66db3a02010-04-19 23:11:58 +000075 unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
76 MachineBasicBlock::iterator Begin,
77 MachineBasicBlock::iterator End,
David Goodwin2e7be612009-10-26 16:59:04 +000078 unsigned InsertPosIndex);
79
80 /// Observe - Update liveness information to account for the current
81 /// instruction, which will not be scheduled.
82 ///
83 void Observe(MachineInstr *MI, unsigned Count, unsigned InsertPosIndex);
84
85 /// Finish - Finish anti-dep breaking for a basic block.
86 void FinishBlock();
87
88 private:
89 void PrescanInstruction(MachineInstr *MI);
90 void ScanInstruction(MachineInstr *MI, unsigned Count);
Jim Grosbach80c2b0d2010-01-06 22:21:25 +000091 unsigned findSuitableFreeRegister(MachineInstr *MI,
92 unsigned AntiDepReg,
David Goodwin2e7be612009-10-26 16:59:04 +000093 unsigned LastNewReg,
94 const TargetRegisterClass *);
95 };
96}
97
98#endif