| Dan Gohman | fce288f | 2009-09-09 00:09:15 +0000 | [diff] [blame] | 1 | ; RUN: llc < %s -march=arm | grep bl.*baz | count 1 |
| 2 | ; RUN: llc < %s -march=arm | grep bl.*quux | count 1 |
| 3 | ; RUN: llc < %s -march=arm -enable-tail-merge=0 | grep bl.*baz | count 2 |
| 4 | ; RUN: llc < %s -march=arm -enable-tail-merge=0 | grep bl.*quux | count 2 |
| 5 | ; RUN: llc < %s -march=arm -enable-eh | grep bl.*baz | count 1 |
| 6 | ; RUN: llc < %s -march=arm -enable-eh | grep bl.*quux | count 1 |
| 7 | ; RUN: llc < %s -march=arm -enable-tail-merge=0 -enable-eh | grep bl.*baz | count 2 |
| 8 | ; RUN: llc < %s -march=arm -enable-tail-merge=0 -enable-eh | grep bl.*quux | count 2 |
| Dale Johannesen | 7e07b30 | 2007-05-22 17:19:23 +0000 | [diff] [blame] | 9 | ; Check that tail merging is the default on ARM, and that -enable-tail-merge=0 works. |
| Duncan Sands | e968514 | 2007-09-05 11:53:04 +0000 | [diff] [blame] | 10 | ; PR1628 |
| Dale Johannesen | 7e07b30 | 2007-05-22 17:19:23 +0000 | [diff] [blame] | 11 | |
| 12 | ; ModuleID = 'tail.c' |
| 13 | target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" |
| 14 | target triple = "i686-apple-darwin8" |
| 15 | |
| 16 | define i32 @f(i32 %i, i32 %q) { |
| 17 | entry: |
| 18 | %i_addr = alloca i32 ; <i32*> [#uses=2] |
| 19 | %q_addr = alloca i32 ; <i32*> [#uses=2] |
| 20 | %retval = alloca i32, align 4 ; <i32*> [#uses=1] |
| 21 | "alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] |
| 22 | store i32 %i, i32* %i_addr |
| 23 | store i32 %q, i32* %q_addr |
| 24 | %tmp = load i32* %i_addr ; <i32> [#uses=1] |
| 25 | %tmp1 = icmp ne i32 %tmp, 0 ; <i1> [#uses=1] |
| 26 | %tmp12 = zext i1 %tmp1 to i8 ; <i8> [#uses=1] |
| 27 | %toBool = icmp ne i8 %tmp12, 0 ; <i1> [#uses=1] |
| 28 | br i1 %toBool, label %cond_true, label %cond_false |
| 29 | |
| 30 | cond_true: ; preds = %entry |
| 31 | %tmp3 = call i32 (...)* @bar( ) ; <i32> [#uses=0] |
| 32 | %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0] |
| 33 | %tmp7 = load i32* %q_addr ; <i32> [#uses=1] |
| 34 | %tmp8 = icmp ne i32 %tmp7, 0 ; <i1> [#uses=1] |
| 35 | %tmp89 = zext i1 %tmp8 to i8 ; <i8> [#uses=1] |
| 36 | %toBool10 = icmp ne i8 %tmp89, 0 ; <i1> [#uses=1] |
| 37 | br i1 %toBool10, label %cond_true11, label %cond_false15 |
| 38 | |
| 39 | cond_false: ; preds = %entry |
| 40 | %tmp5 = call i32 (...)* @foo( ) ; <i32> [#uses=0] |
| 41 | %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; <i32> [#uses=0] |
| 42 | %tmp27 = load i32* %q_addr ; <i32> [#uses=1] |
| 43 | %tmp28 = icmp ne i32 %tmp27, 0 ; <i1> [#uses=1] |
| 44 | %tmp289 = zext i1 %tmp28 to i8 ; <i8> [#uses=1] |
| 45 | %toBool210 = icmp ne i8 %tmp289, 0 ; <i1> [#uses=1] |
| 46 | br i1 %toBool210, label %cond_true11, label %cond_false15 |
| 47 | |
| 48 | cond_true11: ; preds = %cond_next |
| 49 | %tmp13 = call i32 (...)* @foo( ) ; <i32> [#uses=0] |
| 50 | %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0] |
| 51 | br label %cond_next18 |
| 52 | |
| 53 | cond_false15: ; preds = %cond_next |
| 54 | %tmp16 = call i32 (...)* @bar( ) ; <i32> [#uses=0] |
| 55 | %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; <i32> [#uses=0] |
| 56 | br label %cond_next18 |
| 57 | |
| 58 | cond_next18: ; preds = %cond_false15, %cond_true11 |
| 59 | %tmp19 = call i32 (...)* @bar( ) ; <i32> [#uses=0] |
| 60 | br label %return |
| 61 | |
| 62 | return: ; preds = %cond_next18 |
| 63 | %retval20 = load i32* %retval ; <i32> [#uses=1] |
| 64 | ret i32 %retval20 |
| 65 | } |
| 66 | |
| 67 | declare i32 @bar(...) |
| 68 | |
| 69 | declare i32 @baz(...) |
| 70 | |
| 71 | declare i32 @foo(...) |
| 72 | |
| 73 | declare i32 @quux(...) |