Dan Gohman | 36a0947 | 2009-09-08 23:54:48 +0000 | [diff] [blame] | 1 | ; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s |
Mon P Wang | f4646d9 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 2 | |
| 3 | ; test vector shifts converted to proper SSE2 vector shifts when the shift |
| 4 | ; amounts are the same. |
| 5 | |
| 6 | define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind { |
| 7 | entry: |
Mon P Wang | 3653b13 | 2009-09-03 19:57:35 +0000 | [diff] [blame] | 8 | ; CHECK: shift1a: |
| 9 | ; CHECK: psrlq |
Mon P Wang | f4646d9 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 10 | %lshr = lshr <2 x i64> %val, < i64 32, i64 32 > |
| 11 | store <2 x i64> %lshr, <2 x i64>* %dst |
| 12 | ret void |
| 13 | } |
| 14 | |
| 15 | define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind { |
| 16 | entry: |
Mon P Wang | 3653b13 | 2009-09-03 19:57:35 +0000 | [diff] [blame] | 17 | ; CHECK: shift1b: |
| 18 | ; CHECK: movd |
| 19 | ; CHECK-NEXT: psrlq |
Mon P Wang | f4646d9 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 20 | %0 = insertelement <2 x i64> undef, i64 %amt, i32 0 |
| 21 | %1 = insertelement <2 x i64> %0, i64 %amt, i32 1 |
| 22 | %lshr = lshr <2 x i64> %val, %1 |
| 23 | store <2 x i64> %lshr, <2 x i64>* %dst |
| 24 | ret void |
| 25 | } |
| 26 | |
| 27 | define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind { |
| 28 | entry: |
Mon P Wang | 3653b13 | 2009-09-03 19:57:35 +0000 | [diff] [blame] | 29 | ; CHECK: shift2a: |
| 30 | ; CHECK: psrld |
Mon P Wang | f4646d9 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 31 | %lshr = lshr <4 x i32> %val, < i32 17, i32 17, i32 17, i32 17 > |
| 32 | store <4 x i32> %lshr, <4 x i32>* %dst |
| 33 | ret void |
| 34 | } |
| 35 | |
| 36 | define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind { |
| 37 | entry: |
Mon P Wang | 3653b13 | 2009-09-03 19:57:35 +0000 | [diff] [blame] | 38 | ; CHECK: shift2b: |
| 39 | ; CHECK: movd |
| 40 | ; CHECK-NEXT: psrld |
Mon P Wang | f4646d9 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 41 | %0 = insertelement <4 x i32> undef, i32 %amt, i32 0 |
| 42 | %1 = insertelement <4 x i32> %0, i32 %amt, i32 1 |
| 43 | %2 = insertelement <4 x i32> %1, i32 %amt, i32 2 |
| 44 | %3 = insertelement <4 x i32> %2, i32 %amt, i32 3 |
| 45 | %lshr = lshr <4 x i32> %val, %3 |
| 46 | store <4 x i32> %lshr, <4 x i32>* %dst |
| 47 | ret void |
| 48 | } |
| 49 | |
| 50 | |
| 51 | define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind { |
| 52 | entry: |
Mon P Wang | 3653b13 | 2009-09-03 19:57:35 +0000 | [diff] [blame] | 53 | ; CHECK: shift3a: |
| 54 | ; CHECK: psrlw |
Mon P Wang | f4646d9 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 55 | %lshr = lshr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 > |
| 56 | store <8 x i16> %lshr, <8 x i16>* %dst |
| 57 | ret void |
| 58 | } |
| 59 | |
Mon P Wang | 3653b13 | 2009-09-03 19:57:35 +0000 | [diff] [blame] | 60 | ; properly zero extend the shift amount |
Mon P Wang | f4646d9 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 61 | define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind { |
| 62 | entry: |
Mon P Wang | 3653b13 | 2009-09-03 19:57:35 +0000 | [diff] [blame] | 63 | ; CHECK: shift3b: |
| 64 | ; CHECK: movzwl |
| 65 | ; CHECK: movd |
Evan Cheng | b6c215b | 2009-10-23 05:58:34 +0000 | [diff] [blame] | 66 | ; CHECK-NEXT: psrlw |
Mon P Wang | f4646d9 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 67 | %0 = insertelement <8 x i16> undef, i16 %amt, i32 0 |
| 68 | %1 = insertelement <8 x i16> %0, i16 %amt, i32 1 |
| 69 | %2 = insertelement <8 x i16> %0, i16 %amt, i32 2 |
| 70 | %3 = insertelement <8 x i16> %0, i16 %amt, i32 3 |
| 71 | %4 = insertelement <8 x i16> %0, i16 %amt, i32 4 |
| 72 | %5 = insertelement <8 x i16> %0, i16 %amt, i32 5 |
| 73 | %6 = insertelement <8 x i16> %0, i16 %amt, i32 6 |
| 74 | %7 = insertelement <8 x i16> %0, i16 %amt, i32 7 |
| 75 | %lshr = lshr <8 x i16> %val, %7 |
| 76 | store <8 x i16> %lshr, <8 x i16>* %dst |
| 77 | ret void |
Dan Gohman | fea1dd0 | 2009-08-25 15:38:29 +0000 | [diff] [blame] | 78 | } |