blob: dbbf29cdeea81db581d1560831e7b31cfb7fd87e [file] [log] [blame]
Anton Korobeynikovf2c3e172009-05-03 12:57:15 +00001//===- MSP430InstrInfo.cpp - MSP430 Instruction Information ---------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MSP430 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MSP430.h"
15#include "MSP430InstrInfo.h"
16#include "MSP430TargetMachine.h"
17#include "MSP430GenInstrInfo.inc"
18#include "llvm/Function.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22
23
24using namespace llvm;
25
26MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
27 : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)),
Anton Korobeynikovb5612642009-05-03 13:07:54 +000028 RI(tm, *this), TM(tm) {}
Anton Korobeynikov1df221f2009-05-03 13:02:04 +000029
30bool MSP430InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
31 MachineBasicBlock::iterator I,
32 unsigned DestReg, unsigned SrcReg,
33 const TargetRegisterClass *DestRC,
34 const TargetRegisterClass *SrcRC) const {
Anton Korobeynikov1df221f2009-05-03 13:02:04 +000035 DebugLoc DL = DebugLoc::getUnknownLoc();
36 if (I != MBB.end()) DL = I->getDebugLoc();
37
Anton Korobeynikov51c31d62009-05-03 13:05:42 +000038 if (DestRC == SrcRC) {
39 unsigned Opc;
40 if (DestRC == &MSP430::GR16RegClass) {
41 Opc = MSP430::MOV16rr;
42 } else if (DestRC == &MSP430::GR8RegClass) {
43 Opc = MSP430::MOV8rr;
44 } else {
45 return false;
46 }
47
48 BuildMI(MBB, I, DL, get(Opc), DestReg).addReg(SrcReg);
49 return true;
50 }
51
52 return false;
Anton Korobeynikov1df221f2009-05-03 13:02:04 +000053}
54
55bool
56MSP430InstrInfo::isMoveInstr(const MachineInstr& MI,
57 unsigned &SrcReg, unsigned &DstReg,
58 unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
59 SrcSubIdx = DstSubIdx = 0; // No sub-registers yet.
60
61 switch (MI.getOpcode()) {
62 default:
63 return false;
Anton Korobeynikov51c31d62009-05-03 13:05:42 +000064 case MSP430::MOV8rr:
Anton Korobeynikov1df221f2009-05-03 13:02:04 +000065 case MSP430::MOV16rr:
Anton Korobeynikov51c31d62009-05-03 13:05:42 +000066 assert(MI.getNumOperands() >= 2 &&
Anton Korobeynikov1df221f2009-05-03 13:02:04 +000067 MI.getOperand(0).isReg() &&
68 MI.getOperand(1).isReg() &&
69 "invalid register-register move instruction");
70 SrcReg = MI.getOperand(1).getReg();
71 DstReg = MI.getOperand(0).getReg();
72 return true;
73 }
74}