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Chris Lattner5f58e842010-10-05 07:00:12 +00001//===- X86InstrShiftRotate.td - Shift and Rotate Instrs ----*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the shift and rotate instructions.
11//
12//===----------------------------------------------------------------------===//
13
14// FIXME: Someone needs to smear multipattern goodness all over this file.
15
16let Defs = [EFLAGS] in {
17
18let Constraints = "$src1 = $dst" in {
19let Uses = [CL] in {
20def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
21 "shl{b}\t{%cl, $dst|$dst, CL}",
22 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
23def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
24 "shl{w}\t{%cl, $dst|$dst, CL}",
25 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
26def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
27 "shl{l}\t{%cl, $dst|$dst, CL}",
28 [(set GR32:$dst, (shl GR32:$src1, CL))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +000029def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
Devang Patelb1666b92012-01-03 18:22:10 +000030 "shl{q}\t{%cl, $dst|$dst, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +000031 [(set GR64:$dst, (shl GR64:$src1, CL))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +000032} // Uses = [CL]
33
34def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
35 "shl{b}\t{$src2, $dst|$dst, $src2}",
36 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
37
38let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
39def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
40 "shl{w}\t{$src2, $dst|$dst, $src2}",
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
42def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
43 "shl{l}\t{$src2, $dst|$dst, $src2}",
44 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +000045def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
46 (ins GR64:$src1, i8imm:$src2),
47 "shl{q}\t{$src2, $dst|$dst, $src2}",
48 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +000049
50// NOTE: We don't include patterns for shifts of a register by one, because
Chris Lattner5249ff32010-10-05 07:13:35 +000051// 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
Chris Lattner5f58e842010-10-05 07:00:12 +000052def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
53 "shl{b}\t$dst", []>;
54def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
55 "shl{w}\t$dst", []>, OpSize;
56def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
57 "shl{l}\t$dst", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +000058def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
59 "shl{q}\t$dst", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +000060} // isConvertibleToThreeAddress = 1
61} // Constraints = "$src = $dst"
62
63
Chris Lattner5249ff32010-10-05 07:13:35 +000064// FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
65// using CL?
Chris Lattner5f58e842010-10-05 07:00:12 +000066let Uses = [CL] in {
67def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
68 "shl{b}\t{%cl, $dst|$dst, CL}",
69 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
70def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
71 "shl{w}\t{%cl, $dst|$dst, CL}",
72 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
73def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
74 "shl{l}\t{%cl, $dst|$dst, CL}",
75 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +000076def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
Devang Patelb1666b92012-01-03 18:22:10 +000077 "shl{q}\t{%cl, $dst|$dst, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +000078 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +000079}
80def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
81 "shl{b}\t{$src, $dst|$dst, $src}",
82 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
83def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
84 "shl{w}\t{$src, $dst|$dst, $src}",
85 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
86 OpSize;
87def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
88 "shl{l}\t{$src, $dst|$dst, $src}",
89 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +000090def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
91 "shl{q}\t{$src, $dst|$dst, $src}",
92 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +000093
94// Shift by 1
95def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
96 "shl{b}\t$dst",
97 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
98def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
99 "shl{w}\t$dst",
100 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
101 OpSize;
102def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
103 "shl{l}\t$dst",
104 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000105def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
106 "shl{q}\t$dst",
107 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000108
109let Constraints = "$src1 = $dst" in {
110let Uses = [CL] in {
111def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
112 "shr{b}\t{%cl, $dst|$dst, CL}",
113 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
114def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
115 "shr{w}\t{%cl, $dst|$dst, CL}",
116 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
117def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
118 "shr{l}\t{%cl, $dst|$dst, CL}",
119 [(set GR32:$dst, (srl GR32:$src1, CL))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000120def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
Devang Patelb1666b92012-01-03 18:22:10 +0000121 "shr{q}\t{%cl, $dst|$dst, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +0000122 [(set GR64:$dst, (srl GR64:$src1, CL))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000123}
124
125def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
126 "shr{b}\t{$src2, $dst|$dst, $src2}",
127 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
128def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
129 "shr{w}\t{$src2, $dst|$dst, $src2}",
130 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
131def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
132 "shr{l}\t{$src2, $dst|$dst, $src2}",
133 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000134def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
135 "shr{q}\t{$src2, $dst|$dst, $src2}",
136 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000137
Chris Lattner5249ff32010-10-05 07:13:35 +0000138// Shift right by 1
Chris Lattner5f58e842010-10-05 07:00:12 +0000139def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
140 "shr{b}\t$dst",
141 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
142def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
143 "shr{w}\t$dst",
144 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
145def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
146 "shr{l}\t$dst",
147 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000148def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
149 "shr{q}\t$dst",
150 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000151} // Constraints = "$src = $dst"
152
153
154let Uses = [CL] in {
155def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
156 "shr{b}\t{%cl, $dst|$dst, CL}",
157 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
158def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
159 "shr{w}\t{%cl, $dst|$dst, CL}",
160 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
161 OpSize;
162def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
163 "shr{l}\t{%cl, $dst|$dst, CL}",
164 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000165def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
Devang Patelb1666b92012-01-03 18:22:10 +0000166 "shr{q}\t{%cl, $dst|$dst, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +0000167 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000168}
169def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
170 "shr{b}\t{$src, $dst|$dst, $src}",
171 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
172def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
173 "shr{w}\t{$src, $dst|$dst, $src}",
174 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
175 OpSize;
176def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
177 "shr{l}\t{$src, $dst|$dst, $src}",
178 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000179def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
180 "shr{q}\t{$src, $dst|$dst, $src}",
181 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000182
183// Shift by 1
184def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
185 "shr{b}\t$dst",
186 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
187def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
188 "shr{w}\t$dst",
189 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
190def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
191 "shr{l}\t$dst",
192 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000193def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
194 "shr{q}\t$dst",
195 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000196
197let Constraints = "$src1 = $dst" in {
198let Uses = [CL] in {
199def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
200 "sar{b}\t{%cl, $dst|$dst, CL}",
201 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
202def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
203 "sar{w}\t{%cl, $dst|$dst, CL}",
204 [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
205def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
206 "sar{l}\t{%cl, $dst|$dst, CL}",
207 [(set GR32:$dst, (sra GR32:$src1, CL))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000208def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
Devang Patelb1666b92012-01-03 18:22:10 +0000209 "sar{q}\t{%cl, $dst|$dst, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +0000210 [(set GR64:$dst, (sra GR64:$src1, CL))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000211}
212
213def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
214 "sar{b}\t{$src2, $dst|$dst, $src2}",
215 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
216def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
217 "sar{w}\t{$src2, $dst|$dst, $src2}",
218 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
219 OpSize;
220def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
221 "sar{l}\t{$src2, $dst|$dst, $src2}",
222 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000223def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
224 (ins GR64:$src1, i8imm:$src2),
225 "sar{q}\t{$src2, $dst|$dst, $src2}",
226 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000227
228// Shift by 1
229def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
230 "sar{b}\t$dst",
231 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
232def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
233 "sar{w}\t$dst",
234 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
235def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
236 "sar{l}\t$dst",
237 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000238def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
239 "sar{q}\t$dst",
240 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000241} // Constraints = "$src = $dst"
242
243
244let Uses = [CL] in {
245def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
246 "sar{b}\t{%cl, $dst|$dst, CL}",
247 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
248def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
249 "sar{w}\t{%cl, $dst|$dst, CL}",
250 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
251def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
252 "sar{l}\t{%cl, $dst|$dst, CL}",
253 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000254def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
Devang Patelb1666b92012-01-03 18:22:10 +0000255 "sar{q}\t{%cl, $dst|$dst, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +0000256 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000257}
258def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
259 "sar{b}\t{$src, $dst|$dst, $src}",
260 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
261def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
262 "sar{w}\t{$src, $dst|$dst, $src}",
263 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
264 OpSize;
265def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
266 "sar{l}\t{$src, $dst|$dst, $src}",
267 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000268def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
269 "sar{q}\t{$src, $dst|$dst, $src}",
270 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000271
272// Shift by 1
273def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
274 "sar{b}\t$dst",
275 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
276def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
277 "sar{w}\t$dst",
278 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
279 OpSize;
280def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
281 "sar{l}\t$dst",
282 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000283def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
284 "sar{q}\t$dst",
285 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000286
287//===----------------------------------------------------------------------===//
288// Rotate instructions
289//===----------------------------------------------------------------------===//
290
291let Constraints = "$src1 = $dst" in {
292def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000293 "rcl{b}\t$dst", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000294def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
295 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000296let Uses = [CL] in
297def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
298 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000299
300def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000301 "rcl{w}\t$dst", []>, OpSize;
Chris Lattner5f58e842010-10-05 07:00:12 +0000302def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
303 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
Chris Lattner5249ff32010-10-05 07:13:35 +0000304let Uses = [CL] in
305def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
306 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
Chris Lattner5f58e842010-10-05 07:00:12 +0000307
308def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000309 "rcl{l}\t$dst", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000310def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
311 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000312let Uses = [CL] in
313def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
314 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
315
316
317def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000318 "rcl{q}\t$dst", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000319def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
320 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
321let Uses = [CL] in
322def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
323 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
324
325
Chris Lattner5f58e842010-10-05 07:00:12 +0000326def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000327 "rcr{b}\t$dst", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000328def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
329 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000330let Uses = [CL] in
331def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
332 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000333
334def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000335 "rcr{w}\t$dst", []>, OpSize;
Chris Lattner5f58e842010-10-05 07:00:12 +0000336def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
337 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
Chris Lattner5249ff32010-10-05 07:13:35 +0000338let Uses = [CL] in
339def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
340 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
Chris Lattner5f58e842010-10-05 07:00:12 +0000341
342def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000343 "rcr{l}\t$dst", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000344def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
345 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000346let Uses = [CL] in
347def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
348 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
349
350def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000351 "rcr{q}\t$dst", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000352def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
353 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
354let Uses = [CL] in
355def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
356 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
357
Chris Lattner5f58e842010-10-05 07:00:12 +0000358} // Constraints = "$src = $dst"
359
360def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000361 "rcl{b}\t$dst", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000362def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
363 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
364def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000365 "rcl{w}\t$dst", []>, OpSize;
Chris Lattner5f58e842010-10-05 07:00:12 +0000366def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
367 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
368def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000369 "rcl{l}\t$dst", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000370def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
371 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000372def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000373 "rcl{q}\t$dst", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000374def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
375 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>;
376
Chris Lattner5f58e842010-10-05 07:00:12 +0000377def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000378 "rcr{b}\t$dst", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000379def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
380 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
381def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000382 "rcr{w}\t$dst", []>, OpSize;
Chris Lattner5f58e842010-10-05 07:00:12 +0000383def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
384 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
385def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000386 "rcr{l}\t$dst", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000387def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
388 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000389def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
Chris Lattner8c24b0c2010-11-06 21:23:40 +0000390 "rcr{q}\t$dst", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000391def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
392 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000393
394let Uses = [CL] in {
395def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
396 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
397def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
398 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
399def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
400 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000401def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
402 "rcl{q}\t{%cl, $dst|$dst, CL}", []>;
403
Chris Lattner5f58e842010-10-05 07:00:12 +0000404def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
405 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
406def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
407 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
408def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
409 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000410def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
411 "rcr{q}\t{%cl, $dst|$dst, CL}", []>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000412}
413
414let Constraints = "$src1 = $dst" in {
415// FIXME: provide shorter instructions when imm8 == 1
416let Uses = [CL] in {
417def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
418 "rol{b}\t{%cl, $dst|$dst, CL}",
419 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
420def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
421 "rol{w}\t{%cl, $dst|$dst, CL}",
422 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
423def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
424 "rol{l}\t{%cl, $dst|$dst, CL}",
425 [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000426def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
Devang Patelb1666b92012-01-03 18:22:10 +0000427 "rol{q}\t{%cl, $dst|$dst, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +0000428 [(set GR64:$dst, (rotl GR64:$src1, CL))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000429}
430
431def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
432 "rol{b}\t{$src2, $dst|$dst, $src2}",
433 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
434def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
435 "rol{w}\t{$src2, $dst|$dst, $src2}",
436 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
437 OpSize;
438def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
439 "rol{l}\t{$src2, $dst|$dst, $src2}",
440 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000441def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
442 (ins GR64:$src1, i8imm:$src2),
443 "rol{q}\t{$src2, $dst|$dst, $src2}",
444 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000445
446// Rotate by 1
447def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
448 "rol{b}\t$dst",
449 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
450def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
451 "rol{w}\t$dst",
452 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
453def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
454 "rol{l}\t$dst",
455 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000456def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
457 "rol{q}\t$dst",
458 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000459} // Constraints = "$src = $dst"
460
461let Uses = [CL] in {
462def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
463 "rol{b}\t{%cl, $dst|$dst, CL}",
464 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
465def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
466 "rol{w}\t{%cl, $dst|$dst, CL}",
467 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
468def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
469 "rol{l}\t{%cl, $dst|$dst, CL}",
470 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000471def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
Devang Patelb1666b92012-01-03 18:22:10 +0000472 "rol{q}\t{%cl, $dst|$dst, %cl}",
Chris Lattner5249ff32010-10-05 07:13:35 +0000473 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000474}
Chris Lattner5249ff32010-10-05 07:13:35 +0000475def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src1),
476 "rol{b}\t{$src1, $dst|$dst, $src1}",
477 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)]>;
478def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1),
479 "rol{w}\t{$src1, $dst|$dst, $src1}",
480 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)]>,
Chris Lattner5f58e842010-10-05 07:00:12 +0000481 OpSize;
Chris Lattner5249ff32010-10-05 07:13:35 +0000482def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),
483 "rol{l}\t{$src1, $dst|$dst, $src1}",
484 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)]>;
485def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),
486 "rol{q}\t{$src1, $dst|$dst, $src1}",
487 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000488
489// Rotate by 1
490def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
491 "rol{b}\t$dst",
492 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
493def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
494 "rol{w}\t$dst",
495 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
496 OpSize;
497def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
498 "rol{l}\t$dst",
499 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000500def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
501 "rol{q}\t$dst",
502 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000503
504let Constraints = "$src1 = $dst" in {
505let Uses = [CL] in {
506def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
507 "ror{b}\t{%cl, $dst|$dst, CL}",
508 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
509def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
510 "ror{w}\t{%cl, $dst|$dst, CL}",
511 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
512def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
513 "ror{l}\t{%cl, $dst|$dst, CL}",
514 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000515def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
Devang Patelb1666b92012-01-03 18:22:10 +0000516 "ror{q}\t{%cl, $dst|$dst, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +0000517 [(set GR64:$dst, (rotr GR64:$src1, CL))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000518}
519
520def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
521 "ror{b}\t{$src2, $dst|$dst, $src2}",
522 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
523def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
524 "ror{w}\t{$src2, $dst|$dst, $src2}",
525 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
526 OpSize;
527def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
528 "ror{l}\t{$src2, $dst|$dst, $src2}",
529 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000530def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
531 (ins GR64:$src1, i8imm:$src2),
532 "ror{q}\t{$src2, $dst|$dst, $src2}",
533 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000534
535// Rotate by 1
536def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
537 "ror{b}\t$dst",
538 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
539def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
540 "ror{w}\t$dst",
541 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
542def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
543 "ror{l}\t$dst",
544 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000545def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
546 "ror{q}\t$dst",
547 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000548} // Constraints = "$src = $dst"
549
550let Uses = [CL] in {
551def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
552 "ror{b}\t{%cl, $dst|$dst, CL}",
553 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
554def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
555 "ror{w}\t{%cl, $dst|$dst, CL}",
556 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
557def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
558 "ror{l}\t{%cl, $dst|$dst, CL}",
559 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000560def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
Devang Patelb1666b92012-01-03 18:22:10 +0000561 "ror{q}\t{%cl, $dst|$dst, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +0000562 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000563}
564def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
565 "ror{b}\t{$src, $dst|$dst, $src}",
566 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
567def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
568 "ror{w}\t{$src, $dst|$dst, $src}",
569 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
570 OpSize;
571def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
572 "ror{l}\t{$src, $dst|$dst, $src}",
573 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000574def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
575 "ror{q}\t{$src, $dst|$dst, $src}",
576 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000577
578// Rotate by 1
579def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
580 "ror{b}\t$dst",
581 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
582def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
583 "ror{w}\t$dst",
584 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
585 OpSize;
586def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
587 "ror{l}\t$dst",
588 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner5249ff32010-10-05 07:13:35 +0000589def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
590 "ror{q}\t$dst",
591 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
Chris Lattner5f58e842010-10-05 07:00:12 +0000592
593
594//===----------------------------------------------------------------------===//
595// Double shift instructions (generalizations of rotate)
596//===----------------------------------------------------------------------===//
597
598let Constraints = "$src1 = $dst" in {
599
600let Uses = [CL] in {
Chris Lattner5f58e842010-10-05 07:00:12 +0000601def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
602 (ins GR16:$src1, GR16:$src2),
603 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
604 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
605 TB, OpSize;
606def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
607 (ins GR16:$src1, GR16:$src2),
608 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
609 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
610 TB, OpSize;
Chris Lattner5249ff32010-10-05 07:13:35 +0000611def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
612 (ins GR32:$src1, GR32:$src2),
613 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
614 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
615def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
616 (ins GR32:$src1, GR32:$src2),
617 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
618 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
619def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
620 (ins GR64:$src1, GR64:$src2),
Devang Patelb1666b92012-01-03 18:22:10 +0000621 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +0000622 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>,
623 TB;
624def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
625 (ins GR64:$src1, GR64:$src2),
Devang Patelb1666b92012-01-03 18:22:10 +0000626 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +0000627 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>,
628 TB;
Chris Lattner5f58e842010-10-05 07:00:12 +0000629}
630
631let isCommutable = 1 in { // These instructions commute to each other.
Chris Lattner5f58e842010-10-05 07:00:12 +0000632def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
633 (outs GR16:$dst),
634 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
635 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
636 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
637 (i8 imm:$src3)))]>,
638 TB, OpSize;
639def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
640 (outs GR16:$dst),
641 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
642 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
643 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
644 (i8 imm:$src3)))]>,
645 TB, OpSize;
Chris Lattner5249ff32010-10-05 07:13:35 +0000646def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
647 (outs GR32:$dst),
648 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
649 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
650 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
651 (i8 imm:$src3)))]>,
652 TB;
653def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
654 (outs GR32:$dst),
655 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
656 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
657 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
658 (i8 imm:$src3)))]>,
659 TB;
660def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
661 (outs GR64:$dst),
662 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
663 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
664 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
665 (i8 imm:$src3)))]>,
666 TB;
667def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
668 (outs GR64:$dst),
669 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
670 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
671 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
672 (i8 imm:$src3)))]>,
673 TB;
Chris Lattner5f58e842010-10-05 07:00:12 +0000674}
675} // Constraints = "$src = $dst"
676
677let Uses = [CL] in {
Chris Lattner5249ff32010-10-05 07:13:35 +0000678def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
679 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
680 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
681 addr:$dst)]>, TB, OpSize;
682def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
683 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
684 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
685 addr:$dst)]>, TB, OpSize;
686
Chris Lattner5f58e842010-10-05 07:00:12 +0000687def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
688 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
689 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
690 addr:$dst)]>, TB;
691def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
692 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
693 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
694 addr:$dst)]>, TB;
Chris Lattner5249ff32010-10-05 07:13:35 +0000695
696def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
Devang Patelb1666b92012-01-03 18:22:10 +0000697 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +0000698 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
699 addr:$dst)]>, TB;
700def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
Devang Patelb1666b92012-01-03 18:22:10 +0000701 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
Chris Lattner5249ff32010-10-05 07:13:35 +0000702 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
703 addr:$dst)]>, TB;
Chris Lattner5f58e842010-10-05 07:00:12 +0000704}
Chris Lattner5249ff32010-10-05 07:13:35 +0000705
706def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
707 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
708 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
709 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
710 (i8 imm:$src3)), addr:$dst)]>,
711 TB, OpSize;
712def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
713 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
714 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
715 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
716 (i8 imm:$src3)), addr:$dst)]>,
717 TB, OpSize;
718
Chris Lattner5f58e842010-10-05 07:00:12 +0000719def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
720 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
721 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
722 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
723 (i8 imm:$src3)), addr:$dst)]>,
724 TB;
725def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
726 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
727 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
728 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
729 (i8 imm:$src3)), addr:$dst)]>,
730 TB;
731
Chris Lattner5249ff32010-10-05 07:13:35 +0000732def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
733 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
734 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
735 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
736 (i8 imm:$src3)), addr:$dst)]>,
737 TB;
738def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
739 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
740 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
741 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
742 (i8 imm:$src3)), addr:$dst)]>,
743 TB;
744
Chris Lattner5f58e842010-10-05 07:00:12 +0000745} // Defs = [EFLAGS]
746
Craig Topper5679ec32011-10-23 22:18:24 +0000747multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {
748let neverHasSideEffects = 1 in {
749 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2),
750 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
751 []>, TAXD, VEX;
Craig Topper75485d62011-10-23 07:34:00 +0000752 let mayLoad = 1 in
Craig Topper5679ec32011-10-23 22:18:24 +0000753 def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
754 (ins x86memop:$src1, i8imm:$src2),
755 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
756 []>, TAXD, VEX;
757}
758}
Craig Topper75485d62011-10-23 07:34:00 +0000759
Craig Topper5679ec32011-10-23 22:18:24 +0000760multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> {
761let neverHasSideEffects = 1 in {
762 def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
763 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
764 VEX_4VOp3;
Craig Topper75485d62011-10-23 07:34:00 +0000765 let mayLoad = 1 in
Craig Topper5679ec32011-10-23 22:18:24 +0000766 def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
767 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
768 VEX_4VOp3;
769}
770}
771
772let Predicates = [HasBMI2] in {
773 defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>;
774 defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W;
775 defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS;
776 defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W;
777 defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD;
778 defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W;
779 defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8, OpSize;
780 defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8, OpSize, VEX_W;
Craig Topper75485d62011-10-23 07:34:00 +0000781}