Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 1 | //===- X86InstrShiftRotate.td - Shift and Rotate Instrs ----*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file describes the shift and rotate instructions. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | // FIXME: Someone needs to smear multipattern goodness all over this file. |
| 15 | |
| 16 | let Defs = [EFLAGS] in { |
| 17 | |
| 18 | let Constraints = "$src1 = $dst" in { |
| 19 | let Uses = [CL] in { |
| 20 | def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 21 | "shl{b}\t{%cl, $dst|$dst, CL}", |
| 22 | [(set GR8:$dst, (shl GR8:$src1, CL))]>; |
| 23 | def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1), |
| 24 | "shl{w}\t{%cl, $dst|$dst, CL}", |
| 25 | [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize; |
| 26 | def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1), |
| 27 | "shl{l}\t{%cl, $dst|$dst, CL}", |
| 28 | [(set GR32:$dst, (shl GR32:$src1, CL))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 29 | def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 30 | "shl{q}\t{%cl, $dst|$dst, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 31 | [(set GR64:$dst, (shl GR64:$src1, CL))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 32 | } // Uses = [CL] |
| 33 | |
| 34 | def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
| 35 | "shl{b}\t{$src2, $dst|$dst, $src2}", |
| 36 | [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>; |
| 37 | |
| 38 | let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. |
| 39 | def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
| 40 | "shl{w}\t{$src2, $dst|$dst, $src2}", |
| 41 | [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 42 | def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
| 43 | "shl{l}\t{$src2, $dst|$dst, $src2}", |
| 44 | [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 45 | def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), |
| 46 | (ins GR64:$src1, i8imm:$src2), |
| 47 | "shl{q}\t{$src2, $dst|$dst, $src2}", |
| 48 | [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 49 | |
| 50 | // NOTE: We don't include patterns for shifts of a register by one, because |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 51 | // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one). |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 52 | def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1), |
| 53 | "shl{b}\t$dst", []>; |
| 54 | def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1), |
| 55 | "shl{w}\t$dst", []>, OpSize; |
| 56 | def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1), |
| 57 | "shl{l}\t$dst", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 58 | def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1), |
| 59 | "shl{q}\t$dst", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 60 | } // isConvertibleToThreeAddress = 1 |
| 61 | } // Constraints = "$src = $dst" |
| 62 | |
| 63 | |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 64 | // FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern |
| 65 | // using CL? |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 66 | let Uses = [CL] in { |
| 67 | def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst), |
| 68 | "shl{b}\t{%cl, $dst|$dst, CL}", |
| 69 | [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>; |
| 70 | def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst), |
| 71 | "shl{w}\t{%cl, $dst|$dst, CL}", |
| 72 | [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
| 73 | def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst), |
| 74 | "shl{l}\t{%cl, $dst|$dst, CL}", |
| 75 | [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 76 | def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 77 | "shl{q}\t{%cl, $dst|$dst, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 78 | [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 79 | } |
| 80 | def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src), |
| 81 | "shl{b}\t{$src, $dst|$dst, $src}", |
| 82 | [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
| 83 | def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src), |
| 84 | "shl{w}\t{$src, $dst|$dst, $src}", |
| 85 | [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 86 | OpSize; |
| 87 | def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src), |
| 88 | "shl{l}\t{$src, $dst|$dst, $src}", |
| 89 | [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 90 | def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src), |
| 91 | "shl{q}\t{$src, $dst|$dst, $src}", |
| 92 | [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 93 | |
| 94 | // Shift by 1 |
| 95 | def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst), |
| 96 | "shl{b}\t$dst", |
| 97 | [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
| 98 | def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst), |
| 99 | "shl{w}\t$dst", |
| 100 | [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 101 | OpSize; |
| 102 | def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst), |
| 103 | "shl{l}\t$dst", |
| 104 | [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 105 | def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst), |
| 106 | "shl{q}\t$dst", |
| 107 | [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 108 | |
| 109 | let Constraints = "$src1 = $dst" in { |
| 110 | let Uses = [CL] in { |
| 111 | def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 112 | "shr{b}\t{%cl, $dst|$dst, CL}", |
| 113 | [(set GR8:$dst, (srl GR8:$src1, CL))]>; |
| 114 | def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1), |
| 115 | "shr{w}\t{%cl, $dst|$dst, CL}", |
| 116 | [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize; |
| 117 | def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1), |
| 118 | "shr{l}\t{%cl, $dst|$dst, CL}", |
| 119 | [(set GR32:$dst, (srl GR32:$src1, CL))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 120 | def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 121 | "shr{q}\t{%cl, $dst|$dst, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 122 | [(set GR64:$dst, (srl GR64:$src1, CL))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 123 | } |
| 124 | |
| 125 | def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2), |
| 126 | "shr{b}\t{$src2, $dst|$dst, $src2}", |
| 127 | [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>; |
| 128 | def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
| 129 | "shr{w}\t{$src2, $dst|$dst, $src2}", |
| 130 | [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize; |
| 131 | def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
| 132 | "shr{l}\t{$src2, $dst|$dst, $src2}", |
| 133 | [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 134 | def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2), |
| 135 | "shr{q}\t{$src2, $dst|$dst, $src2}", |
| 136 | [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 137 | |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 138 | // Shift right by 1 |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 139 | def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1), |
| 140 | "shr{b}\t$dst", |
| 141 | [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>; |
| 142 | def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1), |
| 143 | "shr{w}\t$dst", |
| 144 | [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize; |
| 145 | def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1), |
| 146 | "shr{l}\t$dst", |
| 147 | [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 148 | def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1), |
| 149 | "shr{q}\t$dst", |
| 150 | [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 151 | } // Constraints = "$src = $dst" |
| 152 | |
| 153 | |
| 154 | let Uses = [CL] in { |
| 155 | def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst), |
| 156 | "shr{b}\t{%cl, $dst|$dst, CL}", |
| 157 | [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>; |
| 158 | def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst), |
| 159 | "shr{w}\t{%cl, $dst|$dst, CL}", |
| 160 | [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>, |
| 161 | OpSize; |
| 162 | def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst), |
| 163 | "shr{l}\t{%cl, $dst|$dst, CL}", |
| 164 | [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 165 | def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 166 | "shr{q}\t{%cl, $dst|$dst, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 167 | [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 168 | } |
| 169 | def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src), |
| 170 | "shr{b}\t{$src, $dst|$dst, $src}", |
| 171 | [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
| 172 | def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src), |
| 173 | "shr{w}\t{$src, $dst|$dst, $src}", |
| 174 | [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 175 | OpSize; |
| 176 | def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src), |
| 177 | "shr{l}\t{$src, $dst|$dst, $src}", |
| 178 | [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 179 | def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src), |
| 180 | "shr{q}\t{$src, $dst|$dst, $src}", |
| 181 | [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 182 | |
| 183 | // Shift by 1 |
| 184 | def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst), |
| 185 | "shr{b}\t$dst", |
| 186 | [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
| 187 | def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst), |
| 188 | "shr{w}\t$dst", |
| 189 | [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize; |
| 190 | def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst), |
| 191 | "shr{l}\t$dst", |
| 192 | [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 193 | def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst), |
| 194 | "shr{q}\t$dst", |
| 195 | [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 196 | |
| 197 | let Constraints = "$src1 = $dst" in { |
| 198 | let Uses = [CL] in { |
| 199 | def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 200 | "sar{b}\t{%cl, $dst|$dst, CL}", |
| 201 | [(set GR8:$dst, (sra GR8:$src1, CL))]>; |
| 202 | def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1), |
| 203 | "sar{w}\t{%cl, $dst|$dst, CL}", |
| 204 | [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize; |
| 205 | def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1), |
| 206 | "sar{l}\t{%cl, $dst|$dst, CL}", |
| 207 | [(set GR32:$dst, (sra GR32:$src1, CL))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 208 | def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 209 | "sar{q}\t{%cl, $dst|$dst, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 210 | [(set GR64:$dst, (sra GR64:$src1, CL))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 211 | } |
| 212 | |
| 213 | def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
| 214 | "sar{b}\t{$src2, $dst|$dst, $src2}", |
| 215 | [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>; |
| 216 | def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
| 217 | "sar{w}\t{$src2, $dst|$dst, $src2}", |
| 218 | [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>, |
| 219 | OpSize; |
| 220 | def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
| 221 | "sar{l}\t{$src2, $dst|$dst, $src2}", |
| 222 | [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 223 | def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), |
| 224 | (ins GR64:$src1, i8imm:$src2), |
| 225 | "sar{q}\t{$src2, $dst|$dst, $src2}", |
| 226 | [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 227 | |
| 228 | // Shift by 1 |
| 229 | def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 230 | "sar{b}\t$dst", |
| 231 | [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>; |
| 232 | def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1), |
| 233 | "sar{w}\t$dst", |
| 234 | [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize; |
| 235 | def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1), |
| 236 | "sar{l}\t$dst", |
| 237 | [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 238 | def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1), |
| 239 | "sar{q}\t$dst", |
| 240 | [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 241 | } // Constraints = "$src = $dst" |
| 242 | |
| 243 | |
| 244 | let Uses = [CL] in { |
| 245 | def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst), |
| 246 | "sar{b}\t{%cl, $dst|$dst, CL}", |
| 247 | [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>; |
| 248 | def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst), |
| 249 | "sar{w}\t{%cl, $dst|$dst, CL}", |
| 250 | [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
| 251 | def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst), |
| 252 | "sar{l}\t{%cl, $dst|$dst, CL}", |
| 253 | [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 254 | def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 255 | "sar{q}\t{%cl, $dst|$dst, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 256 | [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 257 | } |
| 258 | def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src), |
| 259 | "sar{b}\t{$src, $dst|$dst, $src}", |
| 260 | [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
| 261 | def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src), |
| 262 | "sar{w}\t{$src, $dst|$dst, $src}", |
| 263 | [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 264 | OpSize; |
| 265 | def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src), |
| 266 | "sar{l}\t{$src, $dst|$dst, $src}", |
| 267 | [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 268 | def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src), |
| 269 | "sar{q}\t{$src, $dst|$dst, $src}", |
| 270 | [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 271 | |
| 272 | // Shift by 1 |
| 273 | def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst), |
| 274 | "sar{b}\t$dst", |
| 275 | [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
| 276 | def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst), |
| 277 | "sar{w}\t$dst", |
| 278 | [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 279 | OpSize; |
| 280 | def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst), |
| 281 | "sar{l}\t$dst", |
| 282 | [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 283 | def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst), |
| 284 | "sar{q}\t$dst", |
| 285 | [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 286 | |
| 287 | //===----------------------------------------------------------------------===// |
| 288 | // Rotate instructions |
| 289 | //===----------------------------------------------------------------------===// |
| 290 | |
| 291 | let Constraints = "$src1 = $dst" in { |
| 292 | def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 293 | "rcl{b}\t$dst", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 294 | def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt), |
| 295 | "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 296 | let Uses = [CL] in |
| 297 | def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1), |
| 298 | "rcl{b}\t{%cl, $dst|$dst, CL}", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 299 | |
| 300 | def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 301 | "rcl{w}\t$dst", []>, OpSize; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 302 | def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt), |
| 303 | "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 304 | let Uses = [CL] in |
| 305 | def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1), |
| 306 | "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 307 | |
| 308 | def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 309 | "rcl{l}\t$dst", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 310 | def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt), |
| 311 | "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 312 | let Uses = [CL] in |
| 313 | def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1), |
| 314 | "rcl{l}\t{%cl, $dst|$dst, CL}", []>; |
| 315 | |
| 316 | |
| 317 | def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 318 | "rcl{q}\t$dst", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 319 | def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt), |
| 320 | "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 321 | let Uses = [CL] in |
| 322 | def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1), |
| 323 | "rcl{q}\t{%cl, $dst|$dst, CL}", []>; |
| 324 | |
| 325 | |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 326 | def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 327 | "rcr{b}\t$dst", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 328 | def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt), |
| 329 | "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 330 | let Uses = [CL] in |
| 331 | def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1), |
| 332 | "rcr{b}\t{%cl, $dst|$dst, CL}", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 333 | |
| 334 | def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 335 | "rcr{w}\t$dst", []>, OpSize; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 336 | def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt), |
| 337 | "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 338 | let Uses = [CL] in |
| 339 | def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1), |
| 340 | "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 341 | |
| 342 | def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 343 | "rcr{l}\t$dst", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 344 | def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt), |
| 345 | "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 346 | let Uses = [CL] in |
| 347 | def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1), |
| 348 | "rcr{l}\t{%cl, $dst|$dst, CL}", []>; |
| 349 | |
| 350 | def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 351 | "rcr{q}\t$dst", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 352 | def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt), |
| 353 | "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 354 | let Uses = [CL] in |
| 355 | def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1), |
| 356 | "rcr{q}\t{%cl, $dst|$dst, CL}", []>; |
| 357 | |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 358 | } // Constraints = "$src = $dst" |
| 359 | |
| 360 | def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 361 | "rcl{b}\t$dst", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 362 | def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt), |
| 363 | "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 364 | def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 365 | "rcl{w}\t$dst", []>, OpSize; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 366 | def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt), |
| 367 | "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
| 368 | def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 369 | "rcl{l}\t$dst", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 370 | def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt), |
| 371 | "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 372 | def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 373 | "rcl{q}\t$dst", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 374 | def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt), |
| 375 | "rcl{q}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 376 | |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 377 | def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 378 | "rcr{b}\t$dst", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 379 | def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt), |
| 380 | "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>; |
| 381 | def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 382 | "rcr{w}\t$dst", []>, OpSize; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 383 | def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt), |
| 384 | "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize; |
| 385 | def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 386 | "rcr{l}\t$dst", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 387 | def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt), |
| 388 | "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 389 | def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst), |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 390 | "rcr{q}\t$dst", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 391 | def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt), |
| 392 | "rcr{q}\t{$cnt, $dst|$dst, $cnt}", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 393 | |
| 394 | let Uses = [CL] in { |
| 395 | def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst), |
| 396 | "rcl{b}\t{%cl, $dst|$dst, CL}", []>; |
| 397 | def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst), |
| 398 | "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
| 399 | def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst), |
| 400 | "rcl{l}\t{%cl, $dst|$dst, CL}", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 401 | def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst), |
| 402 | "rcl{q}\t{%cl, $dst|$dst, CL}", []>; |
| 403 | |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 404 | def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst), |
| 405 | "rcr{b}\t{%cl, $dst|$dst, CL}", []>; |
| 406 | def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst), |
| 407 | "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize; |
| 408 | def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst), |
| 409 | "rcr{l}\t{%cl, $dst|$dst, CL}", []>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 410 | def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst), |
| 411 | "rcr{q}\t{%cl, $dst|$dst, CL}", []>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 412 | } |
| 413 | |
| 414 | let Constraints = "$src1 = $dst" in { |
| 415 | // FIXME: provide shorter instructions when imm8 == 1 |
| 416 | let Uses = [CL] in { |
| 417 | def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 418 | "rol{b}\t{%cl, $dst|$dst, CL}", |
| 419 | [(set GR8:$dst, (rotl GR8:$src1, CL))]>; |
| 420 | def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1), |
| 421 | "rol{w}\t{%cl, $dst|$dst, CL}", |
| 422 | [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize; |
| 423 | def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1), |
| 424 | "rol{l}\t{%cl, $dst|$dst, CL}", |
| 425 | [(set GR32:$dst, (rotl GR32:$src1, CL))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 426 | def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 427 | "rol{q}\t{%cl, $dst|$dst, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 428 | [(set GR64:$dst, (rotl GR64:$src1, CL))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 429 | } |
| 430 | |
| 431 | def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
| 432 | "rol{b}\t{$src2, $dst|$dst, $src2}", |
| 433 | [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>; |
| 434 | def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
| 435 | "rol{w}\t{$src2, $dst|$dst, $src2}", |
| 436 | [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, |
| 437 | OpSize; |
| 438 | def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
| 439 | "rol{l}\t{$src2, $dst|$dst, $src2}", |
| 440 | [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 441 | def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), |
| 442 | (ins GR64:$src1, i8imm:$src2), |
| 443 | "rol{q}\t{$src2, $dst|$dst, $src2}", |
| 444 | [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 445 | |
| 446 | // Rotate by 1 |
| 447 | def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 448 | "rol{b}\t$dst", |
| 449 | [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>; |
| 450 | def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1), |
| 451 | "rol{w}\t$dst", |
| 452 | [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize; |
| 453 | def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1), |
| 454 | "rol{l}\t$dst", |
| 455 | [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 456 | def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1), |
| 457 | "rol{q}\t$dst", |
| 458 | [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 459 | } // Constraints = "$src = $dst" |
| 460 | |
| 461 | let Uses = [CL] in { |
| 462 | def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst), |
| 463 | "rol{b}\t{%cl, $dst|$dst, CL}", |
| 464 | [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>; |
| 465 | def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst), |
| 466 | "rol{w}\t{%cl, $dst|$dst, CL}", |
| 467 | [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
| 468 | def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst), |
| 469 | "rol{l}\t{%cl, $dst|$dst, CL}", |
| 470 | [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 471 | def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 472 | "rol{q}\t{%cl, $dst|$dst, %cl}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 473 | [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 474 | } |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 475 | def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src1), |
| 476 | "rol{b}\t{$src1, $dst|$dst, $src1}", |
| 477 | [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)]>; |
| 478 | def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1), |
| 479 | "rol{w}\t{$src1, $dst|$dst, $src1}", |
| 480 | [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)]>, |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 481 | OpSize; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 482 | def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1), |
| 483 | "rol{l}\t{$src1, $dst|$dst, $src1}", |
| 484 | [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)]>; |
| 485 | def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1), |
| 486 | "rol{q}\t{$src1, $dst|$dst, $src1}", |
| 487 | [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 488 | |
| 489 | // Rotate by 1 |
| 490 | def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst), |
| 491 | "rol{b}\t$dst", |
| 492 | [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
| 493 | def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst), |
| 494 | "rol{w}\t$dst", |
| 495 | [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 496 | OpSize; |
| 497 | def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst), |
| 498 | "rol{l}\t$dst", |
| 499 | [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 500 | def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst), |
| 501 | "rol{q}\t$dst", |
| 502 | [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 503 | |
| 504 | let Constraints = "$src1 = $dst" in { |
| 505 | let Uses = [CL] in { |
| 506 | def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 507 | "ror{b}\t{%cl, $dst|$dst, CL}", |
| 508 | [(set GR8:$dst, (rotr GR8:$src1, CL))]>; |
| 509 | def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1), |
| 510 | "ror{w}\t{%cl, $dst|$dst, CL}", |
| 511 | [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize; |
| 512 | def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1), |
| 513 | "ror{l}\t{%cl, $dst|$dst, CL}", |
| 514 | [(set GR32:$dst, (rotr GR32:$src1, CL))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 515 | def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 516 | "ror{q}\t{%cl, $dst|$dst, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 517 | [(set GR64:$dst, (rotr GR64:$src1, CL))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 518 | } |
| 519 | |
| 520 | def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2), |
| 521 | "ror{b}\t{$src2, $dst|$dst, $src2}", |
| 522 | [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>; |
| 523 | def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2), |
| 524 | "ror{w}\t{$src2, $dst|$dst, $src2}", |
| 525 | [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, |
| 526 | OpSize; |
| 527 | def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2), |
| 528 | "ror{l}\t{$src2, $dst|$dst, $src2}", |
| 529 | [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 530 | def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), |
| 531 | (ins GR64:$src1, i8imm:$src2), |
| 532 | "ror{q}\t{$src2, $dst|$dst, $src2}", |
| 533 | [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 534 | |
| 535 | // Rotate by 1 |
| 536 | def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 537 | "ror{b}\t$dst", |
| 538 | [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>; |
| 539 | def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1), |
| 540 | "ror{w}\t$dst", |
| 541 | [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize; |
| 542 | def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1), |
| 543 | "ror{l}\t$dst", |
| 544 | [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 545 | def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1), |
| 546 | "ror{q}\t$dst", |
| 547 | [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 548 | } // Constraints = "$src = $dst" |
| 549 | |
| 550 | let Uses = [CL] in { |
| 551 | def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst), |
| 552 | "ror{b}\t{%cl, $dst|$dst, CL}", |
| 553 | [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>; |
| 554 | def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst), |
| 555 | "ror{w}\t{%cl, $dst|$dst, CL}", |
| 556 | [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize; |
| 557 | def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst), |
| 558 | "ror{l}\t{%cl, $dst|$dst, CL}", |
| 559 | [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 560 | def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 561 | "ror{q}\t{%cl, $dst|$dst, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 562 | [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 563 | } |
| 564 | def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src), |
| 565 | "ror{b}\t{$src, $dst|$dst, $src}", |
| 566 | [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
| 567 | def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src), |
| 568 | "ror{w}\t{$src, $dst|$dst, $src}", |
| 569 | [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>, |
| 570 | OpSize; |
| 571 | def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src), |
| 572 | "ror{l}\t{$src, $dst|$dst, $src}", |
| 573 | [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 574 | def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src), |
| 575 | "ror{q}\t{$src, $dst|$dst, $src}", |
| 576 | [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 577 | |
| 578 | // Rotate by 1 |
| 579 | def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst), |
| 580 | "ror{b}\t$dst", |
| 581 | [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>; |
| 582 | def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst), |
| 583 | "ror{w}\t$dst", |
| 584 | [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>, |
| 585 | OpSize; |
| 586 | def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst), |
| 587 | "ror{l}\t$dst", |
| 588 | [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 589 | def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst), |
| 590 | "ror{q}\t$dst", |
| 591 | [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 592 | |
| 593 | |
| 594 | //===----------------------------------------------------------------------===// |
| 595 | // Double shift instructions (generalizations of rotate) |
| 596 | //===----------------------------------------------------------------------===// |
| 597 | |
| 598 | let Constraints = "$src1 = $dst" in { |
| 599 | |
| 600 | let Uses = [CL] in { |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 601 | def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), |
| 602 | (ins GR16:$src1, GR16:$src2), |
| 603 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
| 604 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>, |
| 605 | TB, OpSize; |
| 606 | def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), |
| 607 | (ins GR16:$src1, GR16:$src2), |
| 608 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
| 609 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>, |
| 610 | TB, OpSize; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 611 | def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), |
| 612 | (ins GR32:$src1, GR32:$src2), |
| 613 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
| 614 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB; |
| 615 | def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), |
| 616 | (ins GR32:$src1, GR32:$src2), |
| 617 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
| 618 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB; |
| 619 | def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), |
| 620 | (ins GR64:$src1, GR64:$src2), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 621 | "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 622 | [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, |
| 623 | TB; |
| 624 | def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), |
| 625 | (ins GR64:$src1, GR64:$src2), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 626 | "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 627 | [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, |
| 628 | TB; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 629 | } |
| 630 | |
| 631 | let isCommutable = 1 in { // These instructions commute to each other. |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 632 | def SHLD16rri8 : Ii8<0xA4, MRMDestReg, |
| 633 | (outs GR16:$dst), |
| 634 | (ins GR16:$src1, GR16:$src2, i8imm:$src3), |
| 635 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 636 | [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, |
| 637 | (i8 imm:$src3)))]>, |
| 638 | TB, OpSize; |
| 639 | def SHRD16rri8 : Ii8<0xAC, MRMDestReg, |
| 640 | (outs GR16:$dst), |
| 641 | (ins GR16:$src1, GR16:$src2, i8imm:$src3), |
| 642 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 643 | [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, |
| 644 | (i8 imm:$src3)))]>, |
| 645 | TB, OpSize; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 646 | def SHLD32rri8 : Ii8<0xA4, MRMDestReg, |
| 647 | (outs GR32:$dst), |
| 648 | (ins GR32:$src1, GR32:$src2, i8imm:$src3), |
| 649 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 650 | [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, |
| 651 | (i8 imm:$src3)))]>, |
| 652 | TB; |
| 653 | def SHRD32rri8 : Ii8<0xAC, MRMDestReg, |
| 654 | (outs GR32:$dst), |
| 655 | (ins GR32:$src1, GR32:$src2, i8imm:$src3), |
| 656 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 657 | [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, |
| 658 | (i8 imm:$src3)))]>, |
| 659 | TB; |
| 660 | def SHLD64rri8 : RIi8<0xA4, MRMDestReg, |
| 661 | (outs GR64:$dst), |
| 662 | (ins GR64:$src1, GR64:$src2, i8imm:$src3), |
| 663 | "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 664 | [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, |
| 665 | (i8 imm:$src3)))]>, |
| 666 | TB; |
| 667 | def SHRD64rri8 : RIi8<0xAC, MRMDestReg, |
| 668 | (outs GR64:$dst), |
| 669 | (ins GR64:$src1, GR64:$src2, i8imm:$src3), |
| 670 | "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 671 | [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, |
| 672 | (i8 imm:$src3)))]>, |
| 673 | TB; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 674 | } |
| 675 | } // Constraints = "$src = $dst" |
| 676 | |
| 677 | let Uses = [CL] in { |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 678 | def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
| 679 | "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
| 680 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL), |
| 681 | addr:$dst)]>, TB, OpSize; |
| 682 | def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2), |
| 683 | "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
| 684 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL), |
| 685 | addr:$dst)]>, TB, OpSize; |
| 686 | |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 687 | def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
| 688 | "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
| 689 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL), |
| 690 | addr:$dst)]>, TB; |
| 691 | def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2), |
| 692 | "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
| 693 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL), |
| 694 | addr:$dst)]>, TB; |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 695 | |
| 696 | def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 697 | "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 698 | [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL), |
| 699 | addr:$dst)]>, TB; |
| 700 | def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2), |
Devang Patel | b1666b9 | 2012-01-03 18:22:10 +0000 | [diff] [blame^] | 701 | "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}", |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 702 | [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL), |
| 703 | addr:$dst)]>, TB; |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 704 | } |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 705 | |
| 706 | def SHLD16mri8 : Ii8<0xA4, MRMDestMem, |
| 707 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), |
| 708 | "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 709 | [(store (X86shld (loadi16 addr:$dst), GR16:$src2, |
| 710 | (i8 imm:$src3)), addr:$dst)]>, |
| 711 | TB, OpSize; |
| 712 | def SHRD16mri8 : Ii8<0xAC, MRMDestMem, |
| 713 | (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3), |
| 714 | "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 715 | [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, |
| 716 | (i8 imm:$src3)), addr:$dst)]>, |
| 717 | TB, OpSize; |
| 718 | |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 719 | def SHLD32mri8 : Ii8<0xA4, MRMDestMem, |
| 720 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), |
| 721 | "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 722 | [(store (X86shld (loadi32 addr:$dst), GR32:$src2, |
| 723 | (i8 imm:$src3)), addr:$dst)]>, |
| 724 | TB; |
| 725 | def SHRD32mri8 : Ii8<0xAC, MRMDestMem, |
| 726 | (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3), |
| 727 | "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 728 | [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, |
| 729 | (i8 imm:$src3)), addr:$dst)]>, |
| 730 | TB; |
| 731 | |
Chris Lattner | 5249ff3 | 2010-10-05 07:13:35 +0000 | [diff] [blame] | 732 | def SHLD64mri8 : RIi8<0xA4, MRMDestMem, |
| 733 | (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3), |
| 734 | "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 735 | [(store (X86shld (loadi64 addr:$dst), GR64:$src2, |
| 736 | (i8 imm:$src3)), addr:$dst)]>, |
| 737 | TB; |
| 738 | def SHRD64mri8 : RIi8<0xAC, MRMDestMem, |
| 739 | (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3), |
| 740 | "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}", |
| 741 | [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, |
| 742 | (i8 imm:$src3)), addr:$dst)]>, |
| 743 | TB; |
| 744 | |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 745 | } // Defs = [EFLAGS] |
| 746 | |
Craig Topper | 5679ec3 | 2011-10-23 22:18:24 +0000 | [diff] [blame] | 747 | multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> { |
| 748 | let neverHasSideEffects = 1 in { |
| 749 | def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2), |
| 750 | !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
| 751 | []>, TAXD, VEX; |
Craig Topper | 75485d6 | 2011-10-23 07:34:00 +0000 | [diff] [blame] | 752 | let mayLoad = 1 in |
Craig Topper | 5679ec3 | 2011-10-23 22:18:24 +0000 | [diff] [blame] | 753 | def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst), |
| 754 | (ins x86memop:$src1, i8imm:$src2), |
| 755 | !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
| 756 | []>, TAXD, VEX; |
| 757 | } |
| 758 | } |
Craig Topper | 75485d6 | 2011-10-23 07:34:00 +0000 | [diff] [blame] | 759 | |
Craig Topper | 5679ec3 | 2011-10-23 22:18:24 +0000 | [diff] [blame] | 760 | multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> { |
| 761 | let neverHasSideEffects = 1 in { |
| 762 | def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), |
| 763 | !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, |
| 764 | VEX_4VOp3; |
Craig Topper | 75485d6 | 2011-10-23 07:34:00 +0000 | [diff] [blame] | 765 | let mayLoad = 1 in |
Craig Topper | 5679ec3 | 2011-10-23 22:18:24 +0000 | [diff] [blame] | 766 | def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), |
| 767 | !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, |
| 768 | VEX_4VOp3; |
| 769 | } |
| 770 | } |
| 771 | |
| 772 | let Predicates = [HasBMI2] in { |
| 773 | defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>; |
| 774 | defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W; |
| 775 | defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS; |
| 776 | defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W; |
| 777 | defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD; |
| 778 | defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W; |
| 779 | defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8, OpSize; |
| 780 | defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8, OpSize, VEX_W; |
Craig Topper | 75485d6 | 2011-10-23 07:34:00 +0000 | [diff] [blame] | 781 | } |