| Arnold Schwaighofer | 373e865 | 2007-10-12 21:30:57 +0000 | [diff] [blame] | 1 | //===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===// |
| Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| Chris Lattner | 081ce94 | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This is a target description file for the Intel i386 architecture, refered to |
| 11 | // here as the "X86" architecture. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | // Get the target-independent interfaces which we are implementing... |
| 16 | // |
| 17 | include "../Target.td" |
| 18 | |
| 19 | //===----------------------------------------------------------------------===// |
| 20 | // X86 Subtarget features. |
| 21 | //===----------------------------------------------------------------------===// |
| 22 | |
| 23 | def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", |
| 24 | "Enable MMX instructions">; |
| 25 | def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", |
| 26 | "Enable SSE instructions", |
| 27 | [FeatureMMX]>; |
| 28 | def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", |
| 29 | "Enable SSE2 instructions", |
| 30 | [FeatureSSE1]>; |
| 31 | def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", |
| 32 | "Enable SSE3 instructions", |
| 33 | [FeatureSSE2]>; |
| 34 | def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", |
| 35 | "Enable SSSE3 instructions", |
| 36 | [FeatureSSE3]>; |
| Nate Begeman | b297556 | 2008-02-03 07:18:54 +0000 | [diff] [blame^] | 37 | def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41", |
| 38 | "Enable SSE 4.1 instructions", |
| 39 | [FeatureSSSE3]>; |
| 40 | def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42", |
| 41 | "Enable SSE 4.2 instructions", |
| 42 | [FeatureSSE41]>; |
| Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 43 | def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", |
| 44 | "Enable 3DNow! instructions">; |
| 45 | def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", |
| 46 | "Enable 3DNow! Athlon instructions", |
| 47 | [Feature3DNow]>; |
| 48 | def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", |
| 49 | "Support 64-bit instructions", |
| 50 | [FeatureSSE2]>; |
| 51 | |
| 52 | //===----------------------------------------------------------------------===// |
| 53 | // X86 processors supported. |
| 54 | //===----------------------------------------------------------------------===// |
| 55 | |
| 56 | class Proc<string Name, list<SubtargetFeature> Features> |
| 57 | : Processor<Name, NoItineraries, Features>; |
| 58 | |
| 59 | def : Proc<"generic", []>; |
| 60 | def : Proc<"i386", []>; |
| 61 | def : Proc<"i486", []>; |
| 62 | def : Proc<"pentium", []>; |
| 63 | def : Proc<"pentium-mmx", [FeatureMMX]>; |
| 64 | def : Proc<"i686", []>; |
| 65 | def : Proc<"pentiumpro", []>; |
| 66 | def : Proc<"pentium2", [FeatureMMX]>; |
| 67 | def : Proc<"pentium3", [FeatureSSE1]>; |
| 68 | def : Proc<"pentium-m", [FeatureSSE2]>; |
| 69 | def : Proc<"pentium4", [FeatureSSE2]>; |
| 70 | def : Proc<"x86-64", [Feature64Bit]>; |
| 71 | def : Proc<"yonah", [FeatureSSE3]>; |
| 72 | def : Proc<"prescott", [FeatureSSE3]>; |
| 73 | def : Proc<"nocona", [FeatureSSE3]>; |
| 74 | def : Proc<"core2", [FeatureSSSE3]>; |
| Nate Begeman | b297556 | 2008-02-03 07:18:54 +0000 | [diff] [blame^] | 75 | def : Proc<"penryn", [FeatureSSE41]>; |
| Dan Gohman | f17a25c | 2007-07-18 16:29:46 +0000 | [diff] [blame] | 76 | |
| 77 | def : Proc<"k6", [FeatureMMX]>; |
| 78 | def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>; |
| 79 | def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>; |
| 80 | def : Proc<"athlon", [FeatureMMX, Feature3DNowA]>; |
| 81 | def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA]>; |
| 82 | def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA]>; |
| 83 | def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA]>; |
| 84 | def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA]>; |
| 85 | def : Proc<"k8", [Feature3DNowA, Feature64Bit]>; |
| 86 | def : Proc<"opteron", [Feature3DNowA, Feature64Bit]>; |
| 87 | def : Proc<"athlon64", [Feature3DNowA, Feature64Bit]>; |
| 88 | def : Proc<"athlon-fx", [Feature3DNowA, Feature64Bit]>; |
| 89 | |
| 90 | def : Proc<"winchip-c6", [FeatureMMX]>; |
| 91 | def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>; |
| 92 | def : Proc<"c3", [FeatureMMX, Feature3DNow]>; |
| 93 | def : Proc<"c3-2", [FeatureSSE1]>; |
| 94 | |
| 95 | //===----------------------------------------------------------------------===// |
| 96 | // Register File Description |
| 97 | //===----------------------------------------------------------------------===// |
| 98 | |
| 99 | include "X86RegisterInfo.td" |
| 100 | |
| 101 | //===----------------------------------------------------------------------===// |
| 102 | // Instruction Descriptions |
| 103 | //===----------------------------------------------------------------------===// |
| 104 | |
| 105 | include "X86InstrInfo.td" |
| 106 | |
| 107 | def X86InstrInfo : InstrInfo { |
| 108 | |
| 109 | // Define how we want to layout our TargetSpecific information field... This |
| 110 | // should be kept up-to-date with the fields in the X86InstrInfo.h file. |
| 111 | let TSFlagsFields = ["FormBits", |
| 112 | "hasOpSizePrefix", |
| 113 | "hasAdSizePrefix", |
| 114 | "Prefix", |
| 115 | "hasREX_WPrefix", |
| 116 | "ImmTypeBits", |
| 117 | "FPFormBits", |
| 118 | "Opcode"]; |
| 119 | let TSFlagsShifts = [0, |
| 120 | 6, |
| 121 | 7, |
| 122 | 8, |
| 123 | 12, |
| 124 | 13, |
| 125 | 16, |
| 126 | 24]; |
| 127 | } |
| 128 | |
| 129 | //===----------------------------------------------------------------------===// |
| 130 | // Calling Conventions |
| 131 | //===----------------------------------------------------------------------===// |
| 132 | |
| 133 | include "X86CallingConv.td" |
| 134 | |
| 135 | |
| 136 | //===----------------------------------------------------------------------===// |
| 137 | // Assembly Printers |
| 138 | //===----------------------------------------------------------------------===// |
| 139 | |
| 140 | // The X86 target supports two different syntaxes for emitting machine code. |
| 141 | // This is controlled by the -x86-asm-syntax={att|intel} |
| 142 | def ATTAsmWriter : AsmWriter { |
| 143 | string AsmWriterClassName = "ATTAsmPrinter"; |
| 144 | int Variant = 0; |
| 145 | } |
| 146 | def IntelAsmWriter : AsmWriter { |
| 147 | string AsmWriterClassName = "IntelAsmPrinter"; |
| 148 | int Variant = 1; |
| 149 | } |
| 150 | |
| 151 | |
| 152 | def X86 : Target { |
| 153 | // Information about the instructions... |
| 154 | let InstructionSet = X86InstrInfo; |
| 155 | |
| 156 | let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; |
| 157 | } |