Mon P Wang | bc3c526 | 2009-09-03 19:57:35 +0000 | [diff] [blame^] | 1 | ; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s |
Mon P Wang | 576beb2 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 2 | ; RUN: grep psllq %t | count 1 |
| 3 | ; RUN: grep pslld %t | count 3 |
| 4 | ; RUN: grep psllw %t | count 2 |
| 5 | |
| 6 | ; test vector shifts converted to proper SSE2 vector shifts when the shift |
| 7 | ; amounts are the same when using a shuffle splat. |
| 8 | |
| 9 | define void @shift1a(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind { |
| 10 | entry: |
Mon P Wang | bc3c526 | 2009-09-03 19:57:35 +0000 | [diff] [blame^] | 11 | ; CHECK: shift1a: |
| 12 | ; CHECK: psllq |
Mon P Wang | 576beb2 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 13 | %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0> |
| 14 | %shl = shl <2 x i64> %val, %shamt |
| 15 | store <2 x i64> %shl, <2 x i64>* %dst |
| 16 | ret void |
| 17 | } |
| 18 | |
Mon P Wang | bc3c526 | 2009-09-03 19:57:35 +0000 | [diff] [blame^] | 19 | ; shift1b can't use a packed shift |
Mon P Wang | 576beb2 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 20 | define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind { |
| 21 | entry: |
Mon P Wang | bc3c526 | 2009-09-03 19:57:35 +0000 | [diff] [blame^] | 22 | ; CHECK: shift1b: |
| 23 | ; CHECK: shll |
Mon P Wang | 576beb2 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 24 | %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1> |
| 25 | %shl = shl <2 x i64> %val, %shamt |
| 26 | store <2 x i64> %shl, <2 x i64>* %dst |
| 27 | ret void |
| 28 | } |
| 29 | |
| 30 | define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind { |
| 31 | entry: |
Mon P Wang | bc3c526 | 2009-09-03 19:57:35 +0000 | [diff] [blame^] | 32 | ; CHECK: shift2a: |
| 33 | ; CHECK: pslld |
Mon P Wang | 576beb2 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 34 | %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> |
| 35 | %shl = shl <4 x i32> %val, %shamt |
| 36 | store <4 x i32> %shl, <4 x i32>* %dst |
| 37 | ret void |
| 38 | } |
| 39 | |
| 40 | define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind { |
| 41 | entry: |
Mon P Wang | bc3c526 | 2009-09-03 19:57:35 +0000 | [diff] [blame^] | 42 | ; CHECK: shift2b: |
| 43 | ; CHECK: pslld |
Mon P Wang | 576beb2 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 44 | %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1> |
| 45 | %shl = shl <4 x i32> %val, %shamt |
| 46 | store <4 x i32> %shl, <4 x i32>* %dst |
| 47 | ret void |
| 48 | } |
| 49 | |
| 50 | define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind { |
| 51 | entry: |
Mon P Wang | bc3c526 | 2009-09-03 19:57:35 +0000 | [diff] [blame^] | 52 | ; CHECK: shift2c: |
| 53 | ; CHECK: pslld |
Mon P Wang | 576beb2 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 54 | %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> |
| 55 | %shl = shl <4 x i32> %val, %shamt |
| 56 | store <4 x i32> %shl, <4 x i32>* %dst |
| 57 | ret void |
| 58 | } |
| 59 | |
| 60 | define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind { |
| 61 | entry: |
Mon P Wang | bc3c526 | 2009-09-03 19:57:35 +0000 | [diff] [blame^] | 62 | ; CHECK: shift3a: |
| 63 | ; CHECK: movzwl |
| 64 | ; CHECK: psllw |
Mon P Wang | 576beb2 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 65 | %shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6> |
| 66 | %shl = shl <8 x i16> %val, %shamt |
| 67 | store <8 x i16> %shl, <8 x i16>* %dst |
| 68 | ret void |
| 69 | } |
| 70 | |
| 71 | define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind { |
| 72 | entry: |
Mon P Wang | bc3c526 | 2009-09-03 19:57:35 +0000 | [diff] [blame^] | 73 | ; CHECK: shift3b: |
| 74 | ; CHECK: movzwl |
| 75 | ; CHECK: psllw |
Mon P Wang | 576beb2 | 2009-01-28 08:13:56 +0000 | [diff] [blame] | 76 | %0 = insertelement <8 x i16> undef, i16 %amt, i32 0 |
| 77 | %1 = insertelement <8 x i16> %0, i16 %amt, i32 1 |
| 78 | %2 = insertelement <8 x i16> %0, i16 %amt, i32 2 |
| 79 | %3 = insertelement <8 x i16> %0, i16 %amt, i32 3 |
| 80 | %4 = insertelement <8 x i16> %0, i16 %amt, i32 4 |
| 81 | %5 = insertelement <8 x i16> %0, i16 %amt, i32 5 |
| 82 | %6 = insertelement <8 x i16> %0, i16 %amt, i32 6 |
| 83 | %7 = insertelement <8 x i16> %0, i16 %amt, i32 7 |
| 84 | %shl = shl <8 x i16> %val, %7 |
| 85 | store <8 x i16> %shl, <8 x i16>* %dst |
| 86 | ret void |
| 87 | } |
| 88 | |