Dan Gohman | bcea859 | 2009-10-10 01:32:21 +0000 | [diff] [blame^] | 1 | //===---- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG class ---==// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This declares the Emit routines for the SelectionDAG class, which creates |
| 11 | // MachineInstrs based on the decisions of the SelectionDAG instruction |
| 12 | // selection. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
| 16 | #ifndef INSTREMITTER_H |
| 17 | #define INSTREMITTER_H |
| 18 | |
| 19 | #include "llvm/CodeGen/SelectionDAG.h" |
| 20 | #include "llvm/CodeGen/MachineBasicBlock.h" |
| 21 | #include "llvm/ADT/DenseMap.h" |
| 22 | |
| 23 | namespace llvm { |
| 24 | |
| 25 | class TargetInstrDesc; |
| 26 | |
| 27 | class InstrEmitter { |
| 28 | MachineFunction *MF; |
| 29 | MachineRegisterInfo *MRI; |
| 30 | const TargetMachine *TM; |
| 31 | const TargetInstrInfo *TII; |
| 32 | const TargetRegisterInfo *TRI; |
| 33 | const TargetLowering *TLI; |
| 34 | |
| 35 | MachineBasicBlock *MBB; |
| 36 | MachineBasicBlock::iterator InsertPos; |
| 37 | |
| 38 | /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an |
| 39 | /// implicit physical register output. |
| 40 | void EmitCopyFromReg(SDNode *Node, unsigned ResNo, |
| 41 | bool IsClone, bool IsCloned, |
| 42 | unsigned SrcReg, |
| 43 | DenseMap<SDValue, unsigned> &VRBaseMap); |
| 44 | |
| 45 | /// getDstOfCopyToRegUse - If the only use of the specified result number of |
| 46 | /// node is a CopyToReg, return its destination register. Return 0 otherwise. |
| 47 | unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, |
| 48 | unsigned ResNo) const; |
| 49 | |
| 50 | void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, |
| 51 | const TargetInstrDesc &II, |
| 52 | bool IsClone, bool IsCloned, |
| 53 | DenseMap<SDValue, unsigned> &VRBaseMap); |
| 54 | |
| 55 | /// getVR - Return the virtual register corresponding to the specified result |
| 56 | /// of the specified node. |
| 57 | unsigned getVR(SDValue Op, |
| 58 | DenseMap<SDValue, unsigned> &VRBaseMap); |
| 59 | |
| 60 | /// AddRegisterOperand - Add the specified register as an operand to the |
| 61 | /// specified machine instr. Insert register copies if the register is |
| 62 | /// not in the required register class. |
| 63 | void AddRegisterOperand(MachineInstr *MI, SDValue Op, |
| 64 | unsigned IIOpNum, |
| 65 | const TargetInstrDesc *II, |
| 66 | DenseMap<SDValue, unsigned> &VRBaseMap); |
| 67 | |
| 68 | /// AddOperand - Add the specified operand to the specified machine instr. II |
| 69 | /// specifies the instruction information for the node, and IIOpNum is the |
| 70 | /// operand number (in the II) that we are adding. IIOpNum and II are used for |
| 71 | /// assertions only. |
| 72 | void AddOperand(MachineInstr *MI, SDValue Op, |
| 73 | unsigned IIOpNum, |
| 74 | const TargetInstrDesc *II, |
| 75 | DenseMap<SDValue, unsigned> &VRBaseMap); |
| 76 | |
| 77 | /// EmitSubregNode - Generate machine code for subreg nodes. |
| 78 | /// |
| 79 | void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap); |
| 80 | |
| 81 | /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. |
| 82 | /// COPY_TO_REGCLASS is just a normal copy, except that the destination |
| 83 | /// register is constrained to be in a particular register class. |
| 84 | /// |
| 85 | void EmitCopyToRegClassNode(SDNode *Node, |
| 86 | DenseMap<SDValue, unsigned> &VRBaseMap); |
| 87 | |
| 88 | public: |
| 89 | /// CountResults - The results of target nodes have register or immediate |
| 90 | /// operands first, then an optional chain, and optional flag operands |
| 91 | /// (which do not go into the machine instrs.) |
| 92 | static unsigned CountResults(SDNode *Node); |
| 93 | |
| 94 | /// CountOperands - The inputs to target nodes have any actual inputs first, |
| 95 | /// followed by an optional chain operand, then flag operands. Compute |
| 96 | /// the number of actual operands that will go into the resulting |
| 97 | /// MachineInstr. |
| 98 | static unsigned CountOperands(SDNode *Node); |
| 99 | |
| 100 | /// EmitNode - Generate machine code for an node and needed dependencies. |
| 101 | /// |
| 102 | void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, |
| 103 | DenseMap<SDValue, unsigned> &VRBaseMap, |
| 104 | DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM); |
| 105 | |
| 106 | /// getBlock - Return the current basic block. |
| 107 | MachineBasicBlock *getBlock() { return MBB; } |
| 108 | |
| 109 | /// getInsertPos - Return the current insertion position. |
| 110 | MachineBasicBlock::iterator getInsertPos() { return InsertPos; } |
| 111 | |
| 112 | /// InstrEmitter - Construct an InstrEmitter and set it to start inserting |
| 113 | /// at the given position in the given block. |
| 114 | InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos); |
| 115 | }; |
| 116 | |
| 117 | } |
| 118 | |
| 119 | #endif |