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Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00001//===- MipsInstrFPU.td - Mips FPU Instruction Information -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Mips implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7b76da12008-07-09 04:45:36 +000015// Floating Point Instructions
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000016// ------------------------
17// * 64bit fp:
18// - 32 64-bit registers (default mode)
19// - 16 even 32-bit registers (32-bit compatible mode) for
20// single and double access.
21// * 32bit fp:
22// - 16 even 32-bit registers - single and double (aliased)
23// - 32 32-bit registers (within single-only mode)
24//===----------------------------------------------------------------------===//
25
Bruno Cardoso Lopes7b76da12008-07-09 04:45:36 +000026// Floating Point Compare and Branch
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000027def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisSameAs<0, 2>, SDTCisInt<0>,
28 SDTCisVT<1, OtherVT>]>;
29def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<0>,
30 SDTCisInt<2>]>;
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +000031def SDT_MipsFPSelectCC : SDTypeProfile<1, 4, [SDTCisInt<1>, SDTCisInt<4>,
32 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000033def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
34 [SDNPHasChain]>;
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +000035def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp>;
36def MipsFPSelectCC : SDNode<"MipsISD::FPSelectCC", SDT_MipsFPSelectCC>;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000037
38// Operand for printing out a condition code.
39let PrintMethod = "printFCCOperand" in
40 def condcode : Operand<i32>;
41
42//===----------------------------------------------------------------------===//
43// Feature predicates.
44//===----------------------------------------------------------------------===//
45
46def In32BitMode : Predicate<"!Subtarget.isFP64bit()">;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000047def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
48def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
49
50//===----------------------------------------------------------------------===//
51// Instruction Class Templates
52//
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +000053// A set of multiclasses is used to address the register usage.
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000054//
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +000055// S32 - single precision in 16 32bit even fp registers
56// single precision in 32 32bit fp registers in SingleOnly mode
57// S64 - single precision in 32 64bit fp registers (In64BitMode)
58// D32 - double precision in 16 32bit even fp registers
59// D64 - double precision in 32 64bit fp registers (In64BitMode)
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000060//
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +000061// Only S32 and D32 are supported right now.
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000062//===----------------------------------------------------------------------===//
63
64multiclass FFR1_1<bits<6> funct, string asmstr>
65{
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +000066 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
67 !strconcat(asmstr, ".s $fd, $fs"), []>;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000068
69 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
70 !strconcat(asmstr, ".d $fd, $fs"), []>, Requires<[In32BitMode]>;
71}
72
73multiclass FFR1_2<bits<6> funct, string asmstr, SDNode FOp>
74{
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +000075 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000076 !strconcat(asmstr, ".s $fd, $fs"),
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +000077 [(set FGR32:$fd, (FOp FGR32:$fs))]>;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000078
79 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
80 !strconcat(asmstr, ".d $fd, $fs"),
81 [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>;
82}
83
84class FFR1_3<bits<6> funct, bits<5> fmt, RegisterClass RcSrc,
85 RegisterClass RcDst, string asmstr>:
86 FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
87 !strconcat(asmstr, " $fd, $fs"), []>;
88
89
90multiclass FFR1_4<bits<6> funct, string asmstr, SDNode FOp> {
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +000091 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
Bruno Cardoso Lopes7b76da12008-07-09 04:45:36 +000092 (ins FGR32:$fs, FGR32:$ft),
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000093 !strconcat(asmstr, ".s $fd, $fs, $ft"),
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +000094 [(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000095
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +000096 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000097 (ins AFGR64:$fs, AFGR64:$ft),
98 !strconcat(asmstr, ".d $fd, $fs, $ft"),
99 [(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
100 Requires<[In32BitMode]>;
101}
102
103//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7b76da12008-07-09 04:45:36 +0000104// Floating Point Instructions
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000105//===----------------------------------------------------------------------===//
106
107let ft = 0 in {
108 defm FLOOR_W : FFR1_1<0b001111, "floor.w">;
109 defm CEIL_W : FFR1_1<0b001110, "ceil.w">;
110 defm ROUND_W : FFR1_1<0b001100, "round.w">;
111 defm TRUNC_W : FFR1_1<0b001101, "trunc.w">;
112 defm CVTW : FFR1_1<0b100100, "cvt.w">;
113 defm FMOV : FFR1_1<0b000110, "mov">;
114
115 defm FABS : FFR1_2<0b000101, "abs", fabs>;
116 defm FNEG : FFR1_2<0b000111, "neg", fneg>;
117 defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
118
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000119 /// Convert to Single Precison
120 def CVTS_W32 : FFR1_3<0b100000, 0x2, FGR32, FGR32, "cvt.s.w">;
121
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000122 let Predicates = [IsNotSingleFloat] in {
123 /// Ceil to long signed integer
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000124 def CEIL_LS : FFR1_3<0b001010, 0x0, FGR32, FGR32, "ceil.l">;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000125 def CEIL_LD : FFR1_3<0b001010, 0x1, AFGR64, AFGR64, "ceil.l">;
126
127 /// Round to long signed integer
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000128 def ROUND_LS : FFR1_3<0b001000, 0x0, FGR32, FGR32, "round.l">;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000129 def ROUND_LD : FFR1_3<0b001000, 0x1, AFGR64, AFGR64, "round.l">;
130
131 /// Floor to long signed integer
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000132 def FLOOR_LS : FFR1_3<0b001011, 0x0, FGR32, FGR32, "floor.l">;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000133 def FLOOR_LD : FFR1_3<0b001011, 0x1, AFGR64, AFGR64, "floor.l">;
134
135 /// Trunc to long signed integer
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000136 def TRUNC_LS : FFR1_3<0b001001, 0x0, FGR32, FGR32, "trunc.l">;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000137 def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
138
139 /// Convert to long signed integer
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000140 def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000141 def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
142
143 /// Convert to Double Precison
144 def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
145 def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
146 def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
147
148 /// Convert to Single Precison
149 def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
150 def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
151 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000152}
153
154// The odd-numbered registers are only referenced when doing loads,
155// stores, and moves between floating-point and integer registers.
156// When defining instructions, we reference all 32-bit registers,
157// regardless of register aliasing.
158let fd = 0 in {
159 /// Move Control Registers From/To CPU Registers
160 ///def CFC1 : FFR<0x11, 0x0, 0x2, (outs CPURegs:$rt), (ins FGR32:$fs),
161 /// "cfc1 $rt, $fs", []>;
162
163 ///def CTC1 : FFR<0x11, 0x0, 0x6, (outs CPURegs:$rt), (ins FGR32:$fs),
164 /// "ctc1 $rt, $fs", []>;
165 ///
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000166 def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
167 "mfc1 $rt, $fs", []>;
168
169 def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt),
Bruno Cardoso Lopes7030ae72008-07-30 19:00:31 +0000170 "mtc1 $rt, $fs", []>;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000171}
172
Bruno Cardoso Lopes7b76da12008-07-09 04:45:36 +0000173/// Floating Point Memory Instructions
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000174let Predicates = [IsNotSingleFloat] in {
175 def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
176 "ldc1 $ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
177
178 def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr),
179 "sdc1 $ft, $addr", [(store AFGR64:$ft, addr:$addr)]>;
180}
181
182// LWC1 and SWC1 can always be emited with odd registers.
183def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
184 [(set FGR32:$ft, (load addr:$addr))]>;
185def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr",
186 [(store FGR32:$ft, addr:$addr)]>;
187
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000188/// Floating-point Aritmetic
189defm FADD : FFR1_4<0x10, "add", fadd>;
190defm FDIV : FFR1_4<0x03, "div", fdiv>;
191defm FMUL : FFR1_4<0x02, "mul", fmul>;
192defm FSUB : FFR1_4<0x01, "sub", fsub>;
193
194//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7b76da12008-07-09 04:45:36 +0000195// Floating Point Branch Codes
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000196//===----------------------------------------------------------------------===//
197// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
198// They must be kept in synch.
199def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
200def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
201def MIPS_BRANCH_FL : PatLeaf<(i32 2)>;
202def MIPS_BRANCH_TL : PatLeaf<(i32 3)>;
203
Bruno Cardoso Lopes7b76da12008-07-09 04:45:36 +0000204/// Floating Point Branch of False/True (Likely)
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000205let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in {
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000206 class FBRANCH<PatLeaf op, string asmstr> : FFI<0x11, (outs),
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000207 (ins brtarget:$dst), !strconcat(asmstr, " $dst"),
208 [(MipsFPBrcond op, bb:$dst, FCR31)]>;
209}
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000210def BC1F : FBRANCH<MIPS_BRANCH_F, "bc1f">;
211def BC1T : FBRANCH<MIPS_BRANCH_T, "bc1t">;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000212def BC1FL : FBRANCH<MIPS_BRANCH_FL, "bc1fl">;
213def BC1TL : FBRANCH<MIPS_BRANCH_TL, "bc1tl">;
214
215//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7b76da12008-07-09 04:45:36 +0000216// Floating Point Flag Conditions
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000217//===----------------------------------------------------------------------===//
218// Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
219// They must be kept in synch.
220def MIPS_FCOND_F : PatLeaf<(i32 0)>;
221def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
222def MIPS_FCOND_EQ : PatLeaf<(i32 2)>;
223def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>;
224def MIPS_FCOND_OLT : PatLeaf<(i32 4)>;
225def MIPS_FCOND_ULT : PatLeaf<(i32 5)>;
226def MIPS_FCOND_OLE : PatLeaf<(i32 6)>;
227def MIPS_FCOND_ULE : PatLeaf<(i32 7)>;
228def MIPS_FCOND_SF : PatLeaf<(i32 8)>;
229def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>;
230def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>;
231def MIPS_FCOND_NGL : PatLeaf<(i32 11)>;
232def MIPS_FCOND_LT : PatLeaf<(i32 12)>;
233def MIPS_FCOND_NGE : PatLeaf<(i32 13)>;
234def MIPS_FCOND_LE : PatLeaf<(i32 14)>;
235def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
236
237/// Floating Point Compare
238let hasDelaySlot = 1, Defs=[FCR31] in {
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000239 def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000240 "c.$cc.s $fs, $ft", [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc),
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000241 (implicit FCR31)]>;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000242
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000243 def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000244 "c.$cc.d $fs, $ft", [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc),
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000245 (implicit FCR31)]>, Requires<[In32BitMode]>;
246}
247
248//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000249// Floating Point Pseudo-Instructions
250//===----------------------------------------------------------------------===//
251
252// For some explanation, see Select_CC at MipsInstrInfo.td. We also embedd a
253// condiciton code to enable easy handling by the Custom Inserter.
254let usesCustomDAGSchedInserter = 1, Uses=[FCR31] in {
255 class PseudoFPSelCC<RegisterClass RC, string asmstr> :
256 MipsPseudo<(outs RC:$dst),
257 (ins CPURegs:$CmpRes, RC:$T, RC:$F, condcode:$cc), asmstr,
258 [(set RC:$dst, (MipsFPSelectCC CPURegs:$CmpRes, RC:$T, RC:$F,
259 imm:$cc))]>;
260}
261
262// The values to be selected are fp but the condition test is with integers.
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000263def Select_CC_S32 : PseudoSelCC<FGR32, "# MipsSelect_CC_S32_f32">;
264def Select_CC_D32 : PseudoSelCC<AFGR64, "# MipsSelect_CC_D32_f32">,
265 Requires<[In32BitMode]>;
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000266
267// The values to be selected are int but the condition test is done with fp.
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000268def Select_FCC : PseudoFPSelCC<CPURegs, "# MipsSelect_FCC">;
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000269
270// The values to be selected and the condition test is done with fp.
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000271def Select_FCC_S32 : PseudoFPSelCC<FGR32, "# MipsSelect_FCC_S32_f32">;
272def Select_FCC_D32 : PseudoFPSelCC<AFGR64, "# MipsSelect_FCC_D32_f32">,
273 Requires<[In32BitMode]>;
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000274
275//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7b76da12008-07-09 04:45:36 +0000276// Floating Point Patterns
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000277//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes7030ae72008-07-30 19:00:31 +0000278def fpimm0 : PatLeaf<(fpimm), [{
279 return N->isExactlyValue(+0.0);
280}]>;
281
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000282def : Pat<(f32 fpimm0), (MTC1 ZERO)>;
Bruno Cardoso Lopes7030ae72008-07-30 19:00:31 +0000283
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000284def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>;
285def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>;
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000286
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000287def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S32 FGR32:$src))>;
Bruno Cardoso Lopes7030ae72008-07-30 19:00:31 +0000288
289def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>;
Bruno Cardoso Lopesbdfbb742009-03-21 00:05:07 +0000290def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>;