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Jia Liu31d157a2012-02-18 12:03:15 +00001//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
Tony Linthicumb4b54152011-12-12 21:14:40 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the Hexagon specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonSubtarget.h"
15#include "Hexagon.h"
Sirish Pande7517bbc2012-05-10 20:20:25 +000016#include "HexagonRegisterInfo.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +000017#include "llvm/Support/CommandLine.h"
18#include "llvm/Support/ErrorHandling.h"
19using namespace llvm;
20
Tony Linthicumb4b54152011-12-12 21:14:40 +000021#define GET_SUBTARGETINFO_CTOR
22#define GET_SUBTARGETINFO_TARGET_DESC
23#include "HexagonGenSubtargetInfo.inc"
24
25static cl::opt<bool>
26EnableV3("enable-hexagon-v3", cl::Hidden,
27 cl::desc("Enable Hexagon V3 instructions."));
28
29static cl::opt<bool>
30EnableMemOps(
31 "enable-hexagon-memops",
32 cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed,
Sirish Pande7517bbc2012-05-10 20:20:25 +000033 cl::desc("Generate V4 memop instructions."));
34
35static cl::opt<bool>
36EnableIEEERndNear(
37 "enable-hexagon-ieee-rnd-near",
38 cl::Hidden, cl::ZeroOrMore, cl::init(false),
39 cl::desc("Generate non-chopped conversion from fp to int."));
Tony Linthicumb4b54152011-12-12 21:14:40 +000040
41HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
42 HexagonGenSubtargetInfo(TT, CPU, FS),
Sirish Pandeb3385702012-05-12 05:10:30 +000043 HexagonArchVersion(V2),
Tony Linthicumb4b54152011-12-12 21:14:40 +000044 CPUString(CPU.str()) {
45 ParseSubtargetFeatures(CPU, FS);
46
47 switch(HexagonArchVersion) {
48 case HexagonSubtarget::V2:
49 break;
50 case HexagonSubtarget::V3:
51 EnableV3 = true;
52 break;
53 case HexagonSubtarget::V4:
54 break;
Sirish Pande7517bbc2012-05-10 20:20:25 +000055 case HexagonSubtarget::V5:
56 break;
Tony Linthicumb4b54152011-12-12 21:14:40 +000057 default:
Sebastian Pope88ed092012-07-19 18:24:50 +000058 // If the programmer has not specified a Hexagon version, default
59 // to -mv4.
60 CPUString = "hexagonv4";
61 HexagonArchVersion = HexagonSubtarget::V4;
62 break;
Tony Linthicumb4b54152011-12-12 21:14:40 +000063 }
64
65 // Initialize scheduling itinerary for the specified CPU.
66 InstrItins = getInstrItineraryForCPU(CPUString);
67
Tony Linthicumb4b54152011-12-12 21:14:40 +000068 if (EnableMemOps)
69 UseMemOps = true;
70 else
71 UseMemOps = false;
Sirish Pande7517bbc2012-05-10 20:20:25 +000072
73 if (EnableIEEERndNear)
74 ModeIEEERndNear = true;
75 else
76 ModeIEEERndNear = false;
Tony Linthicumb4b54152011-12-12 21:14:40 +000077}
Sirish Pande7517bbc2012-05-10 20:20:25 +000078