Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / c23b933d5f8be9b51a1d22e717c0311f65f87dcd / . / lib / Target / PowerPC / PPCScheduleA2.td
blob: 4d4a5d0e1b2f6a9432a41a121c7a3539b41aecac [file] [log] [blame]
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]1//===- PPCScheduleA2.td - PPC A2 Scheduling Definitions --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10// Primary reference:
11// A2 Processor User's Manual.
12// IBM (as updated in) 2010.
13
14//===----------------------------------------------------------------------===//
15// Functional units on the PowerPC A2 chip sets
16//
17def IU0to3_0 : FuncUnit; // Fetch unit 1 to 4 slot 1
18def IU0to3_1 : FuncUnit; // Fetch unit 1 to 4 slot 2
19def IU0to3_2 : FuncUnit; // Fetch unit 1 to 4 slot 3
20def IU0to3_3 : FuncUnit; // Fetch unit 1 to 4 slot 4
21def IU4_0 : FuncUnit; // Instruction buffer slot 1
22def IU4_1 : FuncUnit; // Instruction buffer slot 2
23def IU4_2 : FuncUnit; // Instruction buffer slot 3
24def IU4_3 : FuncUnit; // Instruction buffer slot 4
25def IU4_4 : FuncUnit; // Instruction buffer slot 5
26def IU4_5 : FuncUnit; // Instruction buffer slot 6
27def IU4_6 : FuncUnit; // Instruction buffer slot 7
28def IU4_7 : FuncUnit; // Instruction buffer slot 8
29def IU5 : FuncUnit; // Dependency resolution
30def IU6 : FuncUnit; // Instruction issue
31def RF0 : FuncUnit;
32def XRF1 : FuncUnit;
33def XEX1 : FuncUnit; // Execution stage 1 for the XU pipeline
34def XEX2 : FuncUnit; // Execution stage 2 for the XU pipeline
35def XEX3 : FuncUnit; // Execution stage 3 for the XU pipeline
36def XEX4 : FuncUnit; // Execution stage 4 for the XU pipeline
37def XEX5 : FuncUnit; // Execution stage 5 for the XU pipeline
38def XEX6 : FuncUnit; // Execution stage 6 for the XU pipeline
39def FRF1 : FuncUnit;
40def FEX1 : FuncUnit; // Execution stage 1 for the FU pipeline
41def FEX2 : FuncUnit; // Execution stage 2 for the FU pipeline
42def FEX3 : FuncUnit; // Execution stage 3 for the FU pipeline
43def FEX4 : FuncUnit; // Execution stage 4 for the FU pipeline
44def FEX5 : FuncUnit; // Execution stage 5 for the FU pipeline
45def FEX6 : FuncUnit; // Execution stage 6 for the FU pipeline
46
47def CR_Bypass : Bypass; // The bypass for condition regs.
48//def GPR_Bypass : Bypass; // The bypass for general-purpose regs.
49//def FPR_Bypass : Bypass; // The bypass for floating-point regs.
50
51//
52// This file defines the itinerary class data for the PPC A2 processor.
53//
54//===----------------------------------------------------------------------===//
55
56
57def PPCA2Itineraries : ProcessorItineraries<
58 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3,
59 IU4_0, IU4_1, IU4_2, IU4_3, IU4_4, IU4_5, IU4_6, IU4_7,
60 IU5, IU6, RF0, XRF1, XEX1, XEX2, XEX3, XEX4, XEX5, XEX6,
61 FRF1, FEX1, FEX2, FEX3, FEX4, FEX5, FEX6],
62 [CR_Bypass, GPR_Bypass, FPR_Bypass], [
Hal Finkel16803092012-06-12 19:01:24 +0000[diff] [blame]63 InstrItinData<IntSimple , [InstrStage<4,
64 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
65 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
66 IU4_4, IU4_5, IU4_6, IU4_7]>,
67 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
68 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
69 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
70 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
71 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
72 [10, 7, 7],
73 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]74 InstrItinData<IntGeneral , [InstrStage<4,
75 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]76 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
77 IU4_4, IU4_5, IU4_6, IU4_7]>,
78 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
79 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
80 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
81 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
82 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
83 [10, 7, 7],
84 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]85 InstrItinData<IntCompare , [InstrStage<4,
86 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]87 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
88 IU4_4, IU4_5, IU4_6, IU4_7]>,
89 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
90 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
91 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
92 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
93 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
94 [10, 7, 7],
95 [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]96 InstrItinData<IntDivW , [InstrStage<4,
97 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]98 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
99 IU4_4, IU4_5, IU4_6, IU4_7]>,
100 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
101 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
102 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
103 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
104 InstrStage<1, [XEX5]>, InstrStage<38, [XEX6]>],
105 [53, 7, 7],
106 [NoBypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]107 InstrItinData<IntMFFS , [InstrStage<4,
108 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]109 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
110 IU4_4, IU4_5, IU4_6, IU4_7]>,
111 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
112 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
113 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
114 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
115 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
116 [10, 7, 7],
117 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]118 InstrItinData<IntMTFSB0 , [InstrStage<4,
119 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]120 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
121 IU4_4, IU4_5, IU4_6, IU4_7]>,
122 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
123 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
124 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
125 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
126 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
127 [10, 7, 7],
128 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]129 InstrItinData<IntMulHW , [InstrStage<4,
130 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]131 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
132 IU4_4, IU4_5, IU4_6, IU4_7]>,
133 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
134 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
135 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
136 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
137 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
138 [14, 7, 7],
139 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]140 InstrItinData<IntMulHWU , [InstrStage<4,
141 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]142 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
143 IU4_4, IU4_5, IU4_6, IU4_7]>,
144 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
145 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
146 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
147 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
148 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
149 [14, 7, 7],
150 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]151 InstrItinData<IntMulLI , [InstrStage<4,
152 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]153 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
154 IU4_4, IU4_5, IU4_6, IU4_7]>,
155 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
156 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
157 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
158 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
159 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
160 [15, 7, 7],
161 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]162 InstrItinData<IntRotate , [InstrStage<4,
163 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]164 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
165 IU4_4, IU4_5, IU4_6, IU4_7]>,
166 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
167 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
168 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
169 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
170 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
171 [10, 7, 7],
172 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkel04dccea2012-06-12 20:32:29 +0000[diff] [blame]173 InstrItinData<IntRotateD , [InstrStage<4,
174 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
175 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
176 IU4_4, IU4_5, IU4_6, IU4_7]>,
177 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
178 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
179 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
180 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
181 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
182 [10, 7, 7],
183 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]184 InstrItinData<IntShift , [InstrStage<4,
185 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]186 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
187 IU4_4, IU4_5, IU4_6, IU4_7]>,
188 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
189 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
190 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
191 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
192 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
193 [10, 7, 7],
194 [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]195 InstrItinData<IntTrapW , [InstrStage<4,
196 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]197 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
198 IU4_4, IU4_5, IU4_6, IU4_7]>,
199 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
200 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
201 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
202 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
203 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
204 [10, 7, 7],
205 [GPR_Bypass, GPR_Bypass]>,
Hal Finkel04dccea2012-06-12 20:32:29 +0000[diff] [blame]206 InstrItinData<IntTrapD , [InstrStage<4,
207 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
208 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
209 IU4_4, IU4_5, IU4_6, IU4_7]>,
210 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
211 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
212 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
213 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
214 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
215 [10, 7, 7],
216 [GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]217 InstrItinData<BrB , [InstrStage<4,
218 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]219 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
220 IU4_4, IU4_5, IU4_6, IU4_7]>,
221 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
222 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
223 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
224 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
225 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
226 [15, 7, 7],
227 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]228 InstrItinData<BrCR , [InstrStage<4,
229 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]230 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
231 IU4_4, IU4_5, IU4_6, IU4_7]>,
232 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
233 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
234 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
235 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
236 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
237 [10, 7, 7],
238 [CR_Bypass, CR_Bypass, CR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]239 InstrItinData<BrMCR , [InstrStage<4,
240 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]241 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
242 IU4_4, IU4_5, IU4_6, IU4_7]>,
243 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
244 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
245 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
246 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
247 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
248 [10, 7, 7],
249 [CR_Bypass, CR_Bypass, CR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]250 InstrItinData<BrMCRX , [InstrStage<4,
251 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]252 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
253 IU4_4, IU4_5, IU4_6, IU4_7]>,
254 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
255 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
256 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
257 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
258 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
259 [10, 7, 7],
260 [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]261 InstrItinData<LdStDCBA , [InstrStage<4,
262 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]263 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
264 IU4_4, IU4_5, IU4_6, IU4_7]>,
265 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
266 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
267 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
268 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
269 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
270 [13, 11],
271 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]272 InstrItinData<LdStDCBF , [InstrStage<4,
273 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]274 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
275 IU4_4, IU4_5, IU4_6, IU4_7]>,
276 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
277 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
278 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
279 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
280 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
281 [13, 11],
282 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]283 InstrItinData<LdStDCBI , [InstrStage<4,
284 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]285 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
286 IU4_4, IU4_5, IU4_6, IU4_7]>,
287 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
288 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
289 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
290 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
291 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
292 [13, 11],
293 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]294 InstrItinData<LdStLoad , [InstrStage<4,
295 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]296 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
297 IU4_4, IU4_5, IU4_6, IU4_7]>,
298 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
299 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
300 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
301 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
302 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
303 [14, 7],
304 [GPR_Bypass, GPR_Bypass]>,
Hal Finkel79248292012-06-13 05:55:09 +0000[diff] [blame]305 InstrItinData<LdStLD , [InstrStage<4,
306 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
307 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
308 IU4_4, IU4_5, IU4_6, IU4_7]>,
309 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
310 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
311 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
312 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
313 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
314 [14, 7],
315 [GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]316 InstrItinData<LdStStore , [InstrStage<4,
317 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]318 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
319 IU4_4, IU4_5, IU4_6, IU4_7]>,
320 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
321 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
322 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
323 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
324 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
325 [13, 7],
326 [GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]327 InstrItinData<LdStICBI , [InstrStage<4,
328 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]329 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
330 IU4_4, IU4_5, IU4_6, IU4_7]>,
331 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
332 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
333 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
334 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
335 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
336 [14, 7],
337 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]338 InstrItinData<LdStUX , [InstrStage<4,
339 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]340 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
341 IU4_4, IU4_5, IU4_6, IU4_7]>,
342 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
343 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
344 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
345 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
346 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
347 [14, 7, 7],
348 [NoBypass, FPR_Bypass, FPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]349 InstrItinData<LdStLFD , [InstrStage<4,
350 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]351 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
352 IU4_4, IU4_5, IU4_6, IU4_7]>,
353 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
354 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
355 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
356 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
357 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
358 [14, 7, 7],
359 [FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]360 InstrItinData<LdStLFDU , [InstrStage<4,
361 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]362 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
363 IU4_4, IU4_5, IU4_6, IU4_7]>,
364 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
365 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
366 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
367 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
368 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
369 [14, 7, 7],
370 [FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]371 InstrItinData<LdStLHA , [InstrStage<4,
372 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]373 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
374 IU4_4, IU4_5, IU4_6, IU4_7]>,
375 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
376 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
377 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
378 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
379 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
380 [14, 7],
381 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]382 InstrItinData<LdStLMW , [InstrStage<4,
383 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]384 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
385 IU4_4, IU4_5, IU4_6, IU4_7]>,
386 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
387 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
388 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
389 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
390 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
391 [14, 7],
392 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]393 InstrItinData<LdStLWARX , [InstrStage<4,
394 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]395 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
396 IU4_4, IU4_5, IU4_6, IU4_7]>,
397 InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
398 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
399 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
400 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
401 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
402 [26, 7],
403 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]404 InstrItinData<LdStSTD , [InstrStage<4,
405 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]406 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
407 IU4_4, IU4_5, IU4_6, IU4_7]>,
408 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
409 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
410 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
411 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
412 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
413 [13, 7],
414 [GPR_Bypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]415 InstrItinData<LdStSTDCX , [InstrStage<4,
416 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]417 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
418 IU4_4, IU4_5, IU4_6, IU4_7]>,
419 InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
420 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
421 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
422 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
423 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
424 [26, 7],
425 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]426 InstrItinData<LdStSTWCX , [InstrStage<4,
427 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]428 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
429 IU4_4, IU4_5, IU4_6, IU4_7]>,
430 InstrStage<1, [IU5]>, InstrStage<13, [IU6]>,
431 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
432 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
433 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
434 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
435 [26, 7],
436 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]437 InstrItinData<LdStSync , [InstrStage<4,
438 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]439 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
440 IU4_4, IU4_5, IU4_6, IU4_7]>,
441 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
442 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
443 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
444 InstrStage<1, [XEX3]>, InstrStage<12, [XEX4]>,
445 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]446 InstrItinData<SprISYNC , [InstrStage<4,
447 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]448 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
449 IU4_4, IU4_5, IU4_6, IU4_7]>,
450 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
451 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
452 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
453 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
454 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]455 InstrItinData<SprMFSR , [InstrStage<4,
456 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]457 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
458 IU4_4, IU4_5, IU4_6, IU4_7]>,
459 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
460 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
461 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
462 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
463 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
464 [15, 7],
465 [GPR_Bypass, NoBypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]466 InstrItinData<SprMTMSR , [InstrStage<4,
467 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]468 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
469 IU4_4, IU4_5, IU4_6, IU4_7]>,
470 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
471 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
472 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
473 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
474 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
475 [15, 7],
476 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]477 InstrItinData<SprMTSR , [InstrStage<4,
478 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]479 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
480 IU4_4, IU4_5, IU4_6, IU4_7]>,
481 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
482 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
483 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
484 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
485 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
486 [15, 7],
487 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]488 InstrItinData<SprTLBSYNC , [InstrStage<4,
489 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]490 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
491 IU4_4, IU4_5, IU4_6, IU4_7]>,
492 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
493 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
494 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
495 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
496 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]497 InstrItinData<SprMFCR , [InstrStage<4,
498 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]499 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
500 IU4_4, IU4_5, IU4_6, IU4_7]>,
501 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
502 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
503 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
504 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
505 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
506 [10, 7],
507 [GPR_Bypass, CR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]508 InstrItinData<SprMFMSR , [InstrStage<4,
509 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]510 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
511 IU4_4, IU4_5, IU4_6, IU4_7]>,
512 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
513 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
514 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
515 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
516 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
517 [15, 7],
518 [GPR_Bypass, NoBypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]519 InstrItinData<SprMFSPR , [InstrStage<4,
520 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]521 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
522 IU4_4, IU4_5, IU4_6, IU4_7]>,
523 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
524 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
525 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
526 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
527 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
528 [15, 7],
529 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]530 InstrItinData<SprMFTB , [InstrStage<4,
531 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]532 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
533 IU4_4, IU4_5, IU4_6, IU4_7]>,
534 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
535 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
536 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
537 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
538 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
539 [29, 7],
540 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]541 InstrItinData<SprMTSPR , [InstrStage<4,
542 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]543 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
544 IU4_4, IU4_5, IU4_6, IU4_7]>,
545 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
546 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
547 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
548 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
549 InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>],
550 [15, 7],
551 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]552 InstrItinData<SprMTSRIN , [InstrStage<4,
553 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]554 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
555 IU4_4, IU4_5, IU4_6, IU4_7]>,
556 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
557 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
558 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
559 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
560 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
561 [29, 7],
562 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]563 InstrItinData<SprRFI , [InstrStage<4,
564 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]565 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
566 IU4_4, IU4_5, IU4_6, IU4_7]>,
567 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
568 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
569 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
570 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
571 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
572 [29, 7],
573 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]574 InstrItinData<SprSC , [InstrStage<4,
575 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]576 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
577 IU4_4, IU4_5, IU4_6, IU4_7]>,
578 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
579 InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>,
580 InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>,
581 InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>,
582 InstrStage<1, [XEX5]>, InstrStage<14, [XEX6]>],
583 [29, 7],
584 [NoBypass, GPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]585 InstrItinData<FPGeneral , [InstrStage<4,
586 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]587 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
588 IU4_4, IU4_5, IU4_6, IU4_7]>,
589 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
590 InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
591 InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
592 InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
593 InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
594 [15, 7, 7],
595 [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]596 InstrItinData<FPCompare , [InstrStage<4,
597 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]598 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
599 IU4_4, IU4_5, IU4_6, IU4_7]>,
600 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
601 InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
602 InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
603 InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
604 InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
605 [13, 7, 7],
606 [CR_Bypass, FPR_Bypass, FPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]607 InstrItinData<FPDivD , [InstrStage<4,
608 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]609 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
610 IU4_4, IU4_5, IU4_6, IU4_7]>,
611 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
612 InstrStage<1, [RF0]>, InstrStage<71, [FRF1], 0>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]613 InstrStage<71, [FEX1], 0>,
614 InstrStage<71, [FEX2], 0>,
615 InstrStage<71, [FEX3], 0>,
616 InstrStage<71, [FEX4], 0>,
617 InstrStage<71, [FEX5], 0>,
618 InstrStage<71, [FEX6]>],
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]619 [86, 7, 7],
620 [NoBypass, FPR_Bypass, FPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]621 InstrItinData<FPDivS , [InstrStage<4,
622 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]623 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
624 IU4_4, IU4_5, IU4_6, IU4_7]>,
625 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
626 InstrStage<1, [RF0]>, InstrStage<58, [FRF1], 0>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]627 InstrStage<58, [FEX1], 0>,
628 InstrStage<58, [FEX2], 0>,
629 InstrStage<58, [FEX3], 0>,
630 InstrStage<58, [FEX4], 0>,
631 InstrStage<58, [FEX5], 0>,
632 InstrStage<58, [FEX6]>],
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]633 [73, 7, 7],
634 [NoBypass, FPR_Bypass, FPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]635 InstrItinData<FPSqrt , [InstrStage<4,
636 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]637 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
638 IU4_4, IU4_5, IU4_6, IU4_7]>,
639 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
640 InstrStage<1, [RF0]>, InstrStage<68, [FRF1], 0>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]641 InstrStage<68, [FEX1], 0>,
642 InstrStage<68, [FEX2], 0>,
643 InstrStage<68, [FEX3], 0>,
644 InstrStage<68, [FEX4], 0>,
645 InstrStage<68, [FEX5], 0>,
646 InstrStage<68, [FEX6]>],
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]647 [86, 7], // FIXME: should be [86, 7] for double
648 // and [82, 7] for single. Likewise,
649 // the FEX? cycle count should be 68
650 // for double and 64 for single.
651 [NoBypass, FPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]652 InstrItinData<FPFused , [InstrStage<4,
653 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]654 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
655 IU4_4, IU4_5, IU4_6, IU4_7]>,
656 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
657 InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
658 InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
659 InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
660 InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
661 [15, 7, 7, 7],
662 [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
Hal Finkelb66e9432012-04-01 21:20:14 +0000[diff] [blame]663 InstrItinData<FPRes , [InstrStage<4,
664 [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>,
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]665 InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3,
666 IU4_4, IU4_5, IU4_6, IU4_7]>,
667 InstrStage<1, [IU5]>, InstrStage<1, [IU6]>,
668 InstrStage<1, [RF0]>, InstrStage<1, [FRF1]>,
669 InstrStage<1, [FEX1]>, InstrStage<1, [FEX2]>,
670 InstrStage<1, [FEX3]>, InstrStage<1, [FEX4]>,
671 InstrStage<1, [FEX5]>, InstrStage<1, [FEX6]>],
672 [15, 7],
673 [FPR_Bypass, FPR_Bypass]>
674]>;