| Andrew Trick | 1c2d3c5 | 2012-06-13 02:39:03 +0000 | [diff] [blame] | 1 | ; RUN: llc < %s -o /dev/null "-mtriple=thumbv7-apple-ios" -debug-only=post-RA-sched 2> %t |
| 2 | ; RUN: FileCheck %s < %t |
| 3 | ; REQUIRES: asserts |
| 4 | ; Make sure that mayalias store-load dependencies have one cycle |
| 5 | ; latency regardless of whether they are barriers or not. |
| 6 | |
| 7 | ; CHECK: ** List Scheduling |
| 8 | ; CHECK: SU(2){{.*}}STR{{.*}}Volatile |
| 9 | ; CHECK-NOT: ch SU |
| 10 | ; CHECK: ch SU(3): Latency=1 |
| 11 | ; CHECK-NOT: ch SU |
| 12 | ; CHECK: SU(3){{.*}}LDR{{.*}}Volatile |
| 13 | ; CHECK-NOT: ch SU |
| 14 | ; CHECK: ch SU(2): Latency=1 |
| 15 | ; CHECK-NOT: ch SU |
| 16 | ; CHECK: ** List Scheduling |
| 17 | ; CHECK: SU(2){{.*}}STR{{.*}} |
| 18 | ; CHECK-NOT: ch SU |
| 19 | ; CHECK: ch SU(3): Latency=1 |
| 20 | ; CHECK-NOT: ch SU |
| 21 | ; CHECK: SU(3){{.*}}LDR{{.*}} |
| 22 | ; CHECK-NOT: ch SU |
| 23 | ; CHECK: ch SU(2): Latency=1 |
| 24 | ; CHECK-NOT: ch SU |
| 25 | define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { |
| 26 | entry: |
| 27 | store volatile i32 65540, i32* %p1, align 4, !tbaa !0 |
| 28 | %0 = load volatile i32* %p2, align 4, !tbaa !0 |
| 29 | ret i32 %0 |
| 30 | } |
| 31 | |
| 32 | define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind { |
| 33 | entry: |
| 34 | store i32 65540, i32* %p1, align 4, !tbaa !0 |
| 35 | %0 = load i32* %p2, align 4, !tbaa !0 |
| 36 | ret i32 %0 |
| 37 | } |
| 38 | |
| 39 | !0 = metadata !{metadata !"int", metadata !1} |
| 40 | !1 = metadata !{metadata !"omnipotent char", metadata !2} |
| 41 | !2 = metadata !{metadata !"Simple C/C++ TBAA"} |