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Dan Gohmanf17a25c2007-07-18 16:29:46 +00001//===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner081ce942007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Dan Gohmanf17a25c2007-07-18 16:29:46 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Sparc implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef SPARCINSTRUCTIONINFO_H
15#define SPARCINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "SparcRegisterInfo.h"
19
20namespace llvm {
21
22/// SPII - This namespace holds all of the target specific flags that
23/// instruction info tracks.
24///
25namespace SPII {
26 enum {
27 Pseudo = (1<<0),
28 Load = (1<<1),
29 Store = (1<<2),
30 DelaySlot = (1<<3)
31 };
32}
33
Chris Lattnerd2fd6db2008-01-01 01:03:04 +000034class SparcInstrInfo : public TargetInstrInfoImpl {
Dan Gohmanf17a25c2007-07-18 16:29:46 +000035 const SparcRegisterInfo RI;
Owen Anderson8f2c8932007-12-31 06:32:00 +000036 const SparcSubtarget& Subtarget;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000037public:
Dan Gohman40bd38e2008-03-25 22:06:05 +000038 explicit SparcInstrInfo(SparcSubtarget &ST);
Dan Gohmanf17a25c2007-07-18 16:29:46 +000039
40 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
41 /// such, whenever a client has an instance of instruction info, it should
42 /// always be able to get register info as well (through this method).
43 ///
Dan Gohmanb41dfba2008-05-14 01:58:56 +000044 virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; }
Dan Gohmanf17a25c2007-07-18 16:29:46 +000045
Evan Chengf97496a2009-01-20 19:12:24 +000046 /// Return true if the instruction is a register to register move and return
47 /// the source and dest operands and their sub-register indices by reference.
Dan Gohmanf17a25c2007-07-18 16:29:46 +000048 virtual bool isMoveInstr(const MachineInstr &MI,
Evan Chengf97496a2009-01-20 19:12:24 +000049 unsigned &SrcReg, unsigned &DstReg,
50 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000051
52 /// isLoadFromStackSlot - If the specified machine instruction is a direct
53 /// load from a stack slot, return the virtual or physical register number of
54 /// the destination along with the FrameIndex of the loaded stack slot. If
55 /// not, return 0. This predicate must return 0 if the instruction has
56 /// any side effects other than loading from the stack slot.
Dan Gohman90feee22008-11-18 19:49:32 +000057 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
58 int &FrameIndex) const;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000059
60 /// isStoreToStackSlot - If the specified machine instruction is a direct
61 /// store to a stack slot, return the virtual or physical register number of
62 /// the source reg along with the FrameIndex of the loaded stack slot. If
63 /// not, return 0. This predicate must return 0 if the instruction has
64 /// any side effects other than storing to the stack slot.
Dan Gohman90feee22008-11-18 19:49:32 +000065 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
66 int &FrameIndex) const;
Dan Gohmanf17a25c2007-07-18 16:29:46 +000067
68
69 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
70 MachineBasicBlock *FBB,
Owen Andersond131b5b2008-08-14 22:49:33 +000071 const SmallVectorImpl<MachineOperand> &Cond) const;
Owen Anderson8f2c8932007-12-31 06:32:00 +000072
Owen Anderson9fa72d92008-08-26 18:03:31 +000073 virtual bool copyRegToReg(MachineBasicBlock &MBB,
Owen Anderson8f2c8932007-12-31 06:32:00 +000074 MachineBasicBlock::iterator I,
75 unsigned DestReg, unsigned SrcReg,
76 const TargetRegisterClass *DestRC,
Dan Gohman75a44ec2010-05-06 20:33:48 +000077 const TargetRegisterClass *SrcRC,
78 DebugLoc DL) const;
Owen Anderson81875432008-01-01 21:11:32 +000079
80 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MBBI,
82 unsigned SrcReg, bool isKill, int FrameIndex,
Evan Cheng1f8534d2010-05-06 19:06:44 +000083 const TargetRegisterClass *RC,
84 const TargetRegisterInfo *TRI) const;
Owen Anderson81875432008-01-01 21:11:32 +000085
Owen Anderson81875432008-01-01 21:11:32 +000086 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MBBI,
88 unsigned DestReg, int FrameIndex,
Evan Cheng1f8534d2010-05-06 19:06:44 +000089 const TargetRegisterClass *RC,
90 const TargetRegisterInfo *TRI) const;
Owen Anderson9a184ef2008-01-07 01:35:02 +000091
Dan Gohmanedc83d62008-12-03 18:43:12 +000092 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
93 MachineInstr* MI,
94 const SmallVectorImpl<unsigned> &Ops,
95 int FrameIndex) const;
Owen Anderson9a184ef2008-01-07 01:35:02 +000096
Dan Gohmanedc83d62008-12-03 18:43:12 +000097 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
98 MachineInstr* MI,
99 const SmallVectorImpl<unsigned> &Ops,
100 MachineInstr* LoadMI) const {
Owen Anderson9a184ef2008-01-07 01:35:02 +0000101 return 0;
102 }
Chris Lattner49102de2009-09-15 17:46:24 +0000103
104 unsigned getGlobalBaseReg(MachineFunction *MF) const;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000105};
106
107}
108
109#endif