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5 <title>The LLVM Target-Independent Code Generator</title>
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7</head>
8<body>
9
10<div class="doc_title">
11 The LLVM Target-Independent Code Generator
12</div>
13
14<ol>
15 <li><a href="#introduction">Introduction</a>
16 <ul>
17 <li><a href="#required">Required components in the code generator</a></li>
18 <li><a href="#high-level-design">The high-level design of the code generator</a></li>
19 <li><a href="#tablegen">Using TableGen for target description</a></li>
20 </ul>
21 </li>
22 <li><a href="#targetdesc">Target description classes</a>
23 <ul>
24 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
25 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
26 <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
27 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
28 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
29 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
30 </ul>
31 </li>
32 <li><a href="#codegendesc">Machine code description classes</a>
33 </li>
34 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
35 </li>
36 <li><a href="#targetimpls">Target description implementations</a>
37 <ul>
38 <li><a href="#x86">The X86 backend</a></li>
39 </li>
40 </li>
41
42</ol>
43
44<div class="doc_author">
45 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a></p>
46</div>
47
48<!-- *********************************************************************** -->
49<div class="doc_section">
50 <a name="introduction">Introduction</a>
51</div>
52<!-- *********************************************************************** -->
53
54<div class="doc_text">
55
56<p>The LLVM target-independent code generator is a framework that provides a
57suite of reusable components for translating the LLVM internal representation to
58the machine code for a specified target -- either in assembly form (suitable for
59a static compiler) or in binary machine code format (usable for a JIT compiler).
60The LLVM target-independent code generator consists of four main components:</p>
61
62<ol>
63<li><a href="#targetdesc">Abstract target description</a> interfaces which
64capture improtant properties about various aspects of the machine independently
65of how they will be used. These interfaces are defined in
66<tt>include/llvm/Target/</tt>.</li>
67
68<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
69generator for a target. These classes are intended to be abstract enough to
70represent the machine code for <i>any</i> target machine. These classes are
71defined in <tt>include/llvm/CodeGen/</tt>.</li>
72
73<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
74various phases of native code generation (register allocation, scheduling, stack
75frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
76
77<li><a href="#targetimpls">Implementations of the abstract target description
78interfaces</a> for particular targets. These machine descriptions make use of
79the components provided by LLVM, and can optionally provide custom
80target-specific passes, to build complete code generators for a specific target.
81Target descriptions live in <tt>lib/Target/</tt>.</li>
82
83</ol>
84
85<p>
86Depending on which part of the code generator you are interested in working on,
87different pieces of this will be useful to you. In any case, you should be
88familiar with the <a href="#targetdesc">target description</a> and <a
89href="#codegendesc">machine code representation</a> classes. If you want to add
90a backend for a new target, you will need <a href="#targetimpls">implement the
91targe description</a> classes for your new target and understand the <a
92href="LangRef.html">LLVM code representation</a>. If you are interested in
93implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
94should only depend on the target-description and machine code representation
95classes, ensuring that it is portable.
96</p>
97
98</div>
99
100<!-- ======================================================================= -->
101<div class="doc_subsection">
102 <a name="required">Required components in the code generator</a>
103</div>
104
105<div class="doc_text">
106
107<p>The two pieces of the LLVM code generator are the high-level interface to the
108code generator and the set of reusable components that can be used to build
109target-specific backends. The two most important interfaces (<a
110href="#targetmachine"><tt>TargetMachine</tt></a> and <a
111href="#targetdata"><tt>TargetData</tt></a> classes) are the only ones that are
112required to be defined for a backend to fit into the LLVM system, but the others
113must be defined if the reusable code generator components are going to be
114used.</p>
115
116<p>This design has two important implications. The first is that LLVM can
117support completely non-traditional code generation targets. For example, the C
118backend does not require register allocation, instruction selection, or any of
119the other standard components provided by the system. As such, it only
120implements these two interfaces, and does its own thing. Another example of a
121code generator like this is a (purely hypothetical) backend that converts LLVM
122to the GCC RTL form and uses GCC to emit machine code for a target.</p>
123
124<p>The other implication of this design is that it is possible to design and
125implement radically different code generators in the LLVM system that do not
126make use of any of the built-in components. Doing so is not recommended at all,
127but could be required for radically different targets that do not fit into the
128LLVM machine description model: programmable FPGAs for example.</p>
129</p>
130</div>
131
132<!-- ======================================================================= -->
133<div class="doc_subsection">
134 <a name="high-level-design">The high-level design of the code generator</a></li>
135</div>
136
137<div class="doc_text">
138
139<p>The LLVM target-indendent code generator is designed to support efficient and
140quality code generation for standard register-based microprocessors. Code
141generation in this model is divided into the following stages:</p>
142
143<ol>
144<li><b>Instruction Selection</b> - Determining a efficient implementation of the
145input LLVM code in the target instruction set. This stage produces the initial
146code for the program in the target instruction set the makes use of virtual
147registers in SSA form and physical registers that represent any required
148register assignments due to target constraints or calling conventions.</li>
149
150<li><b>SSA-based Machine Code Optimizations</b> - This (optional) stage consists
151of a series of machine-code optimizations that operate on the SSA-form produced
152by the instruction selector. Optimizations like modulo-scheduling, normal
153scheduling, or peephole optimization work here.</li>
154
155<li><b>Register Allocation</b> - The target code is transformed from an infinite
156virtual register file in SSA form to the concrete register file used by the
157target. This phase introduces spill code and eliminates all virtual register
158references from the program.</li>
159
160<li><b>Prolog/Epilog Code Insertion</b> - Once the machine code has been
161generated for the function and the amount of stack space required is known (used
162for LLVM alloca's and spill slots), the prolog and epilog code for the function
163can be inserted and "abstract stack location references" can be eliminated.
164This stage is responsible for implementing optimizations like frame-pointer
165elimination and stack packing.</li>
166
167<li><b>Late Machine Code Optimizations</b> - Optimizations that operate on
168"final" machine code can go here, such as spill code scheduling and peephole
169optimizations.</li>
170
171<li><b>Code Emission</b> - The final stage actually outputs the machine code for
172the current function, either in the target assembler format or in machine
173code.</li>
174
175</ol>
176
177<p>
178The code generator is based on the assumption that the instruction selector will
179use an optimal pattern matching selector to create high-quality sequences of
180native code. Alternative code generator designs based on pattern expansion and
181aggressive iterative peephole optimization are much slower. This design is
182designed to permit efficient compilation (important for JIT environments) and
183aggressive optimization (used when generate code offline) by allowing components
184of varying levels of sophisication to be used for any step of compilation.</p>
185
186<p>
187In addition to these stages, target implementations can insert arbitrary
188target-specific passes into the flow. For example, the X86 target uses a
189special pass to handle the 80x87 floating point stack architecture. Other
190targets with unusual requirements can be supported with custom passes as needed.
191</p>
192
193</div>
194
195
196<!-- ======================================================================= -->
197<div class="doc_subsection">
198 <a name="tablegen">Using TableGen for target description</a></li>
199</div>
200
201<div class="doc_text">
202
203<p>The target description classes require a detailed descriptions of the target
204architecture. These target descriptions often have a large amount of common
205information (e.g., an add instruction is almost identical to a sub instruction).
206In order to allow the maximum amount of commonality to be factored out, the LLVM
207code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
208allow
209</p>
210
211</div>
212
213<!-- *********************************************************************** -->
214<div class="doc_section">
215 <a name="targetdesc">Target description classes</a>
216</div>
217<!-- *********************************************************************** -->
218
219<div class="doc_text">
220
221<p>The LLVM target description classes (which are located in the
222<tt>include/llvm/Target</tt> directory) provide an abstract description of the
223target machine, independent of any particular client. These classes are
224designed to capture the <i>abstract</i> properties of the target (such as what
225instruction and registers it has), and do not incorporate any particular pieces
226of code generation algorithms (these interfaces do not take interference graphs
227as inputs or other algorithm-specific data structures).</p>
228
229<p>All of the target description classes (except the <tt><a
230href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
231the concrete target implementation, and have virtual methods implemented. To
232get to these implementations, <tt><a
233href="#targetmachine">TargetMachine</a></tt> class provides accessors that
234should be implemented by the target.</p>
235
236</div>
237
238<!-- ======================================================================= -->
239<div class="doc_subsection">
240 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
241</div>
242
243<div class="doc_text">
244
245<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
246access the target-specific implementations of the various target description
247classes (with the <tt>getInstrInfo</tt>, <tt>getRegisterInfo</tt>,
248<tt>getFrameInfo</tt>, ... methods). This class is designed to be subclassed by
249a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
250implements the various virtual methods. The only required target description
251class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
252code generator components are to be used, the other interfaces should be
253implemented as well.</p>
254
255</div>
256
257
258<!-- ======================================================================= -->
259<div class="doc_subsection">
260 <a name="targetdata">The <tt>TargetData</tt> class</a>
261</div>
262
263<div class="doc_text">
264
265<p>The <tt>TargetData</tt> class is the only required target description class,
266and it is the only class that is not extensible (it cannot be derived from). It
267specifies information about how the target lays out memory for structures, the
268alignment requirements for various data types, the size of pointers in the
269target, and whether the target is little- or big-endian.</p>
270
271</div>
272
273
274<!-- ======================================================================= -->
275<div class="doc_subsection">
276 <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
277</div>
278
279<div class="doc_text">
280
281<p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
282<tt>TargetRegisterInfo</tt>) is used to describe the register file of the
283target and any interactions between the registers.</p>
284
285<p>Registers in the code generator are represented in the code generator by
286unsigned numbers. Physical registers (those that actually exist in the target
287description) are unique small numbers, and virtual registers are generally
288large.</p>
289
290<p>Each register in the processor description has an associated
291<tt>MRegisterDesc</tt> entry, which provides a textual name for the register
292(used for assembly output and debugging dumps), a set of aliases (used to
293indicate that one register overlaps with another), and some flag bits.
294</p>
295
296<p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
297exposes a set of processor specific register classes (instances of the
298<tt>TargetRegisterClass</tt> class). Each register class contains sets of
299registers that have the same properties (for example, they are all 32-bit
300integer registers). Each SSA virtual register created by the instruction
301selector has an associated register class. When the register allocator runs, it
302replaces virtual registers with a physical register in the set.</p>
303
304<p>
305The target-specific implementations of these classes is auto-generated from a <a
306href="TableGenFundamentals.html">TableGen</a> description of the register file.
307</p>
308
309</div>
310
311<!-- ======================================================================= -->
312<div class="doc_subsection">
313 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
314</div>
315
316<!-- ======================================================================= -->
317<div class="doc_subsection">
318 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
319</div>
320
321<!-- ======================================================================= -->
322<div class="doc_subsection">
323 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
324</div>
325
326<!-- *********************************************************************** -->
327<div class="doc_section">
328 <a name="codegendesc">Machine code description classes</a>
329</div>
330<!-- *********************************************************************** -->
331
332
333
334<!-- *********************************************************************** -->
335<hr>
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342 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
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