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Chris Lattner179cdfb2002-08-09 20:08:03 +00001//===-- PhyRegAlloc.cpp ---------------------------------------------------===//
Vikram S. Adve12af1642001-11-08 04:48:50 +00002//
John Criswellb576c942003-10-20 19:43:21 +00003// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Brian Gaeke222bd532003-09-24 18:16:23 +000010// Traditional graph-coloring global register allocator currently used
11// by the SPARC back-end.
12//
13// NOTE: This register allocator has some special support
14// for the Reoptimizer, such as not saving some registers on calls to
15// the first-level instrumentation function.
16//
17// NOTE 2: This register allocator can save its state in a global
18// variable in the module it's working on. This feature is not
19// thread-safe; if you have doubts, leave it turned off.
Chris Lattner179cdfb2002-08-09 20:08:03 +000020//
21//===----------------------------------------------------------------------===//
Ruchira Sasanka8e604792001-09-14 21:18:34 +000022
Brian Gaeke537132b2003-10-23 20:32:55 +000023#include "AllocInfo.h"
Misha Brukman396c8c32003-10-23 18:06:27 +000024#include "IGNode.h"
Chris Lattner70b2f562003-09-01 20:09:04 +000025#include "PhyRegAlloc.h"
Chris Lattner4309e732003-01-15 19:57:07 +000026#include "RegAllocCommon.h"
Chris Lattner9d4ed152003-01-15 21:14:01 +000027#include "RegClass.h"
Misha Brukman396c8c32003-10-23 18:06:27 +000028#include "llvm/Constants.h"
29#include "llvm/DerivedTypes.h"
30#include "llvm/iOther.h"
31#include "llvm/Module.h"
32#include "llvm/Type.h"
33#include "llvm/Analysis/LoopInfo.h"
Chris Lattner797c1362003-09-30 20:13:59 +000034#include "llvm/CodeGen/FunctionLiveVarInfo.h"
35#include "llvm/CodeGen/InstrSelection.h"
Brian Gaeke3ceac852003-10-30 21:21:33 +000036#include "llvm/CodeGen/MachineCodeForInstruction.h"
Misha Brukman396c8c32003-10-23 18:06:27 +000037#include "llvm/CodeGen/MachineFunction.h"
38#include "llvm/CodeGen/MachineFunctionInfo.h"
Brian Gaeke874f4232003-09-21 02:50:21 +000039#include "llvm/CodeGen/MachineInstr.h"
Chris Lattnerf6ee49f2003-01-15 18:08:07 +000040#include "llvm/CodeGen/MachineInstrBuilder.h"
Vikram S. Advedabb41d2002-05-19 15:29:31 +000041#include "llvm/CodeGen/MachineInstrAnnot.h"
Chris Lattner797c1362003-09-30 20:13:59 +000042#include "llvm/CodeGen/Passes.h"
Chris Lattner797c1362003-09-30 20:13:59 +000043#include "llvm/Support/InstIterator.h"
Misha Brukman396c8c32003-10-23 18:06:27 +000044#include "llvm/Target/TargetInstrInfo.h"
Chris Lattner4bc23482002-09-15 07:07:55 +000045#include "Support/CommandLine.h"
Misha Brukman396c8c32003-10-23 18:06:27 +000046#include "Support/SetOperations.h"
47#include "Support/STLExtras.h"
Brian Gaekebd353fb2003-09-21 03:57:37 +000048#include <cmath>
Vikram S. Adve12af1642001-11-08 04:48:50 +000049
Brian Gaeked0fde302003-11-11 22:41:34 +000050namespace llvm {
51
Chris Lattner70e60cb2002-05-22 17:08:27 +000052RegAllocDebugLevel_t DEBUG_RA;
Vikram S. Adve39c94e12002-09-14 23:05:33 +000053
Brian Gaeke8fc49342003-10-24 21:21:58 +000054/// The reoptimizer wants to be able to grovel through the register
55/// allocator's state after it has done its job. This is a hack.
56///
57PhyRegAlloc::SavedStateMapTy ExportedFnAllocState;
Brian Gaekee9414ca2003-11-10 07:12:01 +000058const bool SaveStateToModule = true;
Brian Gaeke8fc49342003-10-24 21:21:58 +000059
Chris Lattner5ff62e92002-07-22 02:10:13 +000060static cl::opt<RegAllocDebugLevel_t, true>
61DRA_opt("dregalloc", cl::Hidden, cl::location(DEBUG_RA),
62 cl::desc("enable register allocation debugging information"),
63 cl::values(
Vikram S. Adve39c94e12002-09-14 23:05:33 +000064 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
65 clEnumValN(RA_DEBUG_Results, "y", "debug output for allocation results"),
66 clEnumValN(RA_DEBUG_Coloring, "c", "debug output for graph coloring step"),
67 clEnumValN(RA_DEBUG_Interference,"ig","debug output for interference graphs"),
68 clEnumValN(RA_DEBUG_LiveRanges , "lr","debug output for live ranges"),
69 clEnumValN(RA_DEBUG_Verbose, "v", "extra debug output"),
Chris Lattner5ff62e92002-07-22 02:10:13 +000070 0));
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +000071
Brian Gaeke59b1c562003-09-24 17:50:28 +000072static cl::opt<bool>
73SaveRegAllocState("save-ra-state", cl::Hidden,
74 cl::desc("write reg. allocator state into module"));
75
Brian Gaekebf3c4cf2003-08-14 06:09:32 +000076FunctionPass *getRegisterAllocator(TargetMachine &T) {
Brian Gaeke4efe3422003-09-21 01:23:46 +000077 return new PhyRegAlloc (T);
Chris Lattner2f9b28e2002-02-04 15:54:09 +000078}
Chris Lattner6dd98a62002-02-04 00:33:08 +000079
Chris Lattner8474f6f2003-09-23 15:13:04 +000080void PhyRegAlloc::getAnalysisUsage(AnalysisUsage &AU) const {
81 AU.addRequired<LoopInfo> ();
82 AU.addRequired<FunctionLiveVarInfo> ();
83}
84
85
Brian Gaekeaf843702003-10-22 20:22:53 +000086/// Initialize interference graphs (one in each reg class) and IGNodeLists
87/// (one in each IG). The actual nodes will be pushed later.
88///
Chris Lattnerdd1e40b2002-02-03 07:46:34 +000089void PhyRegAlloc::createIGNodeListsAndIGs() {
Chris Lattnerc083dcc2003-09-01 20:05:47 +000090 if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "Creating LR lists ...\n";
Ruchira Sasanka8e604792001-09-14 21:18:34 +000091
Brian Gaeke4efe3422003-09-21 01:23:46 +000092 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
Brian Gaeke4efe3422003-09-21 01:23:46 +000093 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
Ruchira Sasanka8e604792001-09-14 21:18:34 +000094
Chris Lattnerdd1e40b2002-02-03 07:46:34 +000095 for (; HMI != HMIEnd ; ++HMI ) {
96 if (HMI->first) {
97 LiveRange *L = HMI->second; // get the LiveRange
98 if (!L) {
Vikram S. Adve39c94e12002-09-14 23:05:33 +000099 if (DEBUG_RA)
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000100 std::cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
Vikram S. Adve39c94e12002-09-14 23:05:33 +0000101 << RAV(HMI->first) << "****\n";
Chris Lattnerdd1e40b2002-02-03 07:46:34 +0000102 continue;
103 }
Vikram S. Adve39c94e12002-09-14 23:05:33 +0000104
105 // if the Value * is not null, and LR is not yet written to the IGNodeList
Chris Lattner7e708292002-06-25 16:13:24 +0000106 if (!(L->getUserIGNode()) ) {
Chris Lattnerdd1e40b2002-02-03 07:46:34 +0000107 RegClass *const RC = // RegClass of first value in the LR
Brian Gaeke59b1c562003-09-24 17:50:28 +0000108 RegClassList[ L->getRegClassID() ];
Chris Lattnerdd1e40b2002-02-03 07:46:34 +0000109 RC->addLRToIG(L); // add this LR to an IG
110 }
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000111 }
112 }
Chris Lattnerdd1e40b2002-02-03 07:46:34 +0000113
114 // init RegClassList
Chris Lattner7e708292002-06-25 16:13:24 +0000115 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
Chris Lattnerdd1e40b2002-02-03 07:46:34 +0000116 RegClassList[rc]->createInterferenceGraph();
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000117
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000118 if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "LRLists Created!\n";
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000119}
120
121
Brian Gaekeaf843702003-10-22 20:22:53 +0000122/// Add all interferences for a given instruction. Interference occurs only
123/// if the LR of Def (Inst or Arg) is of the same reg class as that of live
124/// var. The live var passed to this function is the LVset AFTER the
125/// instruction.
126///
127void PhyRegAlloc::addInterference(const Value *Def, const ValueSet *LVSet,
Chris Lattner296b7732002-02-05 02:52:05 +0000128 bool isCallInst) {
Chris Lattner296b7732002-02-05 02:52:05 +0000129 ValueSet::const_iterator LIt = LVSet->begin();
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000130
131 // get the live range of instruction
Brian Gaeke4efe3422003-09-21 01:23:46 +0000132 const LiveRange *const LROfDef = LRI->getLiveRangeForValue( Def );
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000133
134 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
135 assert( IGNodeOfDef );
136
137 RegClass *const RCOfDef = LROfDef->getRegClass();
138
139 // for each live var in live variable set
Chris Lattner7e708292002-06-25 16:13:24 +0000140 for ( ; LIt != LVSet->end(); ++LIt) {
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000141
Vikram S. Advef5af6362002-07-08 23:15:32 +0000142 if (DEBUG_RA >= RA_DEBUG_Verbose)
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000143 std::cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000144
145 // get the live range corresponding to live var
Brian Gaeke4efe3422003-09-21 01:23:46 +0000146 LiveRange *LROfVar = LRI->getLiveRangeForValue(*LIt);
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000147
148 // LROfVar can be null if it is a const since a const
149 // doesn't have a dominating def - see Assumptions above
Vikram S. Adve39c94e12002-09-14 23:05:33 +0000150 if (LROfVar)
151 if (LROfDef != LROfVar) // do not set interf for same LR
152 if (RCOfDef == LROfVar->getRegClass()) // 2 reg classes are the same
153 RCOfDef->setInterference( LROfDef, LROfVar);
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000154 }
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000155}
156
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000157
Brian Gaekeaf843702003-10-22 20:22:53 +0000158/// For a call instruction, this method sets the CallInterference flag in
159/// the LR of each variable live in the Live Variable Set live after the
160/// call instruction (except the return value of the call instruction - since
161/// the return value does not interfere with that call itself).
162///
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000163void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
Chris Lattner296b7732002-02-05 02:52:05 +0000164 const ValueSet *LVSetAft) {
Vikram S. Adve39c94e12002-09-14 23:05:33 +0000165 if (DEBUG_RA >= RA_DEBUG_Interference)
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000166 std::cerr << "\n For call inst: " << *MInst;
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000167
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000168 // for each live var in live variable set after machine inst
Vikram S. Adve65b2f402003-07-02 01:24:00 +0000169 for (ValueSet::const_iterator LIt = LVSetAft->begin(), LEnd = LVSetAft->end();
170 LIt != LEnd; ++LIt) {
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000171
Ruchira Sasanka4f3eb222002-01-07 19:19:18 +0000172 // get the live range corresponding to live var
Brian Gaeke4efe3422003-09-21 01:23:46 +0000173 LiveRange *const LR = LRI->getLiveRangeForValue(*LIt );
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000174
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000175 // LR can be null if it is a const since a const
176 // doesn't have a dominating def - see Assumptions above
Vikram S. Adve39c94e12002-09-14 23:05:33 +0000177 if (LR ) {
178 if (DEBUG_RA >= RA_DEBUG_Interference) {
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000179 std::cerr << "\n\tLR after Call: ";
Vikram S. Adve39c94e12002-09-14 23:05:33 +0000180 printSet(*LR);
181 }
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000182 LR->setCallInterference();
Vikram S. Adve39c94e12002-09-14 23:05:33 +0000183 if (DEBUG_RA >= RA_DEBUG_Interference) {
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000184 std::cerr << "\n ++After adding call interference for LR: " ;
Chris Lattner296b7732002-02-05 02:52:05 +0000185 printSet(*LR);
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000186 }
187 }
188
189 }
190
Vikram S. Adve1a53f032002-03-31 18:54:37 +0000191 // Now find the LR of the return value of the call
192 // We do this because, we look at the LV set *after* the instruction
193 // to determine, which LRs must be saved across calls. The return value
194 // of the call is live in this set - but it does not interfere with call
195 // (i.e., we can allocate a volatile register to the return value)
Vikram S. Advedabb41d2002-05-19 15:29:31 +0000196 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
197
198 if (const Value *RetVal = argDesc->getReturnValue()) {
Brian Gaeke4efe3422003-09-21 01:23:46 +0000199 LiveRange *RetValLR = LRI->getLiveRangeForValue( RetVal );
Vikram S. Adve1a53f032002-03-31 18:54:37 +0000200 assert( RetValLR && "No LR for RetValue of call");
201 RetValLR->clearCallInterference();
202 }
203
204 // If the CALL is an indirect call, find the LR of the function pointer.
205 // That has a call interference because it conflicts with outgoing args.
Chris Lattner7e708292002-06-25 16:13:24 +0000206 if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
Brian Gaeke4efe3422003-09-21 01:23:46 +0000207 LiveRange *AddrValLR = LRI->getLiveRangeForValue( AddrVal );
Vikram S. Adve1a53f032002-03-31 18:54:37 +0000208 assert( AddrValLR && "No LR for indirect addr val of call");
209 AddrValLR->setCallInterference();
210 }
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000211}
212
213
Brian Gaekeaf843702003-10-22 20:22:53 +0000214/// Create interferences in the IG of each RegClass, and calculate the spill
215/// cost of each Live Range (it is done in this method to save another pass
216/// over the code).
217///
218void PhyRegAlloc::buildInterferenceGraphs() {
Vikram S. Adve39c94e12002-09-14 23:05:33 +0000219 if (DEBUG_RA >= RA_DEBUG_Interference)
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000220 std::cerr << "Creating interference graphs ...\n";
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000221
Ruchira Sasanka4f3eb222002-01-07 19:19:18 +0000222 unsigned BBLoopDepthCost;
Brian Gaeke4efe3422003-09-21 01:23:46 +0000223 for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
Chris Lattner2fbfdcf2002-04-07 20:49:59 +0000224 BBI != BBE; ++BBI) {
Chris Lattnerf726e772002-10-28 19:22:04 +0000225 const MachineBasicBlock &MBB = *BBI;
226 const BasicBlock *BB = MBB.getBasicBlock();
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000227
Ruchira Sasanka4f3eb222002-01-07 19:19:18 +0000228 // find the 10^(loop_depth) of this BB
Chris Lattnerf726e772002-10-28 19:22:04 +0000229 BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
Ruchira Sasanka4f3eb222002-01-07 19:19:18 +0000230
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000231 // get the iterator for machine instructions
Chris Lattnerf726e772002-10-28 19:22:04 +0000232 MachineBasicBlock::const_iterator MII = MBB.begin();
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000233
234 // iterate over all the machine instructions in BB
Chris Lattnerf726e772002-10-28 19:22:04 +0000235 for ( ; MII != MBB.end(); ++MII) {
236 const MachineInstr *MInst = *MII;
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000237
238 // get the LV set after the instruction
Chris Lattnerf726e772002-10-28 19:22:04 +0000239 const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
240 bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000241
Brian Gaekeaf843702003-10-22 20:22:53 +0000242 if (isCallInst) {
Misha Brukman37f92e22003-09-11 22:34:13 +0000243 // set the isCallInterference flag of each live range which extends
244 // across this call instruction. This information is used by graph
245 // coloring algorithm to avoid allocating volatile colors to live ranges
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000246 // that span across calls (since they have to be saved/restored)
Chris Lattner748697d2002-02-05 04:20:12 +0000247 setCallInterferences(MInst, &LVSetAI);
Ruchira Sasanka958faf32001-10-19 17:21:03 +0000248 }
249
Ruchira Sasanka4f3eb222002-01-07 19:19:18 +0000250 // iterate over all MI operands to find defs
Chris Lattner2f898d22002-02-05 06:02:59 +0000251 for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
252 OpE = MInst->end(); OpI != OpE; ++OpI) {
Vikram S. Adve5f2180c2003-05-27 00:05:23 +0000253 if (OpI.isDefOnly() || OpI.isDefAndUse()) // create a new LR since def
Chris Lattner748697d2002-02-05 04:20:12 +0000254 addInterference(*OpI, &LVSetAI, isCallInst);
Ruchira Sasanka4f3eb222002-01-07 19:19:18 +0000255
256 // Calculate the spill cost of each live range
Brian Gaeke4efe3422003-09-21 01:23:46 +0000257 LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
Chris Lattner2f898d22002-02-05 06:02:59 +0000258 if (LR) LR->addSpillCost(BBLoopDepthCost);
Ruchira Sasanka4f3eb222002-01-07 19:19:18 +0000259 }
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000260
Brian Gaekeaf843702003-10-22 20:22:53 +0000261 // Mark all operands of pseudo-instructions as interfering with one
262 // another. This must be done because pseudo-instructions may be
263 // expanded to multiple instructions by the assembler, so all the
264 // operands must get distinct registers.
Chris Lattnerdd1e40b2002-02-03 07:46:34 +0000265 if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
Ruchira Sasanka22ccb1b2001-11-14 15:33:58 +0000266 addInterf4PseudoInstr(MInst);
267
Ruchira Sasankac4d4b762001-10-16 01:23:19 +0000268 // Also add interference for any implicit definitions in a machine
269 // instr (currently, only calls have this).
Ruchira Sasankac4d4b762001-10-16 01:23:19 +0000270 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
Vikram S. Adve5f2180c2003-05-27 00:05:23 +0000271 for (unsigned z=0; z < NumOfImpRefs; z++)
272 if (MInst->getImplicitOp(z).opIsDefOnly() ||
273 MInst->getImplicitOp(z).opIsDefAndUse())
274 addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
Ruchira Sasankaef1b0cb2001-11-03 17:13:27 +0000275
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000276 } // for all machine instructions in BB
Chris Lattner2fbfdcf2002-04-07 20:49:59 +0000277 } // for all BBs in function
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000278
Misha Brukman37f92e22003-09-11 22:34:13 +0000279 // add interferences for function arguments. Since there are no explicit
Chris Lattner2fbfdcf2002-04-07 20:49:59 +0000280 // defs in the function for args, we have to add them manually
Ruchira Sasanka4f3eb222002-01-07 19:19:18 +0000281 addInterferencesForArgs();
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000282
Vikram S. Adve39c94e12002-09-14 23:05:33 +0000283 if (DEBUG_RA >= RA_DEBUG_Interference)
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000284 std::cerr << "Interference graphs calculated!\n";
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000285}
286
Ruchira Sasanka4f3eb222002-01-07 19:19:18 +0000287
Brian Gaekeaf843702003-10-22 20:22:53 +0000288/// Mark all operands of the given MachineInstr as interfering with one
289/// another.
290///
Brian Gaeke43ce8fe2003-09-21 02:24:09 +0000291void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
Ruchira Sasankaf6dfca12001-11-15 15:00:53 +0000292 bool setInterf = false;
293
Brian Gaeke43ce8fe2003-09-21 02:24:09 +0000294 // iterate over MI operands to find defs
Chris Lattner2f898d22002-02-05 06:02:59 +0000295 for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
296 ItE = MInst->end(); It1 != ItE; ++It1) {
Brian Gaeke4efe3422003-09-21 01:23:46 +0000297 const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000298 assert((LROfOp1 || !It1.isUseOnly())&&"No LR for Def in PSEUDO insruction");
Ruchira Sasanka22ccb1b2001-11-14 15:33:58 +0000299
Chris Lattner2f898d22002-02-05 06:02:59 +0000300 MachineInstr::const_val_op_iterator It2 = It1;
Chris Lattner7e708292002-06-25 16:13:24 +0000301 for (++It2; It2 != ItE; ++It2) {
Brian Gaeke4efe3422003-09-21 01:23:46 +0000302 const LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
Ruchira Sasankaf6dfca12001-11-15 15:00:53 +0000303
Chris Lattner2f898d22002-02-05 06:02:59 +0000304 if (LROfOp2) {
305 RegClass *RCOfOp1 = LROfOp1->getRegClass();
306 RegClass *RCOfOp2 = LROfOp2->getRegClass();
Ruchira Sasanka22ccb1b2001-11-14 15:33:58 +0000307
Chris Lattner7e708292002-06-25 16:13:24 +0000308 if (RCOfOp1 == RCOfOp2 ){
Ruchira Sasanka22ccb1b2001-11-14 15:33:58 +0000309 RCOfOp1->setInterference( LROfOp1, LROfOp2 );
Ruchira Sasankaf6dfca12001-11-15 15:00:53 +0000310 setInterf = true;
Ruchira Sasanka22ccb1b2001-11-14 15:33:58 +0000311 }
Ruchira Sasanka22ccb1b2001-11-14 15:33:58 +0000312 } // if Op2 has a LR
Ruchira Sasanka22ccb1b2001-11-14 15:33:58 +0000313 } // for all other defs in machine instr
Ruchira Sasanka22ccb1b2001-11-14 15:33:58 +0000314 } // for all operands in an instruction
315
Chris Lattner2f898d22002-02-05 06:02:59 +0000316 if (!setInterf && MInst->getNumOperands() > 2) {
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000317 std::cerr << "\nInterf not set for any operand in pseudo instr:\n";
318 std::cerr << *MInst;
Ruchira Sasankaf6dfca12001-11-15 15:00:53 +0000319 assert(0 && "Interf not set for pseudo instr with > 2 operands" );
Ruchira Sasankaf6dfca12001-11-15 15:00:53 +0000320 }
Ruchira Sasanka22ccb1b2001-11-14 15:33:58 +0000321}
322
323
Brian Gaekeaf843702003-10-22 20:22:53 +0000324/// Add interferences for incoming arguments to a function.
325///
Chris Lattner296b7732002-02-05 02:52:05 +0000326void PhyRegAlloc::addInterferencesForArgs() {
327 // get the InSet of root BB
Chris Lattnerf726e772002-10-28 19:22:04 +0000328 const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000329
Chris Lattnerf726e772002-10-28 19:22:04 +0000330 for (Function::const_aiterator AI = Fn->abegin(); AI != Fn->aend(); ++AI) {
Chris Lattner7e708292002-06-25 16:13:24 +0000331 // add interferences between args and LVars at start
332 addInterference(AI, &InSet, false);
333
Vikram S. Adve39c94e12002-09-14 23:05:33 +0000334 if (DEBUG_RA >= RA_DEBUG_Interference)
Brian Gaekeaf843702003-10-22 20:22:53 +0000335 std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
Ruchira Sasanka8e604792001-09-14 21:18:34 +0000336 }
337}
338
339
Brian Gaekeaf843702003-10-22 20:22:53 +0000340/// The following are utility functions used solely by updateMachineCode and
341/// the functions that it calls. They should probably be folded back into
342/// updateMachineCode at some point.
343///
Vikram S. Adve48762092002-04-25 04:34:15 +0000344
Brian Gaekeaf843702003-10-22 20:22:53 +0000345// used by: updateMachineCode (1 time), PrependInstructions (1 time)
346inline void InsertBefore(MachineInstr* newMI, MachineBasicBlock& MBB,
347 MachineBasicBlock::iterator& MII) {
Chris Lattnerf726e772002-10-28 19:22:04 +0000348 MII = MBB.insert(MII, newMI);
Vikram S. Advecb202e32002-10-11 16:12:40 +0000349 ++MII;
350}
351
Brian Gaekeaf843702003-10-22 20:22:53 +0000352// used by: AppendInstructions (1 time)
353inline void InsertAfter(MachineInstr* newMI, MachineBasicBlock& MBB,
354 MachineBasicBlock::iterator& MII) {
Vikram S. Advecb202e32002-10-11 16:12:40 +0000355 ++MII; // insert before the next instruction
Chris Lattnerf726e772002-10-28 19:22:04 +0000356 MII = MBB.insert(MII, newMI);
Vikram S. Advecb202e32002-10-11 16:12:40 +0000357}
358
Brian Gaekeaf843702003-10-22 20:22:53 +0000359// used by: updateMachineCode (1 time)
360inline void DeleteInstruction(MachineBasicBlock& MBB,
361 MachineBasicBlock::iterator& MII) {
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000362 MII = MBB.erase(MII);
363}
364
Brian Gaekeaf843702003-10-22 20:22:53 +0000365// used by: updateMachineCode (1 time)
366inline void SubstituteInPlace(MachineInstr* newMI, MachineBasicBlock& MBB,
367 MachineBasicBlock::iterator MII) {
Vikram S. Advecb202e32002-10-11 16:12:40 +0000368 *MII = newMI;
369}
370
Brian Gaekeaf843702003-10-22 20:22:53 +0000371// used by: updateMachineCode (2 times)
372inline void PrependInstructions(std::vector<MachineInstr *> &IBef,
373 MachineBasicBlock& MBB,
374 MachineBasicBlock::iterator& MII,
375 const std::string& msg) {
376 if (!IBef.empty()) {
Vikram S. Adve48762092002-04-25 04:34:15 +0000377 MachineInstr* OrigMI = *MII;
Vikram S. Advedabb41d2002-05-19 15:29:31 +0000378 std::vector<MachineInstr *>::iterator AdIt;
Brian Gaekeaf843702003-10-22 20:22:53 +0000379 for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt) {
Vikram S. Adve48762092002-04-25 04:34:15 +0000380 if (DEBUG_RA) {
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000381 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
382 std::cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
Vikram S. Adve48762092002-04-25 04:34:15 +0000383 }
Chris Lattnerf726e772002-10-28 19:22:04 +0000384 InsertBefore(*AdIt, MBB, MII);
Vikram S. Adve48762092002-04-25 04:34:15 +0000385 }
386 }
387}
388
Brian Gaekeaf843702003-10-22 20:22:53 +0000389// used by: updateMachineCode (1 time)
390inline void AppendInstructions(std::vector<MachineInstr *> &IAft,
391 MachineBasicBlock& MBB,
392 MachineBasicBlock::iterator& MII,
393 const std::string& msg) {
394 if (!IAft.empty()) {
Vikram S. Adve48762092002-04-25 04:34:15 +0000395 MachineInstr* OrigMI = *MII;
Vikram S. Advedabb41d2002-05-19 15:29:31 +0000396 std::vector<MachineInstr *>::iterator AdIt;
Brian Gaekeaf843702003-10-22 20:22:53 +0000397 for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
Chris Lattner7e708292002-06-25 16:13:24 +0000398 if (DEBUG_RA) {
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000399 if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
400 std::cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
Vikram S. Adve48762092002-04-25 04:34:15 +0000401 }
Chris Lattnerf726e772002-10-28 19:22:04 +0000402 InsertAfter(*AdIt, MBB, MII);
Vikram S. Adve48762092002-04-25 04:34:15 +0000403 }
404 }
405}
406
Brian Gaekeaf843702003-10-22 20:22:53 +0000407/// Set the registers for operands in the given MachineInstr, if a register was
408/// successfully allocated. Return true if any of its operands has been marked
409/// for spill.
410///
Brian Gaeke4efe3422003-09-21 01:23:46 +0000411bool PhyRegAlloc::markAllocatedRegs(MachineInstr* MInst)
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000412{
Vikram S. Adve814030a2003-07-29 19:49:21 +0000413 bool instrNeedsSpills = false;
414
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000415 // First, set the registers for operands in the machine instruction
416 // if a register was successfully allocated. Do this first because we
417 // will need to know which registers are already used by this instr'n.
Brian Gaekeaf843702003-10-22 20:22:53 +0000418 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000419 MachineOperand& Op = MInst->getOperand(OpNum);
420 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
Brian Gaekeaf843702003-10-22 20:22:53 +0000421 Op.getType() == MachineOperand::MO_CCRegister) {
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000422 const Value *const Val = Op.getVRegValue();
Brian Gaeke4efe3422003-09-21 01:23:46 +0000423 if (const LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
Vikram S. Adve814030a2003-07-29 19:49:21 +0000424 // Remember if any operand needs spilling
425 instrNeedsSpills |= LR->isMarkedForSpill();
426
427 // An operand may have a color whether or not it needs spilling
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000428 if (LR->hasColor())
429 MInst->SetRegForOperand(OpNum,
Brian Gaeke59b1c562003-09-24 17:50:28 +0000430 MRI.getUnifiedRegNum(LR->getRegClassID(),
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000431 LR->getColor()));
Vikram S. Adve814030a2003-07-29 19:49:21 +0000432 }
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000433 }
434 } // for each operand
Vikram S. Adve814030a2003-07-29 19:49:21 +0000435
436 return instrNeedsSpills;
437}
438
Brian Gaekeaf843702003-10-22 20:22:53 +0000439/// Mark allocated registers (using markAllocatedRegs()) on the instruction
440/// that MII points to. Then, if it's a call instruction, insert caller-saving
441/// code before and after it. Finally, insert spill code before and after it,
442/// using insertCode4SpilledLR().
443///
Vikram S. Adve814030a2003-07-29 19:49:21 +0000444void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
Brian Gaekeaf843702003-10-22 20:22:53 +0000445 MachineBasicBlock &MBB) {
Vikram S. Adve814030a2003-07-29 19:49:21 +0000446 MachineInstr* MInst = *MII;
447 unsigned Opcode = MInst->getOpCode();
448
449 // Reset tmp stack positions so they can be reused for each machine instr.
Brian Gaeke4efe3422003-09-21 01:23:46 +0000450 MF->getInfo()->popAllTempValues();
Vikram S. Adve814030a2003-07-29 19:49:21 +0000451
452 // Mark the operands for which regs have been allocated.
Brian Gaeke4efe3422003-09-21 01:23:46 +0000453 bool instrNeedsSpills = markAllocatedRegs(*MII);
Vikram S. Adve814030a2003-07-29 19:49:21 +0000454
455#ifndef NDEBUG
456 // Mark that the operands have been updated. Later,
457 // setRelRegsUsedByThisInst() is called to find registers used by each
458 // MachineInst, and it should not be used for an instruction until
459 // this is done. This flag just serves as a sanity check.
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000460 OperandsColoredMap[MInst] = true;
Vikram S. Adve814030a2003-07-29 19:49:21 +0000461#endif
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000462
Vikram S. Advebc001b22003-07-25 21:06:09 +0000463 // Now insert caller-saving code before/after the call.
464 // Do this before inserting spill code since some registers must be
465 // used by save/restore and spill code should not use those registers.
Vikram S. Advebc001b22003-07-25 21:06:09 +0000466 if (TM.getInstrInfo().isCall(Opcode)) {
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000467 AddedInstrns &AI = AddedInstrMap[MInst];
Vikram S. Adve814030a2003-07-29 19:49:21 +0000468 insertCallerSavingCode(AI.InstrnsBefore, AI.InstrnsAfter, MInst,
469 MBB.getBasicBlock());
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000470 }
Vikram S. Advebc001b22003-07-25 21:06:09 +0000471
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000472 // Now insert spill code for remaining operands not allocated to
473 // registers. This must be done even for call return instructions
474 // since those are not handled by the special code above.
Vikram S. Adve814030a2003-07-29 19:49:21 +0000475 if (instrNeedsSpills)
Brian Gaekeaf843702003-10-22 20:22:53 +0000476 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
Vikram S. Adve814030a2003-07-29 19:49:21 +0000477 MachineOperand& Op = MInst->getOperand(OpNum);
478 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
Brian Gaekeaf843702003-10-22 20:22:53 +0000479 Op.getType() == MachineOperand::MO_CCRegister) {
Vikram S. Adve814030a2003-07-29 19:49:21 +0000480 const Value* Val = Op.getVRegValue();
Brian Gaeke4efe3422003-09-21 01:23:46 +0000481 if (const LiveRange *LR = LRI->getLiveRangeForValue(Val))
Vikram S. Adve814030a2003-07-29 19:49:21 +0000482 if (LR->isMarkedForSpill())
483 insertCode4SpilledLR(LR, MII, MBB, OpNum);
484 }
485 } // for each operand
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000486}
487
Brian Gaekeaf843702003-10-22 20:22:53 +0000488/// Iterate over all the MachineBasicBlocks in the current function and set
489/// the allocated registers for each instruction (using updateInstruction()),
490/// after register allocation is complete. Then move code out of delay slots.
491///
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000492void PhyRegAlloc::updateMachineCode()
493{
Chris Lattner7e708292002-06-25 16:13:24 +0000494 // Insert any instructions needed at method entry
Brian Gaeke4efe3422003-09-21 01:23:46 +0000495 MachineBasicBlock::iterator MII = MF->front().begin();
496 PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MF->front(), MII,
Chris Lattner7e708292002-06-25 16:13:24 +0000497 "At function entry: \n");
498 assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
499 "InstrsAfter should be unnecessary since we are just inserting at "
500 "the function entry point here.");
Vikram S. Adve48762092002-04-25 04:34:15 +0000501
Brian Gaeke4efe3422003-09-21 01:23:46 +0000502 for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
Chris Lattner2fbfdcf2002-04-07 20:49:59 +0000503 BBI != BBE; ++BBI) {
Chris Lattnerf726e772002-10-28 19:22:04 +0000504 MachineBasicBlock &MBB = *BBI;
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000505
506 // Iterate over all machine instructions in BB and mark operands with
507 // their assigned registers or insert spill code, as appropriate.
508 // Also, fix operands of call/return instructions.
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000509 for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
Vikram S. Adve814030a2003-07-29 19:49:21 +0000510 if (! TM.getInstrInfo().isDummyPhiInstr((*MII)->getOpCode()))
511 updateInstruction(MII, MBB);
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000512
513 // Now, move code out of delay slots of branches and returns if needed.
514 // (Also, move "after" code from calls to the last delay slot instruction.)
515 // Moving code out of delay slots is needed in 2 situations:
516 // (1) If this is a branch and it needs instructions inserted after it,
517 // move any existing instructions out of the delay slot so that the
518 // instructions can go into the delay slot. This only supports the
519 // case that #instrsAfter <= #delay slots.
520 //
521 // (2) If any instruction in the delay slot needs
522 // instructions inserted, move it out of the delay slot and before the
523 // branch because putting code before or after it would be VERY BAD!
524 //
525 // If the annul bit of the branch is set, neither of these is legal!
526 // If so, we need to handle spill differently but annulling is not yet used.
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000527 for (MachineBasicBlock::iterator MII = MBB.begin();
528 MII != MBB.end(); ++MII)
529 if (unsigned delaySlots =
Brian Gaekeaf843702003-10-22 20:22:53 +0000530 TM.getInstrInfo().getNumDelaySlots((*MII)->getOpCode())) {
Vikram S. Adve814030a2003-07-29 19:49:21 +0000531 MachineInstr *MInst = *MII, *DelaySlotMI = *(MII+1);
532
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000533 // Check the 2 conditions above:
534 // (1) Does a branch need instructions added after it?
535 // (2) O/w does delay slot instr. need instrns before or after?
Vikram S. Adve814030a2003-07-29 19:49:21 +0000536 bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpCode()) ||
537 TM.getInstrInfo().isReturn(MInst->getOpCode()));
538 bool cond1 = (isBranch &&
539 AddedInstrMap.count(MInst) &&
540 AddedInstrMap[MInst].InstrnsAfter.size() > 0);
541 bool cond2 = (AddedInstrMap.count(DelaySlotMI) &&
542 (AddedInstrMap[DelaySlotMI].InstrnsBefore.size() > 0 ||
543 AddedInstrMap[DelaySlotMI].InstrnsAfter.size() > 0));
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000544
Brian Gaekeaf843702003-10-22 20:22:53 +0000545 if (cond1 || cond2) {
Vikram S. Adve814030a2003-07-29 19:49:21 +0000546 assert((MInst->getOpCodeFlags() & AnnulFlag) == 0 &&
547 "FIXME: Moving an annulled delay slot instruction!");
548 assert(delaySlots==1 &&
549 "InsertBefore does not yet handle >1 delay slots!");
550 InsertBefore(DelaySlotMI, MBB, MII); // MII pts back to branch
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000551
552 // In case (1), delete it and don't replace with anything!
553 // Otherwise (i.e., case (2) only) replace it with a NOP.
554 if (cond1) {
Vikram S. Adve814030a2003-07-29 19:49:21 +0000555 DeleteInstruction(MBB, ++MII); // MII now points to next inst.
556 --MII; // reset MII for ++MII of loop
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000557 }
Vikram S. Adve814030a2003-07-29 19:49:21 +0000558 else
559 SubstituteInPlace(BuildMI(TM.getInstrInfo().getNOPOpCode(),1),
560 MBB, MII+1); // replace with NOP
561
562 if (DEBUG_RA) {
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000563 std::cerr << "\nRegAlloc: Moved instr. with added code: "
Vikram S. Adve814030a2003-07-29 19:49:21 +0000564 << *DelaySlotMI
565 << " out of delay slots of instr: " << *MInst;
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000566 }
567 }
Vikram S. Adve814030a2003-07-29 19:49:21 +0000568 else
569 // For non-branch instr with delay slots (probably a call), move
570 // InstrAfter to the instr. in the last delay slot.
571 move2DelayedInstr(*MII, *(MII+delaySlots));
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000572 }
573
574 // Finally iterate over all instructions in BB and insert before/after
Vikram S. Advebc001b22003-07-25 21:06:09 +0000575 for (MachineBasicBlock::iterator MII=MBB.begin(); MII != MBB.end(); ++MII) {
Vikram S. Adve48762092002-04-25 04:34:15 +0000576 MachineInstr *MInst = *MII;
Vikram S. Advebc001b22003-07-25 21:06:09 +0000577
Ruchira Sasanka65480b72001-11-10 21:21:36 +0000578 // do not process Phis
Vikram S. Advebc001b22003-07-25 21:06:09 +0000579 if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()))
Ruchira Sasanka65480b72001-11-10 21:21:36 +0000580 continue;
581
Vikram S. Advebc001b22003-07-25 21:06:09 +0000582 // if there are any added instructions...
Chris Lattner7e708292002-06-25 16:13:24 +0000583 if (AddedInstrMap.count(MInst)) {
Vikram S. Advebc001b22003-07-25 21:06:09 +0000584 AddedInstrns &CallAI = AddedInstrMap[MInst];
585
586#ifndef NDEBUG
Vikram S. Adve814030a2003-07-29 19:49:21 +0000587 bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpCode()) ||
588 TM.getInstrInfo().isReturn(MInst->getOpCode()));
589 assert((!isBranch ||
590 AddedInstrMap[MInst].InstrnsAfter.size() <=
591 TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) &&
592 "Cannot put more than #delaySlots instrns after "
593 "branch or return! Need to handle temps differently.");
594#endif
595
596#ifndef NDEBUG
Vikram S. Advebc001b22003-07-25 21:06:09 +0000597 // Temporary sanity checking code to detect whether the same machine
598 // instruction is ever inserted twice before/after a call.
599 // I suspect this is happening but am not sure. --Vikram, 7/1/03.
Vikram S. Advebc001b22003-07-25 21:06:09 +0000600 std::set<const MachineInstr*> instrsSeen;
601 for (int i = 0, N = CallAI.InstrnsBefore.size(); i < N; ++i) {
602 assert(instrsSeen.count(CallAI.InstrnsBefore[i]) == 0 &&
603 "Duplicate machine instruction in InstrnsBefore!");
604 instrsSeen.insert(CallAI.InstrnsBefore[i]);
605 }
606 for (int i = 0, N = CallAI.InstrnsAfter.size(); i < N; ++i) {
607 assert(instrsSeen.count(CallAI.InstrnsAfter[i]) == 0 &&
608 "Duplicate machine instruction in InstrnsBefore/After!");
609 instrsSeen.insert(CallAI.InstrnsAfter[i]);
610 }
611#endif
612
613 // Now add the instructions before/after this MI.
614 // We do this here to ensure that spill for an instruction is inserted
615 // as close as possible to an instruction (see above insertCode4Spill)
Vikram S. Advebc001b22003-07-25 21:06:09 +0000616 if (! CallAI.InstrnsBefore.empty())
617 PrependInstructions(CallAI.InstrnsBefore, MBB, MII,"");
618
619 if (! CallAI.InstrnsAfter.empty())
620 AppendInstructions(CallAI.InstrnsAfter, MBB, MII,"");
621
622 } // if there are any added instructions
Ruchira Sasankac4d4b762001-10-16 01:23:19 +0000623 } // for each machine instruction
Ruchira Sasanka0931a012001-09-15 19:06:58 +0000624 }
625}
626
627
Brian Gaekeaf843702003-10-22 20:22:53 +0000628/// Insert spill code for AN operand whose LR was spilled. May be called
629/// repeatedly for a single MachineInstr if it has many spilled operands. On
630/// each call, it finds a register which is not live at that instruction and
631/// also which is not used by other spilled operands of the same
632/// instruction. Then it uses this register temporarily to accommodate the
633/// spilled value.
634///
Ruchira Sasanka5a61d852001-11-08 16:43:25 +0000635void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
Vikram S. Adve814030a2003-07-29 19:49:21 +0000636 MachineBasicBlock::iterator& MII,
637 MachineBasicBlock &MBB,
Ruchira Sasanka5a61d852001-11-08 16:43:25 +0000638 const unsigned OpNum) {
Vikram S. Adve814030a2003-07-29 19:49:21 +0000639 MachineInstr *MInst = *MII;
640 const BasicBlock *BB = MBB.getBasicBlock();
641
Vikram S. Advead9c9782002-09-28 17:02:40 +0000642 assert((! TM.getInstrInfo().isCall(MInst->getOpCode()) || OpNum == 0) &&
643 "Outgoing arg of a call must be handled elsewhere (func arg ok)");
644 assert(! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
645 "Return value of a ret must be handled elsewhere");
Ruchira Sasankaba9d5db2001-11-15 20:23:19 +0000646
Ruchira Sasanka5a61d852001-11-08 16:43:25 +0000647 MachineOperand& Op = MInst->getOperand(OpNum);
Vikram S. Adve5f2180c2003-05-27 00:05:23 +0000648 bool isDef = Op.opIsDefOnly();
649 bool isDefAndUse = Op.opIsDefAndUse();
Vikram S. Advebc001b22003-07-25 21:06:09 +0000650 unsigned RegType = MRI.getRegTypeForLR(LR);
Ruchira Sasanka5a61d852001-11-08 16:43:25 +0000651 int SpillOff = LR->getSpillOffFromFP();
652 RegClass *RC = LR->getRegClass();
Vikram S. Adve814030a2003-07-29 19:49:21 +0000653
654 // Get the live-variable set to find registers free before this instr.
Vikram S. Advefeb32982003-08-12 22:22:24 +0000655 const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
656
657#ifndef NDEBUG
658 // If this instr. is in the delay slot of a branch or return, we need to
659 // include all live variables before that branch or return -- we don't want to
660 // trample those! Verify that the set is included in the LV set before MInst.
Vikram S. Adve814030a2003-07-29 19:49:21 +0000661 if (MII != MBB.begin()) {
662 MachineInstr *PredMI = *(MII-1);
Vikram S. Advefeb32982003-08-12 22:22:24 +0000663 if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode()))
664 assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
665 .empty() && "Live-var set before branch should be included in "
666 "live-var set of each delay slot instruction!");
Vikram S. Adve814030a2003-07-29 19:49:21 +0000667 }
Vikram S. Advefeb32982003-08-12 22:22:24 +0000668#endif
Vikram S. Adve00521d72001-11-12 23:26:35 +0000669
Brian Gaekeaf843702003-10-22 20:22:53 +0000670 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
Ruchira Sasanka5a61d852001-11-08 16:43:25 +0000671
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000672 std::vector<MachineInstr*> MIBef, MIAft;
673 std::vector<MachineInstr*> AdIMid;
Ruchira Sasankaba9d5db2001-11-15 20:23:19 +0000674
Vikram S. Adve3bf08922003-07-10 19:42:55 +0000675 // Choose a register to hold the spilled value, if one was not preallocated.
676 // This may insert code before and after MInst to free up the value. If so,
677 // this code should be first/last in the spill sequence before/after MInst.
678 int TmpRegU=(LR->hasColor()
Brian Gaeke59b1c562003-09-24 17:50:28 +0000679 ? MRI.getUnifiedRegNum(LR->getRegClassID(),LR->getColor())
Vikram S. Adve3bf08922003-07-10 19:42:55 +0000680 : getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef,MIAft));
Ruchira Sasankaba9d5db2001-11-15 20:23:19 +0000681
Vikram S. Advef5af6362002-07-08 23:15:32 +0000682 // Set the operand first so that it this register does not get used
683 // as a scratch register for later calls to getUsableUniRegAtMI below
684 MInst->SetRegForOperand(OpNum, TmpRegU);
685
686 // get the added instructions for this instruction
Chris Lattner0b0ffa02002-04-09 05:13:04 +0000687 AddedInstrns &AI = AddedInstrMap[MInst];
Vikram S. Advef5af6362002-07-08 23:15:32 +0000688
689 // We may need a scratch register to copy the spilled value to/from memory.
690 // This may itself have to insert code to free up a scratch register.
691 // Any such code should go before (after) the spill code for a load (store).
Vikram S. Adved0d06ad2003-05-31 07:32:01 +0000692 // The scratch reg is not marked as used because it is only used
693 // for the copy and not used across MInst.
Vikram S. Advef5af6362002-07-08 23:15:32 +0000694 int scratchRegType = -1;
695 int scratchReg = -1;
Brian Gaekeaf843702003-10-22 20:22:53 +0000696 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
Chris Lattner27a08932002-10-22 23:16:21 +0000697 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
698 MInst, MIBef, MIAft);
Vikram S. Advef5af6362002-07-08 23:15:32 +0000699 assert(scratchReg != MRI.getInvalidRegNum());
Vikram S. Advef5af6362002-07-08 23:15:32 +0000700 }
701
702 if (!isDef || isDefAndUse) {
Ruchira Sasanka5a61d852001-11-08 16:43:25 +0000703 // for a USE, we have to load the value of LR from stack to a TmpReg
704 // and use the TmpReg as one operand of instruction
Vikram S. Advedabb41d2002-05-19 15:29:31 +0000705
Vikram S. Advef5af6362002-07-08 23:15:32 +0000706 // actual loading instruction(s)
Vikram S. Adve814030a2003-07-29 19:49:21 +0000707 MRI.cpMem2RegMI(AdIMid, MRI.getFramePointer(), SpillOff, TmpRegU,
708 RegType, scratchReg);
Ruchira Sasanka226f1f02001-11-08 19:11:30 +0000709
Vikram S. Advef5af6362002-07-08 23:15:32 +0000710 // the actual load should be after the instructions to free up TmpRegU
711 MIBef.insert(MIBef.end(), AdIMid.begin(), AdIMid.end());
712 AdIMid.clear();
713 }
714
Vikram S. Adve3bf08922003-07-10 19:42:55 +0000715 if (isDef || isDefAndUse) { // if this is a Def
Ruchira Sasanka5a61d852001-11-08 16:43:25 +0000716 // for a DEF, we have to store the value produced by this instruction
717 // on the stack position allocated for this LR
Vikram S. Advedabb41d2002-05-19 15:29:31 +0000718
Vikram S. Advef5af6362002-07-08 23:15:32 +0000719 // actual storing instruction(s)
Vikram S. Adve814030a2003-07-29 19:49:21 +0000720 MRI.cpReg2MemMI(AdIMid, TmpRegU, MRI.getFramePointer(), SpillOff,
721 RegType, scratchReg);
Vikram S. Advedabb41d2002-05-19 15:29:31 +0000722
Vikram S. Advef5af6362002-07-08 23:15:32 +0000723 MIAft.insert(MIAft.begin(), AdIMid.begin(), AdIMid.end());
Ruchira Sasanka5a61d852001-11-08 16:43:25 +0000724 } // if !DEF
Vikram S. Advedabb41d2002-05-19 15:29:31 +0000725
Vikram S. Advef5af6362002-07-08 23:15:32 +0000726 // Finally, insert the entire spill code sequences before/after MInst
727 AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
728 AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
729
Chris Lattner7e708292002-06-25 16:13:24 +0000730 if (DEBUG_RA) {
Chris Lattnerc083dcc2003-09-01 20:05:47 +0000731 std::cerr << "\nFor Inst:\n " << *MInst;
732 std::cerr << "SPILLED LR# " << LR->getUserIGNode()->getIndex();
733 std::cerr << "; added Instructions:";
Anand Shuklad58290e2002-07-09 19:18:56 +0000734 for_each(MIBef.begin(), MIBef.end(), std::mem_fun(&MachineInstr::dump));
735 for_each(MIAft.begin(), MIAft.end(), std::mem_fun(&MachineInstr::dump));
Chris Lattner7e708292002-06-25 16:13:24 +0000736 }
Ruchira Sasanka5a61d852001-11-08 16:43:25 +0000737}
738
739
Brian Gaekeaf843702003-10-22 20:22:53 +0000740/// Insert caller saving/restoring instructions before/after a call machine
741/// instruction (before or after any other instructions that were inserted for
742/// the call).
743///
Vikram S. Adve814030a2003-07-29 19:49:21 +0000744void
745PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
746 std::vector<MachineInstr*> &instrnsAfter,
747 MachineInstr *CallMI,
Brian Gaekeaf843702003-10-22 20:22:53 +0000748 const BasicBlock *BB) {
Vikram S. Adve814030a2003-07-29 19:49:21 +0000749 assert(TM.getInstrInfo().isCall(CallMI->getOpCode()));
750
Brian Gaeke43ce8fe2003-09-21 02:24:09 +0000751 // hash set to record which registers were saved/restored
Vikram S. Adve814030a2003-07-29 19:49:21 +0000752 hash_set<unsigned> PushedRegSet;
753
754 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
755
756 // if the call is to a instrumentation function, do not insert save and
757 // restore instructions the instrumentation function takes care of save
758 // restore for volatile regs.
759 //
760 // FIXME: this should be made general, not specific to the reoptimizer!
Vikram S. Adve814030a2003-07-29 19:49:21 +0000761 const Function *Callee = argDesc->getCallInst()->getCalledFunction();
762 bool isLLVMFirstTrigger = Callee && Callee->getName() == "llvm_first_trigger";
763
764 // Now check if the call has a return value (using argDesc) and if so,
765 // find the LR of the TmpInstruction representing the return value register.
766 // (using the last or second-last *implicit operand* of the call MI).
767 // Insert it to to the PushedRegSet since we must not save that register
768 // and restore it after the call.
769 // We do this because, we look at the LV set *after* the instruction
770 // to determine, which LRs must be saved across calls. The return value
771 // of the call is live in this set - but we must not save/restore it.
Vikram S. Adve814030a2003-07-29 19:49:21 +0000772 if (const Value *origRetVal = argDesc->getReturnValue()) {
773 unsigned retValRefNum = (CallMI->getNumImplicitRefs() -
774 (argDesc->getIndirectFuncPtr()? 1 : 2));
775 const TmpInstruction* tmpRetVal =
776 cast<TmpInstruction>(CallMI->getImplicitRef(retValRefNum));
777 assert(tmpRetVal->getOperand(0) == origRetVal &&
778 tmpRetVal->getType() == origRetVal->getType() &&
779 "Wrong implicit ref?");
Brian Gaeke4efe3422003-09-21 01:23:46 +0000780 LiveRange *RetValLR = LRI->getLiveRangeForValue(tmpRetVal);
Vikram S. Adve814030a2003-07-29 19:49:21 +0000781 assert(RetValLR && "No LR for RetValue of call");
782
783 if (! RetValLR->isMarkedForSpill())
784 PushedRegSet.insert(MRI.getUnifiedRegNum(RetValLR->getRegClassID(),
785 RetValLR->getColor()));
786 }
787
788 const ValueSet &LVSetAft = LVI->getLiveVarSetAfterMInst(CallMI, BB);
789 ValueSet::const_iterator LIt = LVSetAft.begin();
790
791 // for each live var in live variable set after machine inst
792 for( ; LIt != LVSetAft.end(); ++LIt) {
Brian Gaeke43ce8fe2003-09-21 02:24:09 +0000793 // get the live range corresponding to live var
Brian Gaeke4efe3422003-09-21 01:23:46 +0000794 LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
Vikram S. Adve814030a2003-07-29 19:49:21 +0000795
796 // LR can be null if it is a const since a const
797 // doesn't have a dominating def - see Assumptions above
Brian Gaekeaf843702003-10-22 20:22:53 +0000798 if (LR) {
799 if (! LR->isMarkedForSpill()) {
Vikram S. Adve814030a2003-07-29 19:49:21 +0000800 assert(LR->hasColor() && "LR is neither spilled nor colored?");
801 unsigned RCID = LR->getRegClassID();
802 unsigned Color = LR->getColor();
803
804 if (MRI.isRegVolatile(RCID, Color) ) {
Brian Gaeke43ce8fe2003-09-21 02:24:09 +0000805 // if this is a call to the first-level reoptimizer
806 // instrumentation entry point, and the register is not
807 // modified by call, don't save and restore it.
Vikram S. Adve814030a2003-07-29 19:49:21 +0000808 if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color))
809 continue;
810
811 // if the value is in both LV sets (i.e., live before and after
812 // the call machine instruction)
Vikram S. Adve814030a2003-07-29 19:49:21 +0000813 unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
814
Brian Gaeke43ce8fe2003-09-21 02:24:09 +0000815 // if we haven't already pushed this register...
Vikram S. Adve814030a2003-07-29 19:49:21 +0000816 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
Vikram S. Adve814030a2003-07-29 19:49:21 +0000817 unsigned RegType = MRI.getRegTypeForLR(LR);
818
819 // Now get two instructions - to push on stack and pop from stack
820 // and add them to InstrnsBefore and InstrnsAfter of the
821 // call instruction
Vikram S. Adve814030a2003-07-29 19:49:21 +0000822 int StackOff =
Brian Gaeke4efe3422003-09-21 01:23:46 +0000823 MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
Vikram S. Adve814030a2003-07-29 19:49:21 +0000824
825 //---- Insert code for pushing the reg on stack ----------
826
827 std::vector<MachineInstr*> AdIBef, AdIAft;
828
829 // We may need a scratch register to copy the saved value
830 // to/from memory. This may itself have to insert code to
831 // free up a scratch register. Any such code should go before
832 // the save code. The scratch register, if any, is by default
833 // temporary and not "used" by the instruction unless the
834 // copy code itself decides to keep the value in the scratch reg.
835 int scratchRegType = -1;
836 int scratchReg = -1;
837 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
838 { // Find a register not live in the LVSet before CallMI
839 const ValueSet &LVSetBef =
840 LVI->getLiveVarSetBeforeMInst(CallMI, BB);
841 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
842 CallMI, AdIBef, AdIAft);
843 assert(scratchReg != MRI.getInvalidRegNum());
844 }
845
846 if (AdIBef.size() > 0)
847 instrnsBefore.insert(instrnsBefore.end(),
848 AdIBef.begin(), AdIBef.end());
849
850 MRI.cpReg2MemMI(instrnsBefore, Reg, MRI.getFramePointer(),
851 StackOff, RegType, scratchReg);
852
853 if (AdIAft.size() > 0)
854 instrnsBefore.insert(instrnsBefore.end(),
855 AdIAft.begin(), AdIAft.end());
856
857 //---- Insert code for popping the reg from the stack ----------
Vikram S. Adve814030a2003-07-29 19:49:21 +0000858 AdIBef.clear();
859 AdIAft.clear();
860
861 // We may need a scratch register to copy the saved value
862 // from memory. This may itself have to insert code to
863 // free up a scratch register. Any such code should go
864 // after the save code. As above, scratch is not marked "used".
Vikram S. Adve814030a2003-07-29 19:49:21 +0000865 scratchRegType = -1;
866 scratchReg = -1;
867 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
868 { // Find a register not live in the LVSet after CallMI
869 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetAft,
870 CallMI, AdIBef, AdIAft);
871 assert(scratchReg != MRI.getInvalidRegNum());
872 }
873
874 if (AdIBef.size() > 0)
875 instrnsAfter.insert(instrnsAfter.end(),
876 AdIBef.begin(), AdIBef.end());
877
878 MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff,
879 Reg, RegType, scratchReg);
880
881 if (AdIAft.size() > 0)
882 instrnsAfter.insert(instrnsAfter.end(),
883 AdIAft.begin(), AdIAft.end());
884
885 PushedRegSet.insert(Reg);
886
887 if(DEBUG_RA) {
888 std::cerr << "\nFor call inst:" << *CallMI;
889 std::cerr << " -inserted caller saving instrs: Before:\n\t ";
890 for_each(instrnsBefore.begin(), instrnsBefore.end(),
891 std::mem_fun(&MachineInstr::dump));
892 std::cerr << " -and After:\n\t ";
893 for_each(instrnsAfter.begin(), instrnsAfter.end(),
894 std::mem_fun(&MachineInstr::dump));
895 }
896 } // if not already pushed
Vikram S. Adve814030a2003-07-29 19:49:21 +0000897 } // if LR has a volatile color
Vikram S. Adve814030a2003-07-29 19:49:21 +0000898 } // if LR has color
Vikram S. Adve814030a2003-07-29 19:49:21 +0000899 } // if there is a LR for Var
Vikram S. Adve814030a2003-07-29 19:49:21 +0000900 } // for each value in the LV set after instruction
901}
902
903
Brian Gaekeaf843702003-10-22 20:22:53 +0000904/// Returns the unified register number of a temporary register to be used
905/// BEFORE MInst. If no register is available, it will pick one and modify
906/// MIBef and MIAft to contain instructions used to free up this returned
907/// register.
908///
Vikram S. Advef5af6362002-07-08 23:15:32 +0000909int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
910 const ValueSet *LVSetBef,
911 MachineInstr *MInst,
912 std::vector<MachineInstr*>& MIBef,
913 std::vector<MachineInstr*>& MIAft) {
Chris Lattner133f0792002-10-28 04:45:29 +0000914 RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
Vikram S. Advef5af6362002-07-08 23:15:32 +0000915
Brian Gaekeaf843702003-10-22 20:22:53 +0000916 int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
Vikram S. Advef5af6362002-07-08 23:15:32 +0000917
918 if (RegU == -1) {
Ruchira Sasanka80b1a1a2001-11-03 20:41:22 +0000919 // we couldn't find an unused register. Generate code to free up a reg by
Ruchira Sasanka174bded2001-10-28 18:12:02 +0000920 // saving it on stack and restoring after the instruction
Vikram S. Advef5af6362002-07-08 23:15:32 +0000921
Brian Gaeke4efe3422003-09-21 01:23:46 +0000922 int TmpOff = MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
Vikram S. Adve12af1642001-11-08 04:48:50 +0000923
Vikram S. Advebc001b22003-07-25 21:06:09 +0000924 RegU = getUniRegNotUsedByThisInst(RC, RegType, MInst);
Vikram S. Advedabb41d2002-05-19 15:29:31 +0000925
Vikram S. Advef5af6362002-07-08 23:15:32 +0000926 // Check if we need a scratch register to copy this register to memory.
927 int scratchRegType = -1;
Brian Gaekeaf843702003-10-22 20:22:53 +0000928 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
Chris Lattner133f0792002-10-28 04:45:29 +0000929 int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
930 MInst, MIBef, MIAft);
Vikram S. Advef5af6362002-07-08 23:15:32 +0000931 assert(scratchReg != MRI.getInvalidRegNum());
932
933 // We may as well hold the value in the scratch register instead
934 // of copying it to memory and back. But we have to mark the
935 // register as used by this instruction, so it does not get used
936 // as a scratch reg. by another operand or anyone else.
Chris Lattner3fd1f5b2003-08-05 22:11:13 +0000937 ScratchRegsUsed.insert(std::make_pair(MInst, scratchReg));
Vikram S. Advef5af6362002-07-08 23:15:32 +0000938 MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
939 MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
Brian Gaekeaf843702003-10-22 20:22:53 +0000940 } else { // the register can be copied directly to/from memory so do it.
Vikram S. Advef5af6362002-07-08 23:15:32 +0000941 MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
942 MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
Brian Gaekeaf843702003-10-22 20:22:53 +0000943 }
Ruchira Sasanka174bded2001-10-28 18:12:02 +0000944 }
Vikram S. Advef5af6362002-07-08 23:15:32 +0000945
Ruchira Sasankaba9d5db2001-11-15 20:23:19 +0000946 return RegU;
Ruchira Sasanka174bded2001-10-28 18:12:02 +0000947}
948
Vikram S. Adve814030a2003-07-29 19:49:21 +0000949
Brian Gaekeaf843702003-10-22 20:22:53 +0000950/// Returns the register-class register number of a new unused register that
951/// can be used to accommodate a temporary value. May be called repeatedly
952/// for a single MachineInstr. On each call, it finds a register which is not
953/// live at that instruction and which is not used by any spilled operands of
954/// that instruction.
955///
956int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC, const int RegType,
Vikram S. Adve814030a2003-07-29 19:49:21 +0000957 const MachineInstr *MInst,
958 const ValueSet* LVSetBef) {
Vikram S. Advebc001b22003-07-25 21:06:09 +0000959 RC->clearColorsUsed(); // Reset array
Vikram S. Adve814030a2003-07-29 19:49:21 +0000960
961 if (LVSetBef == NULL) {
962 LVSetBef = &LVI->getLiveVarSetBeforeMInst(MInst);
963 assert(LVSetBef != NULL && "Unable to get live-var set before MInst?");
964 }
965
Chris Lattner296b7732002-02-05 02:52:05 +0000966 ValueSet::const_iterator LIt = LVSetBef->begin();
Ruchira Sasanka174bded2001-10-28 18:12:02 +0000967
968 // for each live var in live variable set after machine inst
Chris Lattner7e708292002-06-25 16:13:24 +0000969 for ( ; LIt != LVSetBef->end(); ++LIt) {
Brian Gaeke43ce8fe2003-09-21 02:24:09 +0000970 // Get the live range corresponding to live var, and its RegClass
Brian Gaeke4efe3422003-09-21 01:23:46 +0000971 LiveRange *const LRofLV = LRI->getLiveRangeForValue(*LIt );
Ruchira Sasanka174bded2001-10-28 18:12:02 +0000972
973 // LR can be null if it is a const since a const
974 // doesn't have a dominating def - see Assumptions above
Vikram S. Advebc001b22003-07-25 21:06:09 +0000975 if (LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor())
976 RC->markColorsUsed(LRofLV->getColor(),
977 MRI.getRegTypeForLR(LRofLV), RegType);
Ruchira Sasanka174bded2001-10-28 18:12:02 +0000978 }
979
980 // It is possible that one operand of this MInst was already spilled
981 // and it received some register temporarily. If that's the case,
982 // it is recorded in machine operand. We must skip such registers.
Vikram S. Advebc001b22003-07-25 21:06:09 +0000983 setRelRegsUsedByThisInst(RC, RegType, MInst);
Ruchira Sasanka174bded2001-10-28 18:12:02 +0000984
Vikram S. Advebc001b22003-07-25 21:06:09 +0000985 int unusedReg = RC->getUnusedColor(RegType); // find first unused color
986 if (unusedReg >= 0)
987 return MRI.getUnifiedRegNum(RC->getID(), unusedReg);
988
Chris Lattner85c54652002-05-23 15:50:03 +0000989 return -1;
Ruchira Sasanka174bded2001-10-28 18:12:02 +0000990}
991
992
Brian Gaekeaf843702003-10-22 20:22:53 +0000993/// Return the unified register number of a register in class RC which is not
994/// used by any operands of MInst.
995///
Ruchira Sasankaba9d5db2001-11-15 20:23:19 +0000996int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
Vikram S. Advebc001b22003-07-25 21:06:09 +0000997 const int RegType,
Chris Lattner85c54652002-05-23 15:50:03 +0000998 const MachineInstr *MInst) {
Vikram S. Advebc001b22003-07-25 21:06:09 +0000999 RC->clearColorsUsed();
Ruchira Sasankaba9d5db2001-11-15 20:23:19 +00001000
Vikram S. Advebc001b22003-07-25 21:06:09 +00001001 setRelRegsUsedByThisInst(RC, RegType, MInst);
Ruchira Sasankaba9d5db2001-11-15 20:23:19 +00001002
Vikram S. Advebc001b22003-07-25 21:06:09 +00001003 // find the first unused color
1004 int unusedReg = RC->getUnusedColor(RegType);
1005 assert(unusedReg >= 0 &&
1006 "FATAL: No free register could be found in reg class!!");
Ruchira Sasankaba9d5db2001-11-15 20:23:19 +00001007
Vikram S. Advebc001b22003-07-25 21:06:09 +00001008 return MRI.getUnifiedRegNum(RC->getID(), unusedReg);
Ruchira Sasankaba9d5db2001-11-15 20:23:19 +00001009}
1010
1011
Brian Gaekeaf843702003-10-22 20:22:53 +00001012/// Modify the IsColorUsedArr of register class RC, by setting the bits
1013/// corresponding to register RegNo. This is a helper method of
1014/// setRelRegsUsedByThisInst().
1015///
Chris Lattner3bed95b2003-08-05 21:55:58 +00001016static void markRegisterUsed(int RegNo, RegClass *RC, int RegType,
1017 const TargetRegInfo &TRI) {
1018 unsigned classId = 0;
1019 int classRegNum = TRI.getClassRegNum(RegNo, classId);
1020 if (RC->getID() == classId)
1021 RC->markColorsUsed(classRegNum, RegType, RegType);
1022}
1023
1024void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
Brian Gaekeaf843702003-10-22 20:22:53 +00001025 const MachineInstr *MI) {
Chris Lattner3bed95b2003-08-05 21:55:58 +00001026 assert(OperandsColoredMap[MI] == true &&
Vikram S. Adved0d06ad2003-05-31 07:32:01 +00001027 "Illegal to call setRelRegsUsedByThisInst() until colored operands "
1028 "are marked for an instruction.");
Ruchira Sasanka174bded2001-10-28 18:12:02 +00001029
Brian Gaekeaf843702003-10-22 20:22:53 +00001030 // Add the registers already marked as used by the instruction. Both
1031 // explicit and implicit operands are set.
Chris Lattner3bed95b2003-08-05 21:55:58 +00001032 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
1033 if (MI->getOperand(i).hasAllocatedReg())
1034 markRegisterUsed(MI->getOperand(i).getAllocatedRegNum(), RC, RegType,MRI);
1035
1036 for (unsigned i = 0, e = MI->getNumImplicitRefs(); i != e; ++i)
1037 if (MI->getImplicitOp(i).hasAllocatedReg())
1038 markRegisterUsed(MI->getImplicitOp(i).getAllocatedRegNum(), RC,
1039 RegType,MRI);
1040
Chris Lattner3fd1f5b2003-08-05 22:11:13 +00001041 // Add all of the scratch registers that are used to save values across the
1042 // instruction (e.g., for saving state register values).
1043 std::pair<ScratchRegsUsedTy::iterator, ScratchRegsUsedTy::iterator>
1044 IR = ScratchRegsUsed.equal_range(MI);
1045 for (ScratchRegsUsedTy::iterator I = IR.first; I != IR.second; ++I)
1046 markRegisterUsed(I->second, RC, RegType, MRI);
Vikram S. Adved0d06ad2003-05-31 07:32:01 +00001047
Vikram S. Advef5af6362002-07-08 23:15:32 +00001048 // If there are implicit references, mark their allocated regs as well
Chris Lattner3bed95b2003-08-05 21:55:58 +00001049 for (unsigned z=0; z < MI->getNumImplicitRefs(); z++)
Vikram S. Advef5af6362002-07-08 23:15:32 +00001050 if (const LiveRange*
Brian Gaeke4efe3422003-09-21 01:23:46 +00001051 LRofImpRef = LRI->getLiveRangeForValue(MI->getImplicitRef(z)))
Vikram S. Advef5af6362002-07-08 23:15:32 +00001052 if (LRofImpRef->hasColor())
1053 // this implicit reference is in a LR that received a color
Vikram S. Advebc001b22003-07-25 21:06:09 +00001054 RC->markColorsUsed(LRofImpRef->getColor(),
1055 MRI.getRegTypeForLR(LRofImpRef), RegType);
Ruchira Sasanka174bded2001-10-28 18:12:02 +00001056}
1057
1058
Brian Gaekeaf843702003-10-22 20:22:53 +00001059/// If there are delay slots for an instruction, the instructions added after
1060/// it must really go after the delayed instruction(s). So, we Move the
1061/// InstrAfter of that instruction to the corresponding delayed instruction
1062/// using the following method.
1063///
Vikram S. Adved0d06ad2003-05-31 07:32:01 +00001064void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
1065 const MachineInstr *DelayedMI)
1066{
Vikram S. Advefeb32982003-08-12 22:22:24 +00001067 // "added after" instructions of the original instr
1068 std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
1069
1070 if (DEBUG_RA && OrigAft.size() > 0) {
Chris Lattnerc083dcc2003-09-01 20:05:47 +00001071 std::cerr << "\nRegAlloc: Moved InstrnsAfter for: " << *OrigMI;
1072 std::cerr << " to last delay slot instrn: " << *DelayedMI;
Vikram S. Adve814030a2003-07-29 19:49:21 +00001073 }
1074
Ruchira Sasanka251d8db2001-10-23 21:38:00 +00001075 // "added after" instructions of the delayed instr
Vikram S. Adve814030a2003-07-29 19:49:21 +00001076 std::vector<MachineInstr *> &DelayedAft=AddedInstrMap[DelayedMI].InstrnsAfter;
Ruchira Sasanka251d8db2001-10-23 21:38:00 +00001077
1078 // go thru all the "added after instructions" of the original instruction
Vikram S. Adved0d06ad2003-05-31 07:32:01 +00001079 // and append them to the "added after instructions" of the delayed
Ruchira Sasanka251d8db2001-10-23 21:38:00 +00001080 // instructions
Chris Lattner697954c2002-01-20 22:54:45 +00001081 DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end());
Ruchira Sasanka251d8db2001-10-23 21:38:00 +00001082
1083 // empty the "added after instructions" of the original instruction
1084 OrigAft.clear();
Ruchira Sasanka251d8db2001-10-23 21:38:00 +00001085}
Ruchira Sasanka0931a012001-09-15 19:06:58 +00001086
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +00001087
Ruchira Sasankaa5ab9642001-09-30 23:11:59 +00001088void PhyRegAlloc::colorIncomingArgs()
1089{
Brian Gaeke4efe3422003-09-21 01:23:46 +00001090 MRI.colorMethodArgs(Fn, *LRI, AddedInstrAtEntry.InstrnsBefore,
Vikram S. Adve814030a2003-07-29 19:49:21 +00001091 AddedInstrAtEntry.InstrnsAfter);
Ruchira Sasankaa5ab9642001-09-30 23:11:59 +00001092}
1093
Ruchira Sasankae727f852001-09-18 22:43:57 +00001094
Brian Gaekeaf843702003-10-22 20:22:53 +00001095/// Determine whether the suggested color of each live range is really usable,
1096/// and then call its setSuggestedColorUsable() method to record the answer. A
1097/// suggested color is NOT usable when the suggested color is volatile AND
1098/// when there are call interferences.
1099///
Ruchira Sasanka0e62aa62001-10-19 21:39:31 +00001100void PhyRegAlloc::markUnusableSugColors()
1101{
Brian Gaeke4efe3422003-09-21 01:23:46 +00001102 LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
1103 LiveRangeMapType::const_iterator HMIEnd = (LRI->getLiveRangeMap())->end();
Ruchira Sasanka0e62aa62001-10-19 21:39:31 +00001104
Brian Gaeke43ce8fe2003-09-21 02:24:09 +00001105 for (; HMI != HMIEnd ; ++HMI ) {
1106 if (HMI->first) {
1107 LiveRange *L = HMI->second; // get the LiveRange
Brian Gaeke59b1c562003-09-24 17:50:28 +00001108 if (L && L->hasSuggestedColor ())
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001109 L->setSuggestedColorUsable
1110 (!(MRI.isRegVolatile (L->getRegClassID (), L->getSuggestedColor ())
1111 && L->isCallInterference ()));
Brian Gaeke43ce8fe2003-09-21 02:24:09 +00001112 }
1113 } // for all LR's in hash map
Ruchira Sasanka0e62aa62001-10-19 21:39:31 +00001114}
1115
1116
Brian Gaekeaf843702003-10-22 20:22:53 +00001117/// For each live range that is spilled, allocates a new spill position on the
1118/// stack, and set the stack offsets of the live range that will be spilled to
1119/// that position. This must be called just after coloring the LRs.
1120///
Chris Lattner37730942002-02-05 03:52:29 +00001121void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
Chris Lattnerc083dcc2003-09-01 20:05:47 +00001122 if (DEBUG_RA) std::cerr << "\nSetting LR stack offsets for spills...\n";
Ruchira Sasanka0e62aa62001-10-19 21:39:31 +00001123
Brian Gaeke4efe3422003-09-21 01:23:46 +00001124 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
1125 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
Ruchira Sasanka174bded2001-10-28 18:12:02 +00001126
Chris Lattner7e708292002-06-25 16:13:24 +00001127 for ( ; HMI != HMIEnd ; ++HMI) {
Chris Lattner37730942002-02-05 03:52:29 +00001128 if (HMI->first && HMI->second) {
Vikram S. Adve3bf08922003-07-10 19:42:55 +00001129 LiveRange *L = HMI->second; // get the LiveRange
1130 if (L->isMarkedForSpill()) { // NOTE: allocating size of long Type **
Brian Gaeke4efe3422003-09-21 01:23:46 +00001131 int stackOffset = MF->getInfo()->allocateSpilledValue(Type::LongTy);
Vikram S. Adve39c94e12002-09-14 23:05:33 +00001132 L->setSpillOffFromFP(stackOffset);
1133 if (DEBUG_RA)
Chris Lattnerc083dcc2003-09-01 20:05:47 +00001134 std::cerr << " LR# " << L->getUserIGNode()->getIndex()
Vikram S. Adve39c94e12002-09-14 23:05:33 +00001135 << ": stack-offset = " << stackOffset << "\n";
1136 }
Chris Lattner37730942002-02-05 03:52:29 +00001137 }
1138 } // for all LR's in hash map
Ruchira Sasanka174bded2001-10-28 18:12:02 +00001139}
Ruchira Sasanka0e62aa62001-10-19 21:39:31 +00001140
Brian Gaeke874f4232003-09-21 02:50:21 +00001141
Brian Gaeke21390412003-11-10 00:05:26 +00001142void PhyRegAlloc::saveStateForValue (std::vector<AllocInfo> &state,
1143 const Value *V, unsigned Insn, int Opnd) {
1144 LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap ()->find (V);
1145 LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
1146 AllocInfo::AllocStateTy AllocState = AllocInfo::NotAllocated;
1147 int Placement = -1;
1148 if ((HMI != HMIEnd) && HMI->second) {
1149 LiveRange *L = HMI->second;
1150 assert ((L->hasColor () || L->isMarkedForSpill ())
1151 && "Live range exists but not colored or spilled");
1152 if (L->hasColor ()) {
1153 AllocState = AllocInfo::Allocated;
1154 Placement = MRI.getUnifiedRegNum (L->getRegClassID (),
1155 L->getColor ());
1156 } else if (L->isMarkedForSpill ()) {
1157 AllocState = AllocInfo::Spilled;
1158 assert (L->hasSpillOffset ()
1159 && "Live range marked for spill but has no spill offset");
1160 Placement = L->getSpillOffFromFP ();
1161 }
1162 }
1163 state.push_back (AllocInfo (Insn, Opnd, AllocState, Placement));
1164}
1165
1166
Brian Gaekeaf843702003-10-22 20:22:53 +00001167/// Save the global register allocation decisions made by the register
1168/// allocator so that they can be accessed later (sort of like "poor man's
1169/// debug info").
1170///
1171void PhyRegAlloc::saveState () {
Brian Gaeke537132b2003-10-23 20:32:55 +00001172 std::vector<AllocInfo> &state = FnAllocState[Fn];
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001173 unsigned Insn = 0;
Brian Gaeke3ceac852003-10-30 21:21:33 +00001174 for (const_inst_iterator II=inst_begin (Fn), IE=inst_end (Fn); II!=IE; ++II){
Brian Gaeke21390412003-11-10 00:05:26 +00001175 saveStateForValue (state, (*II), Insn, -1);
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001176 for (unsigned i = 0; i < (*II)->getNumOperands (); ++i) {
1177 const Value *V = (*II)->getOperand (i);
Brian Gaeke21390412003-11-10 00:05:26 +00001178 // Don't worry about it unless it's something whose reg. we'll need.
1179 if (!isa<Argument> (V) && !isa<Instruction> (V))
1180 continue;
1181 saveStateForValue (state, V, Insn, i);
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001182 }
Brian Gaeke3ceac852003-10-30 21:21:33 +00001183 ++Insn;
1184 }
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001185}
1186
Brian Gaeke537132b2003-10-23 20:32:55 +00001187
Brian Gaekeaf843702003-10-22 20:22:53 +00001188/// Check the saved state filled in by saveState(), and abort if it looks
Brian Gaeke55766e12003-11-04 22:42:41 +00001189/// wrong. Only used when debugging. FIXME: Currently it just prints out
1190/// the state, which isn't quite as useful.
Brian Gaekeaf843702003-10-22 20:22:53 +00001191///
1192void PhyRegAlloc::verifySavedState () {
Brian Gaeke3ceac852003-10-30 21:21:33 +00001193 std::vector<AllocInfo> &state = FnAllocState[Fn];
1194 unsigned Insn = 0;
1195 for (const_inst_iterator II=inst_begin (Fn), IE=inst_end (Fn); II!=IE; ++II) {
1196 const Instruction *I = *II;
1197 MachineCodeForInstruction &Instrs = MachineCodeForInstruction::get (I);
1198 std::cerr << "Instruction:\n" << " " << *I << "\n"
1199 << "MachineCodeForInstruction:\n";
1200 for (unsigned i = 0, n = Instrs.size (); i != n; ++i)
1201 std::cerr << " " << *Instrs[i] << "\n";
1202 std::cerr << "FnAllocState:\n";
1203 for (unsigned i = 0; i < state.size (); ++i) {
1204 AllocInfo &S = state[i];
1205 if (Insn == S.Instruction) {
1206 std::cerr << " (Instruction " << S.Instruction
1207 << ", Operand " << S.Operand
1208 << ", AllocState " << S.allocStateToString ()
1209 << ", Placement " << S.Placement << ")\n";
1210 }
1211 }
1212 std::cerr << "----------\n";
1213 ++Insn;
1214 }
Brian Gaekeaf843702003-10-22 20:22:53 +00001215}
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001216
Brian Gaekecce4e7a2003-11-04 18:25:56 +00001217
Brian Gaeke537132b2003-10-23 20:32:55 +00001218/// Finish the job of saveState(), by collapsing FnAllocState into an LLVM
1219/// Constant and stuffing it inside the Module. (NOTE: Soon, there will be
1220/// other, better ways of storing the saved state; this one is cumbersome and
Brian Gaeke21390412003-11-10 00:05:26 +00001221/// does not work well with the JIT.)
Brian Gaeke537132b2003-10-23 20:32:55 +00001222///
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001223bool PhyRegAlloc::doFinalization (Module &M) {
1224 if (!SaveRegAllocState)
1225 return false; // Nothing to do here, unless we're saving state.
1226
Brian Gaekecce4e7a2003-11-04 18:25:56 +00001227 // If saving state into the module, just copy new elements to the
1228 // correct global.
Brian Gaeke8fc49342003-10-24 21:21:58 +00001229 if (!SaveStateToModule) {
1230 ExportedFnAllocState = FnAllocState;
Brian Gaekecce4e7a2003-11-04 18:25:56 +00001231 // FIXME: should ONLY copy new elements in FnAllocState
Brian Gaeke8fc49342003-10-24 21:21:58 +00001232 return false;
1233 }
1234
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001235 // Convert FnAllocState to a single Constant array and add it
1236 // to the Module.
1237 ArrayType *AT = ArrayType::get (AllocInfo::getConstantType (), 0);
1238 std::vector<const Type *> TV;
1239 TV.push_back (Type::UIntTy);
1240 TV.push_back (AT);
1241 PointerType *PT = PointerType::get (StructType::get (TV));
1242
1243 std::vector<Constant *> allstate;
1244 for (Module::iterator I = M.begin (), E = M.end (); I != E; ++I) {
1245 Function *F = I;
Brian Gaeke55766e12003-11-04 22:42:41 +00001246 if (F->isExternal ()) continue;
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001247 if (FnAllocState.find (F) == FnAllocState.end ()) {
1248 allstate.push_back (ConstantPointerNull::get (PT));
1249 } else {
Brian Gaeke537132b2003-10-23 20:32:55 +00001250 std::vector<AllocInfo> &state = FnAllocState[F];
Brian Gaeke60a3c552003-10-22 20:44:23 +00001251
1252 // Convert state into an LLVM ConstantArray, and put it in a
1253 // ConstantStruct (named S) along with its size.
Brian Gaeke537132b2003-10-23 20:32:55 +00001254 std::vector<Constant *> stateConstants;
1255 for (unsigned i = 0, s = state.size (); i != s; ++i)
1256 stateConstants.push_back (state[i].toConstant ());
1257 unsigned Size = stateConstants.size ();
Brian Gaeke60a3c552003-10-22 20:44:23 +00001258 ArrayType *AT = ArrayType::get (AllocInfo::getConstantType (), Size);
1259 std::vector<const Type *> TV;
1260 TV.push_back (Type::UIntTy);
1261 TV.push_back (AT);
1262 StructType *ST = StructType::get (TV);
1263 std::vector<Constant *> CV;
1264 CV.push_back (ConstantUInt::get (Type::UIntTy, Size));
Brian Gaeke537132b2003-10-23 20:32:55 +00001265 CV.push_back (ConstantArray::get (AT, stateConstants));
Brian Gaeke60a3c552003-10-22 20:44:23 +00001266 Constant *S = ConstantStruct::get (ST, CV);
1267
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001268 GlobalVariable *GV =
Brian Gaeke60a3c552003-10-22 20:44:23 +00001269 new GlobalVariable (ST, true,
1270 GlobalValue::InternalLinkage, S,
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001271 F->getName () + ".regAllocState", &M);
Brian Gaeke60a3c552003-10-22 20:44:23 +00001272
Brian Gaeke21390412003-11-10 00:05:26 +00001273 // Have: { uint, [Size x { uint, int, uint, int }] } *
1274 // Cast it to: { uint, [0 x { uint, int, uint, int }] } *
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001275 Constant *CE = ConstantExpr::getCast (ConstantPointerRef::get (GV), PT);
1276 allstate.push_back (CE);
1277 }
1278 }
1279
1280 unsigned Size = allstate.size ();
1281 // Final structure type is:
Brian Gaeke21390412003-11-10 00:05:26 +00001282 // { uint, [Size x { uint, [0 x { uint, int, uint, int }] } *] }
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001283 std::vector<const Type *> TV2;
1284 TV2.push_back (Type::UIntTy);
1285 ArrayType *AT2 = ArrayType::get (PT, Size);
1286 TV2.push_back (AT2);
1287 StructType *ST2 = StructType::get (TV2);
1288 std::vector<Constant *> CV2;
1289 CV2.push_back (ConstantUInt::get (Type::UIntTy, Size));
1290 CV2.push_back (ConstantArray::get (AT2, allstate));
Brian Gaekee9414ca2003-11-10 07:12:01 +00001291 new GlobalVariable (ST2, true, GlobalValue::ExternalLinkage,
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001292 ConstantStruct::get (ST2, CV2), "_llvm_regAllocState",
1293 &M);
1294 return false; // No error.
1295}
1296
1297
Brian Gaekeaf843702003-10-22 20:22:53 +00001298/// Allocate registers for the machine code previously generated for F using
1299/// the graph-coloring algorithm.
1300///
Brian Gaeke4efe3422003-09-21 01:23:46 +00001301bool PhyRegAlloc::runOnFunction (Function &F) {
1302 if (DEBUG_RA)
1303 std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
1304
1305 Fn = &F;
1306 MF = &MachineFunction::get (Fn);
1307 LVI = &getAnalysis<FunctionLiveVarInfo> ();
1308 LRI = new LiveRangeInfo (Fn, TM, RegClassList);
1309 LoopDepthCalc = &getAnalysis<LoopInfo> ();
1310
1311 // Create each RegClass for the target machine and add it to the
1312 // RegClassList. This must be done before calling constructLiveRanges().
1313 for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
1314 RegClassList.push_back (new RegClass (Fn, &TM.getRegInfo (),
1315 MRI.getMachineRegClass (rc)));
1316
1317 LRI->constructLiveRanges(); // create LR info
Vikram S. Adve39c94e12002-09-14 23:05:33 +00001318 if (DEBUG_RA >= RA_DEBUG_LiveRanges)
Brian Gaeke4efe3422003-09-21 01:23:46 +00001319 LRI->printLiveRanges();
Ruchira Sasankaa5ab9642001-09-30 23:11:59 +00001320
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +00001321 createIGNodeListsAndIGs(); // create IGNode list and IGs
1322
1323 buildInterferenceGraphs(); // build IGs in all reg classes
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +00001324
Vikram S. Adve39c94e12002-09-14 23:05:33 +00001325 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +00001326 // print all LRs in all reg classes
Chris Lattner7e708292002-06-25 16:13:24 +00001327 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1328 RegClassList[rc]->printIGNodeList();
Ruchira Sasankaa5ab9642001-09-30 23:11:59 +00001329
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +00001330 // print IGs in all register classes
Chris Lattner7e708292002-06-25 16:13:24 +00001331 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1332 RegClassList[rc]->printIG();
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +00001333 }
Ruchira Sasanka4f3eb222002-01-07 19:19:18 +00001334
Brian Gaeke4efe3422003-09-21 01:23:46 +00001335 LRI->coalesceLRs(); // coalesce all live ranges
Ruchira Sasankaef1b0cb2001-11-03 17:13:27 +00001336
Vikram S. Adve39c94e12002-09-14 23:05:33 +00001337 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +00001338 // print all LRs in all reg classes
Chris Lattnerf726e772002-10-28 19:22:04 +00001339 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1340 RegClassList[rc]->printIGNodeList();
Ruchira Sasankaa5ab9642001-09-30 23:11:59 +00001341
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +00001342 // print IGs in all register classes
Chris Lattnerf726e772002-10-28 19:22:04 +00001343 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1344 RegClassList[rc]->printIG();
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +00001345 }
1346
Ruchira Sasanka0e62aa62001-10-19 21:39:31 +00001347 // mark un-usable suggested color before graph coloring algorithm.
1348 // When this is done, the graph coloring algo will not reserve
1349 // suggested color unnecessarily - they can be used by another LR
1350 markUnusableSugColors();
1351
1352 // color all register classes using the graph coloring algo
Chris Lattner7e708292002-06-25 16:13:24 +00001353 for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
Chris Lattnerf726e772002-10-28 19:22:04 +00001354 RegClassList[rc]->colorAllRegs();
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +00001355
Misha Brukman37f92e22003-09-11 22:34:13 +00001356 // After graph coloring, if some LRs did not receive a color (i.e, spilled)
1357 // a position for such spilled LRs
Ruchira Sasanka174bded2001-10-28 18:12:02 +00001358 allocateStackSpace4SpilledLRs();
Ruchira Sasankaa5ab9642001-09-30 23:11:59 +00001359
Vikram S. Adved0d06ad2003-05-31 07:32:01 +00001360 // Reset the temp. area on the stack before use by the first instruction.
1361 // This will also happen after updating each instruction.
Brian Gaeke4efe3422003-09-21 01:23:46 +00001362 MF->getInfo()->popAllTempValues();
Ruchira Sasankaf90870f2001-11-15 22:02:06 +00001363
Ruchira Sasanka4f3eb222002-01-07 19:19:18 +00001364 // color incoming args - if the correct color was not received
1365 // insert code to copy to the correct register
Ruchira Sasankaa5ab9642001-09-30 23:11:59 +00001366 colorIncomingArgs();
Ruchira Sasankaa5ab9642001-09-30 23:11:59 +00001367
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001368 // Save register allocation state for this function in a Constant.
1369 if (SaveRegAllocState)
1370 saveState();
Brian Gaekeaf843702003-10-22 20:22:53 +00001371 if (DEBUG_RA) { // Check our work.
1372 verifySavedState ();
1373 }
Brian Gaeke6a256cc2003-09-24 18:08:54 +00001374
Brian Gaeke60a3c552003-10-22 20:44:23 +00001375 // Now update the machine code with register names and add any additional
1376 // code inserted by the register allocator to the instruction stream.
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +00001377 updateMachineCode();
Ruchira Sasanka4f3eb222002-01-07 19:19:18 +00001378
Chris Lattner045e7c82001-09-19 16:26:23 +00001379 if (DEBUG_RA) {
Chris Lattnerc083dcc2003-09-01 20:05:47 +00001380 std::cerr << "\n**** Machine Code After Register Allocation:\n\n";
Brian Gaeke4efe3422003-09-21 01:23:46 +00001381 MF->dump();
Chris Lattner045e7c82001-09-19 16:26:23 +00001382 }
Brian Gaeke4efe3422003-09-21 01:23:46 +00001383
1384 // Tear down temporary data structures
1385 for (unsigned rc = 0; rc < NumOfRegClasses; ++rc)
1386 delete RegClassList[rc];
1387 RegClassList.clear ();
1388 AddedInstrMap.clear ();
1389 OperandsColoredMap.clear ();
1390 ScratchRegsUsed.clear ();
1391 AddedInstrAtEntry.clear ();
1392 delete LRI;
Ruchira Sasanka6b0a8b52001-09-15 21:11:11 +00001393
Brian Gaeke4efe3422003-09-21 01:23:46 +00001394 if (DEBUG_RA) std::cerr << "\nRegister allocation complete!\n";
1395 return false; // Function was not modified
1396}
Brian Gaeked0fde302003-11-11 22:41:34 +00001397
1398} // End llvm namespace