Chris Lattner | ed5171e | 2002-02-03 07:52:04 +0000 | [diff] [blame] | 1 | //===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===// |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | ed5171e | 2002-02-03 07:52:04 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file contains implementation of Sparc specific helper methods |
| 11 | // used for register allocation. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 15 | #include "SparcInternals.h" |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 16 | #include "SparcRegClassInfo.h" |
Misha Brukman | fce1143 | 2002-10-28 00:28:31 +0000 | [diff] [blame] | 17 | #include "llvm/CodeGen/MachineFunction.h" |
Chris Lattner | 1b849be | 2002-12-28 20:21:29 +0000 | [diff] [blame] | 18 | #include "llvm/CodeGen/MachineFunctionInfo.h" |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 19 | #include "llvm/CodeGen/InstrSelection.h" |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Anand Shukla | 55afc33 | 2003-06-01 02:48:23 +0000 | [diff] [blame] | 21 | #include "llvm/CodeGen/MachineCodeForInstruction.h" |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/MachineInstrAnnot.h" |
Chris Lattner | 893f954 | 2003-09-01 20:12:17 +0000 | [diff] [blame] | 23 | #include "../../CodeGen/RegAlloc/LiveRangeInfo.h" // FIXME!! |
Chris Lattner | 84681f1 | 2003-09-01 20:17:13 +0000 | [diff] [blame] | 24 | #include "../../CodeGen/RegAlloc/LiveRange.h" // FIXME!! |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 25 | #include "llvm/iTerminators.h" |
| 26 | #include "llvm/iOther.h" |
Chris Lattner | 0ac5429 | 2002-04-09 19:08:28 +0000 | [diff] [blame] | 27 | #include "llvm/Function.h" |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 28 | #include "llvm/DerivedTypes.h" |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 29 | |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame^] | 30 | namespace llvm { |
| 31 | |
Chris Lattner | 92ba2aa | 2003-01-14 23:05:08 +0000 | [diff] [blame] | 32 | enum { |
| 33 | BadRegClass = ~0 |
| 34 | }; |
| 35 | |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 36 | UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt) |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 37 | : TargetRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32) |
| 38 | { |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 39 | MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID)); |
| 40 | MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID)); |
| 41 | MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID)); |
| 42 | MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID)); |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 43 | MachineRegClassArr.push_back(new SparcSpecialRegClass(SpecialRegClassID)); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 44 | |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 45 | assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 && |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 46 | "32 Float regs are used for float arg passing"); |
| 47 | } |
| 48 | |
| 49 | |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 50 | // getZeroRegNum - returns the register that contains always zero. |
| 51 | // this is the unified register number |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 52 | // |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 53 | int UltraSparcRegInfo::getZeroRegNum() const { |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 54 | return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, |
| 55 | SparcIntRegClass::g0); |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 56 | } |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 57 | |
| 58 | // getCallAddressReg - returns the reg used for pushing the address when a |
| 59 | // method is called. This can be used for other purposes between calls |
| 60 | // |
| 61 | unsigned UltraSparcRegInfo::getCallAddressReg() const { |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 62 | return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, |
| 63 | SparcIntRegClass::o7); |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 64 | } |
| 65 | |
| 66 | // Returns the register containing the return address. |
| 67 | // It should be made sure that this register contains the return |
| 68 | // value when a return instruction is reached. |
| 69 | // |
| 70 | unsigned UltraSparcRegInfo::getReturnAddressReg() const { |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 71 | return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, |
| 72 | SparcIntRegClass::i7); |
| 73 | } |
| 74 | |
| 75 | // Register get name implementations... |
| 76 | |
| 77 | // Int register names in same order as enum in class SparcIntRegClass |
| 78 | static const char * const IntRegNames[] = { |
| 79 | "o0", "o1", "o2", "o3", "o4", "o5", "o7", |
| 80 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
| 81 | "i0", "i1", "i2", "i3", "i4", "i5", |
| 82 | "i6", "i7", |
| 83 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
| 84 | "o6" |
| 85 | }; |
| 86 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 87 | const char * const SparcIntRegClass::getRegName(unsigned reg) const { |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 88 | assert(reg < NumOfAllRegs); |
| 89 | return IntRegNames[reg]; |
| 90 | } |
| 91 | |
| 92 | static const char * const FloatRegNames[] = { |
| 93 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", |
| 94 | "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", |
| 95 | "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", |
| 96 | "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
| 97 | "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", |
| 98 | "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", |
| 99 | "f60", "f61", "f62", "f63" |
| 100 | }; |
| 101 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 102 | const char * const SparcFloatRegClass::getRegName(unsigned reg) const { |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 103 | assert (reg < NumOfAllRegs); |
| 104 | return FloatRegNames[reg]; |
| 105 | } |
| 106 | |
| 107 | |
| 108 | static const char * const IntCCRegNames[] = { |
Vikram S. Adve | 786833a | 2003-07-06 20:13:59 +0000 | [diff] [blame] | 109 | "xcc", "icc", "ccr" |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 110 | }; |
| 111 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 112 | const char * const SparcIntCCRegClass::getRegName(unsigned reg) const { |
Vikram S. Adve | 786833a | 2003-07-06 20:13:59 +0000 | [diff] [blame] | 113 | assert(reg < 3); |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 114 | return IntCCRegNames[reg]; |
| 115 | } |
| 116 | |
| 117 | static const char * const FloatCCRegNames[] = { |
| 118 | "fcc0", "fcc1", "fcc2", "fcc3" |
| 119 | }; |
| 120 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 121 | const char * const SparcFloatCCRegClass::getRegName(unsigned reg) const { |
| 122 | assert (reg < 5); |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 123 | return FloatCCRegNames[reg]; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 124 | } |
| 125 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 126 | static const char * const SpecialRegNames[] = { |
| 127 | "fsr" |
| 128 | }; |
| 129 | |
| 130 | const char * const SparcSpecialRegClass::getRegName(unsigned reg) const { |
| 131 | assert (reg < 1); |
| 132 | return SpecialRegNames[reg]; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 133 | } |
| 134 | |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 135 | // Get unified reg number for frame pointer |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 136 | unsigned UltraSparcRegInfo::getFramePointer() const { |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 137 | return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, |
| 138 | SparcIntRegClass::i6); |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 139 | } |
| 140 | |
Vikram S. Adve | f1c15ee | 2002-03-18 03:12:16 +0000 | [diff] [blame] | 141 | // Get unified reg number for stack pointer |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 142 | unsigned UltraSparcRegInfo::getStackPointer() const { |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 143 | return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, |
| 144 | SparcIntRegClass::o6); |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 148 | //--------------------------------------------------------------------------- |
| 149 | // Finds whether a call is an indirect call |
| 150 | //--------------------------------------------------------------------------- |
| 151 | |
| 152 | inline bool |
| 153 | isVarArgsFunction(const Type *funcType) { |
| 154 | return cast<FunctionType>(cast<PointerType>(funcType) |
| 155 | ->getElementType())->isVarArg(); |
| 156 | } |
| 157 | |
| 158 | inline bool |
| 159 | isVarArgsCall(const MachineInstr *CallMI) { |
| 160 | Value* callee = CallMI->getOperand(0).getVRegValue(); |
| 161 | // const Type* funcType = isa<Function>(callee)? callee->getType() |
| 162 | // : cast<PointerType>(callee->getType())->getElementType(); |
| 163 | const Type* funcType = callee->getType(); |
| 164 | return isVarArgsFunction(funcType); |
| 165 | } |
| 166 | |
| 167 | |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 168 | // Get the register number for the specified argument #argNo, |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 169 | // |
| 170 | // Return value: |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 171 | // getInvalidRegNum(), if there is no int register available for the arg. |
| 172 | // regNum, otherwise (this is NOT the unified reg. num). |
| 173 | // regClassId is set to the register class ID. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 174 | // |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 175 | int |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 176 | UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 177 | unsigned argNo, unsigned& regClassId) const |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 178 | { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 179 | regClassId = IntRegClassID; |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 180 | if (argNo >= NumOfIntArgRegs) |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 181 | return getInvalidRegNum(); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 182 | else |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 183 | return argNo + (inCallee? SparcIntRegClass::i0 : SparcIntRegClass::o0); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 184 | } |
| 185 | |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 186 | // Get the register number for the specified FP argument #argNo, |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 187 | // Use INT regs for FP args if this is a varargs call. |
| 188 | // |
| 189 | // Return value: |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 190 | // getInvalidRegNum(), if there is no int register available for the arg. |
| 191 | // regNum, otherwise (this is NOT the unified reg. num). |
| 192 | // regClassId is set to the register class ID. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 193 | // |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 194 | int |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 195 | UltraSparcRegInfo::regNumForFPArg(unsigned regType, |
| 196 | bool inCallee, bool isVarArgsCall, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 197 | unsigned argNo, unsigned& regClassId) const |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 198 | { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 199 | if (isVarArgsCall) |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 200 | return regNumForIntArg(inCallee, isVarArgsCall, argNo, regClassId); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 201 | else |
| 202 | { |
| 203 | regClassId = FloatRegClassID; |
| 204 | if (regType == FPSingleRegType) |
| 205 | return (argNo*2+1 >= NumOfFloatArgRegs)? |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 206 | getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2 + 1); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 207 | else if (regType == FPDoubleRegType) |
| 208 | return (argNo*2 >= NumOfFloatArgRegs)? |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 209 | getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 210 | else |
| 211 | assert(0 && "Illegal FP register type"); |
Chris Lattner | b82d97e | 2002-07-25 06:08:32 +0000 | [diff] [blame] | 212 | return 0; |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 213 | } |
Vikram S. Adve | a44c6c0 | 2002-03-31 19:04:50 +0000 | [diff] [blame] | 214 | } |
| 215 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 216 | |
| 217 | //--------------------------------------------------------------------------- |
| 218 | // Finds the return address of a call sparc specific call instruction |
| 219 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 220 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 221 | // The following 4 methods are used to find the RegType (SparcInternals.h) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 222 | // of a LiveRange, a Value, and for a given register unified reg number. |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 223 | // |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 224 | int UltraSparcRegInfo::getRegTypeForClassAndType(unsigned regClassID, |
| 225 | const Type* type) const |
| 226 | { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 227 | switch (regClassID) { |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 228 | case IntRegClassID: return IntRegType; |
| 229 | case FloatRegClassID: |
| 230 | if (type == Type::FloatTy) return FPSingleRegType; |
| 231 | else if (type == Type::DoubleTy) return FPDoubleRegType; |
| 232 | assert(0 && "Unknown type in FloatRegClass"); return 0; |
| 233 | case IntCCRegClassID: return IntCCRegType; |
| 234 | case FloatCCRegClassID: return FloatCCRegType; |
| 235 | case SpecialRegClassID: return SpecialRegType; |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 236 | default: assert( 0 && "Unknown reg class ID"); return 0; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 237 | } |
| 238 | } |
| 239 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 240 | int UltraSparcRegInfo::getRegTypeForDataType(const Type* type) const |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 241 | { |
| 242 | return getRegTypeForClassAndType(getRegClassIDOfType(type), type); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 243 | } |
| 244 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 245 | int UltraSparcRegInfo::getRegTypeForLR(const LiveRange *LR) const |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 246 | { |
| 247 | return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType()); |
| 248 | } |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 249 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 250 | int UltraSparcRegInfo::getRegType(int unifiedRegNum) const |
| 251 | { |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 252 | if (unifiedRegNum < 32) |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 253 | return IntRegType; |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 254 | else if (unifiedRegNum < (32 + 32)) |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 255 | return FPSingleRegType; |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 256 | else if (unifiedRegNum < (64 + 32)) |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 257 | return FPDoubleRegType; |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 258 | else if (unifiedRegNum < (64+32+4)) |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 259 | return FloatCCRegType; |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 260 | else if (unifiedRegNum < (64+32+4+2)) |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 261 | return IntCCRegType; |
| 262 | else |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 263 | assert(0 && "Invalid unified register number in getRegType"); |
Chris Lattner | 49b8a9c | 2002-02-24 23:02:40 +0000 | [diff] [blame] | 264 | return 0; |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 265 | } |
| 266 | |
| 267 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 268 | // To find the register class used for a specified Type |
| 269 | // |
| 270 | unsigned UltraSparcRegInfo::getRegClassIDOfType(const Type *type, |
Chris Lattner | b82d97e | 2002-07-25 06:08:32 +0000 | [diff] [blame] | 271 | bool isCCReg) const { |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 272 | Type::PrimitiveID ty = type->getPrimitiveID(); |
| 273 | unsigned res; |
| 274 | |
| 275 | // FIXME: Comparing types like this isn't very safe... |
| 276 | if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) || |
| 277 | (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) ) |
| 278 | res = IntRegClassID; // sparc int reg (ty=0: void) |
| 279 | else if (ty <= Type::DoubleTyID) |
| 280 | res = FloatRegClassID; // sparc float reg class |
| 281 | else { |
| 282 | //std::cerr << "TypeID: " << ty << "\n"; |
| 283 | assert(0 && "Cannot resolve register class for type"); |
| 284 | return 0; |
| 285 | } |
| 286 | |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 287 | if (isCCReg) |
| 288 | return res + 2; // corresponding condition code register |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 289 | else |
| 290 | return res; |
| 291 | } |
| 292 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 293 | unsigned UltraSparcRegInfo::getRegClassIDOfRegType(int regType) const { |
| 294 | switch(regType) { |
| 295 | case IntRegType: return IntRegClassID; |
| 296 | case FPSingleRegType: |
| 297 | case FPDoubleRegType: return FloatRegClassID; |
| 298 | case IntCCRegType: return IntCCRegClassID; |
| 299 | case FloatCCRegType: return FloatCCRegClassID; |
| 300 | default: |
| 301 | assert(0 && "Invalid register type in getRegClassIDOfRegType"); |
| 302 | return 0; |
| 303 | } |
| 304 | } |
| 305 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 306 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 307 | // Suggests a register for the ret address in the RET machine instruction. |
| 308 | // We always suggest %i7 by convention. |
| 309 | //--------------------------------------------------------------------------- |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 310 | void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI, |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 311 | LiveRangeInfo& LRI) const { |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 312 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 313 | assert(target.getInstrInfo().isReturn(RetMI->getOpCode())); |
Vikram S. Adve | 53fec86 | 2001-10-22 13:41:12 +0000 | [diff] [blame] | 314 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 315 | // return address is always mapped to i7 so set it immediately |
| 316 | RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID, |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 317 | SparcIntRegClass::i7)); |
Vikram S. Adve | 53fec86 | 2001-10-22 13:41:12 +0000 | [diff] [blame] | 318 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 319 | // Possible Optimization: |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 320 | // Instead of setting the color, we can suggest one. In that case, |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 321 | // we have to test later whether it received the suggested color. |
| 322 | // In that case, a LR has to be created at the start of method. |
| 323 | // It has to be done as follows (remove the setRegVal above): |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 324 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 325 | // MachineOperand & MO = RetMI->getOperand(0); |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 326 | // const Value *RetAddrVal = MO.getVRegValue(); |
| 327 | // assert( RetAddrVal && "LR for ret address must be created at start"); |
| 328 | // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal); |
| 329 | // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 330 | // SparcIntRegOrdr::i7) ); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | |
| 334 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 335 | // Suggests a register for the ret address in the JMPL/CALL machine instr. |
| 336 | // Sparc ABI dictates that %o7 be used for this purpose. |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 337 | //--------------------------------------------------------------------------- |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 338 | void |
| 339 | UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI, |
| 340 | LiveRangeInfo& LRI) const |
| 341 | { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 342 | CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); |
| 343 | const Value *RetAddrVal = argDesc->getReturnAddrReg(); |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 344 | assert(RetAddrVal && "INTERNAL ERROR: Return address value is required"); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 345 | |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 346 | // A LR must already exist for the return address. |
| 347 | LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal); |
| 348 | assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!"); |
| 349 | |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 350 | unsigned RegClassID = RetAddrLR->getRegClassID(); |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 351 | RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcIntRegClass::o7)); |
| 352 | } |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 353 | |
| 354 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 355 | |
| 356 | //--------------------------------------------------------------------------- |
| 357 | // This method will suggest colors to incoming args to a method. |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 358 | // According to the Sparc ABI, the first 6 incoming args are in |
| 359 | // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float). |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 360 | // If the arg is passed on stack due to the lack of regs, NOTHING will be |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 361 | // done - it will be colored (or spilled) as a normal live range. |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 362 | //--------------------------------------------------------------------------- |
Chris Lattner | b7653df | 2002-04-08 22:03:57 +0000 | [diff] [blame] | 363 | void UltraSparcRegInfo::suggestRegs4MethodArgs(const Function *Meth, |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 364 | LiveRangeInfo& LRI) const |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 365 | { |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 366 | // Check if this is a varArgs function. needed for choosing regs. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 367 | bool isVarArgs = isVarArgsFunction(Meth->getType()); |
| 368 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 369 | // Count the arguments, *ignoring* whether they are int or FP args. |
| 370 | // Use this common arg numbering to pick the right int or fp register. |
| 371 | unsigned argNo=0; |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 372 | for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend(); |
| 373 | I != E; ++I, ++argNo) { |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 374 | LiveRange *LR = LRI.getLiveRangeForValue(I); |
| 375 | assert(LR && "No live range found for method arg"); |
| 376 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 377 | unsigned regType = getRegTypeForLR(LR); |
| 378 | unsigned regClassIDOfArgReg = BadRegClass; // for chosen reg (unused) |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 379 | |
| 380 | int regNum = (regType == IntRegType) |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 381 | ? regNumForIntArg(/*inCallee*/ true, isVarArgs, argNo, regClassIDOfArgReg) |
| 382 | : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, argNo, |
| 383 | regClassIDOfArgReg); |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 384 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 385 | if (regNum != getInvalidRegNum()) |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 386 | LR->setSuggestedColor(regNum); |
| 387 | } |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 388 | } |
| 389 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 390 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 391 | //--------------------------------------------------------------------------- |
| 392 | // This method is called after graph coloring to move incoming args to |
| 393 | // the correct hardware registers if they did not receive the correct |
| 394 | // (suggested) color through graph coloring. |
| 395 | //--------------------------------------------------------------------------- |
Chris Lattner | b7653df | 2002-04-08 22:03:57 +0000 | [diff] [blame] | 396 | void UltraSparcRegInfo::colorMethodArgs(const Function *Meth, |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 397 | LiveRangeInfo &LRI, |
| 398 | std::vector<MachineInstr*>& InstrnsBefore, |
| 399 | std::vector<MachineInstr*>& InstrnsAfter) const { |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 400 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 401 | // check if this is a varArgs function. needed for choosing regs. |
| 402 | bool isVarArgs = isVarArgsFunction(Meth->getType()); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 403 | MachineInstr *AdMI; |
| 404 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 405 | // for each argument |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 406 | // for each argument. count INT and FP arguments separately. |
| 407 | unsigned argNo=0, intArgNo=0, fpArgNo=0; |
| 408 | for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend(); |
| 409 | I != E; ++I, ++argNo) { |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 410 | // get the LR of arg |
Chris Lattner | 0b12b5f | 2002-06-25 16:13:21 +0000 | [diff] [blame] | 411 | LiveRange *LR = LRI.getLiveRangeForValue(I); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 412 | assert( LR && "No live range found for method arg"); |
| 413 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 414 | unsigned regType = getRegTypeForLR(LR); |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 415 | unsigned RegClassID = LR->getRegClassID(); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 416 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 417 | // Find whether this argument is coming in a register (if not, on stack) |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 418 | // Also find the correct register the argument must use (UniArgReg) |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 419 | // |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 420 | bool isArgInReg = false; |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 421 | unsigned UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with |
Chris Lattner | 92ba2aa | 2003-01-14 23:05:08 +0000 | [diff] [blame] | 422 | unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 423 | |
| 424 | int regNum = (regType == IntRegType) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 425 | ? regNumForIntArg(/*inCallee*/ true, isVarArgs, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 426 | argNo, regClassIDOfArgReg) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 427 | : regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 428 | argNo, regClassIDOfArgReg); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 429 | |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 430 | if(regNum != getInvalidRegNum()) { |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 431 | isArgInReg = true; |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 432 | UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 433 | } |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 434 | |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 435 | if( ! LR->isMarkedForSpill() ) { // if this arg received a register |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 436 | |
Ruchira Sasanka | c74a720 | 2001-10-24 15:56:58 +0000 | [diff] [blame] | 437 | unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() ); |
| 438 | |
| 439 | // if LR received the correct color, nothing to do |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 440 | // |
Ruchira Sasanka | c74a720 | 2001-10-24 15:56:58 +0000 | [diff] [blame] | 441 | if( UniLRReg == UniArgReg ) |
| 442 | continue; |
| 443 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 444 | // We are here because the LR did not receive the suggested |
| 445 | // but LR received another register. |
| 446 | // Now we have to copy the %i reg (or stack pos of arg) |
| 447 | // to the register the LR was colored with. |
Ruchira Sasanka | c74a720 | 2001-10-24 15:56:58 +0000 | [diff] [blame] | 448 | |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 449 | // if the arg is coming in UniArgReg register, it MUST go into |
Ruchira Sasanka | c74a720 | 2001-10-24 15:56:58 +0000 | [diff] [blame] | 450 | // the UniLRReg register |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 451 | // |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 452 | if( isArgInReg ) { |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 453 | if( regClassIDOfArgReg != RegClassID ) { |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 454 | assert(0 && "This could should work but it is not tested yet"); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 455 | |
| 456 | // It is a variable argument call: the float reg must go in a %o reg. |
| 457 | // We have to move an int reg to a float reg via memory. |
| 458 | // |
| 459 | assert(isVarArgs && |
| 460 | RegClassID == FloatRegClassID && |
| 461 | regClassIDOfArgReg == IntRegClassID && |
| 462 | "This should only be an Int register for an FP argument"); |
| 463 | |
Chris Lattner | 1b849be | 2002-12-28 20:21:29 +0000 | [diff] [blame] | 464 | int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue( |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 465 | getSpilledRegSize(regType)); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 466 | cpReg2MemMI(InstrnsBefore, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 467 | UniArgReg, getFramePointer(), TmpOff, IntRegType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 468 | |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 469 | cpMem2RegMI(InstrnsBefore, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 470 | getFramePointer(), TmpOff, UniLRReg, regType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 471 | } |
| 472 | else { |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 473 | cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 474 | } |
| 475 | } |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 476 | else { |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 477 | |
Misha Brukman | cf00c4a | 2003-10-10 17:57:28 +0000 | [diff] [blame] | 478 | // Now the arg is coming on stack. Since the LR received a register, |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 479 | // we just have to load the arg on stack into that register |
Ruchira Sasanka | d00982a | 2002-01-07 19:20:28 +0000 | [diff] [blame] | 480 | // |
Chris Lattner | 1b849be | 2002-12-28 20:21:29 +0000 | [diff] [blame] | 481 | const TargetFrameInfo& frameInfo = target.getFrameInfo(); |
Vikram S. Adve | 1c0fba6 | 2001-11-08 04:56:41 +0000 | [diff] [blame] | 482 | int offsetFromFP = |
Misha Brukman | fce1143 | 2002-10-28 00:28:31 +0000 | [diff] [blame] | 483 | frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 484 | argNo); |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 485 | |
| 486 | // float arguments on stack are right justified so adjust the offset! |
| 487 | // int arguments are also right justified but they are always loaded as |
| 488 | // a full double-word so the offset does not need to be adjusted. |
| 489 | if (regType == FPSingleRegType) { |
| 490 | unsigned argSize = target.getTargetData().getTypeSize(LR->getType()); |
| 491 | unsigned slotSize = frameInfo.getSizeOfEachArgOnStack(); |
| 492 | assert(argSize <= slotSize && "Insufficient slot size!"); |
| 493 | offsetFromFP += slotSize - argSize; |
| 494 | } |
| 495 | |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 496 | cpMem2RegMI(InstrnsBefore, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 497 | getFramePointer(), offsetFromFP, UniLRReg, regType); |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 498 | } |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 499 | |
| 500 | } // if LR received a color |
| 501 | |
| 502 | else { |
| 503 | |
| 504 | // Now, the LR did not receive a color. But it has a stack offset for |
| 505 | // spilling. |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 506 | // So, if the arg is coming in UniArgReg register, we can just move |
| 507 | // that on to the stack pos of LR |
| 508 | |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 509 | if( isArgInReg ) { |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 510 | |
| 511 | if( regClassIDOfArgReg != RegClassID ) { |
| 512 | assert(0 && |
| 513 | "FP arguments to a varargs function should be explicitly " |
| 514 | "copied to/from int registers by instruction selection!"); |
| 515 | |
| 516 | // It must be a float arg for a variable argument call, which |
| 517 | // must come in a %o reg. Move the int reg to the stack. |
| 518 | // |
| 519 | assert(isVarArgs && regClassIDOfArgReg == IntRegClassID && |
| 520 | "This should only be an Int register for an FP argument"); |
| 521 | |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 522 | cpReg2MemMI(InstrnsBefore, UniArgReg, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 523 | getFramePointer(), LR->getSpillOffFromFP(), IntRegType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 524 | } |
| 525 | else { |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 526 | cpReg2MemMI(InstrnsBefore, UniArgReg, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 527 | getFramePointer(), LR->getSpillOffFromFP(), regType); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 528 | } |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 529 | } |
| 530 | |
| 531 | else { |
| 532 | |
| 533 | // Now the arg is coming on stack. Since the LR did NOT |
Misha Brukman | cf00c4a | 2003-10-10 17:57:28 +0000 | [diff] [blame] | 534 | // received a register as well, it is allocated a stack position. We |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 535 | // can simply change the stack position of the LR. We can do this, |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 536 | // since this method is called before any other method that makes |
| 537 | // uses of the stack pos of the LR (e.g., updateMachineInstr) |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 538 | // |
Chris Lattner | 1b849be | 2002-12-28 20:21:29 +0000 | [diff] [blame] | 539 | const TargetFrameInfo& frameInfo = target.getFrameInfo(); |
Vikram S. Adve | 1c0fba6 | 2001-11-08 04:56:41 +0000 | [diff] [blame] | 540 | int offsetFromFP = |
Misha Brukman | fce1143 | 2002-10-28 00:28:31 +0000 | [diff] [blame] | 541 | frameInfo.getIncomingArgOffset(MachineFunction::get(Meth), |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 542 | argNo); |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 543 | |
| 544 | // FP arguments on stack are right justified so adjust offset! |
| 545 | // int arguments are also right justified but they are always loaded as |
| 546 | // a full double-word so the offset does not need to be adjusted. |
| 547 | if (regType == FPSingleRegType) { |
| 548 | unsigned argSize = target.getTargetData().getTypeSize(LR->getType()); |
| 549 | unsigned slotSize = frameInfo.getSizeOfEachArgOnStack(); |
| 550 | assert(argSize <= slotSize && "Insufficient slot size!"); |
| 551 | offsetFromFP += slotSize - argSize; |
| 552 | } |
Vikram S. Adve | 1c0fba6 | 2001-11-08 04:56:41 +0000 | [diff] [blame] | 553 | |
| 554 | LR->modifySpillOffFromFP( offsetFromFP ); |
Ruchira Sasanka | 20c82b1 | 2001-10-28 18:15:12 +0000 | [diff] [blame] | 555 | } |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 556 | |
| 557 | } |
| 558 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 559 | } // for each incoming argument |
| 560 | |
| 561 | } |
| 562 | |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 563 | |
| 564 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 565 | //--------------------------------------------------------------------------- |
| 566 | // This method is called before graph coloring to suggest colors to the |
| 567 | // outgoing call args and the return value of the call. |
| 568 | //--------------------------------------------------------------------------- |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 569 | void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 570 | LiveRangeInfo& LRI) const { |
Vikram S. Adve | c654c78 | 2002-10-13 00:05:30 +0000 | [diff] [blame] | 571 | assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) ); |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 572 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 573 | CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 574 | |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 575 | suggestReg4CallAddr(CallMI, LRI); |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 576 | |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 577 | // First color the return value of the call instruction, if any. |
| 578 | // The return value will be in %o0 if the value is an integer type, |
| 579 | // or in %f0 if the value is a float type. |
| 580 | // |
| 581 | if (const Value *RetVal = argDesc->getReturnValue()) { |
| 582 | LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal); |
| 583 | assert(RetValLR && "No LR for return Value of call!"); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 584 | |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 585 | unsigned RegClassID = RetValLR->getRegClassID(); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 586 | |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 587 | // now suggest a register depending on the register class of ret arg |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 588 | if( RegClassID == IntRegClassID ) |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 589 | RetValLR->setSuggestedColor(SparcIntRegClass::o0); |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 590 | else if (RegClassID == FloatRegClassID ) |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 591 | RetValLR->setSuggestedColor(SparcFloatRegClass::f0 ); |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 592 | else assert( 0 && "Unknown reg class for return value of call\n"); |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 593 | } |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 594 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 595 | // Now suggest colors for arguments (operands) of the call instruction. |
| 596 | // Colors are suggested only if the arg number is smaller than the |
| 597 | // the number of registers allocated for argument passing. |
Ruchira Sasanka | b3b6f53 | 2001-10-21 16:43:41 +0000 | [diff] [blame] | 598 | // Now, go thru call args - implicit operands of the call MI |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 599 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 600 | unsigned NumOfCallArgs = argDesc->getNumArgs(); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 601 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 602 | for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0; |
| 603 | i < NumOfCallArgs; ++i, ++argNo) { |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 604 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 605 | const Value *CallArg = argDesc->getArgInfo(i).getArgVal(); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 606 | |
| 607 | // get the LR of call operand (parameter) |
Ruchira Sasanka | cc3ccac | 2001-10-15 16:25:28 +0000 | [diff] [blame] | 608 | LiveRange *const LR = LRI.getLiveRangeForValue(CallArg); |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 609 | if (!LR) |
| 610 | continue; // no live ranges for constants and labels |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 611 | |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 612 | unsigned regType = getRegTypeForLR(LR); |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 613 | unsigned regClassIDOfArgReg = BadRegClass; // chosen reg class (unused) |
Vikram S. Adve | 8781765 | 2002-09-28 16:59:05 +0000 | [diff] [blame] | 614 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 615 | // Choose a register for this arg depending on whether it is |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 616 | // an INT or FP value. Here we ignore whether or not it is a |
| 617 | // varargs calls, because FP arguments will be explicitly copied |
| 618 | // to an integer Value and handled under (argCopy != NULL) below. |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 619 | int regNum = (regType == IntRegType) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 620 | ? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 621 | argNo, regClassIDOfArgReg) |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 622 | : regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false, |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 623 | argNo, regClassIDOfArgReg); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 624 | |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 625 | // If a register could be allocated, use it. |
| 626 | // If not, do NOTHING as this will be colored as a normal value. |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 627 | if(regNum != getInvalidRegNum()) |
Vikram S. Adve | 31f78c4 | 2002-04-25 04:42:21 +0000 | [diff] [blame] | 628 | LR->setSuggestedColor(regNum); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 629 | } // for all call arguments |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 630 | } |
| 631 | |
| 632 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 633 | //--------------------------------------------------------------------------- |
Anand Shukla | 55afc33 | 2003-06-01 02:48:23 +0000 | [diff] [blame] | 634 | // this method is called for an LLVM return instruction to identify which |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 635 | // values will be returned from this method and to suggest colors. |
| 636 | //--------------------------------------------------------------------------- |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 637 | void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI, |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 638 | LiveRangeInfo& LRI) const { |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 639 | |
Vikram S. Adve | c654c78 | 2002-10-13 00:05:30 +0000 | [diff] [blame] | 640 | assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) ); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 641 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 642 | suggestReg4RetAddr(RetMI, LRI); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 643 | |
Vikram S. Adve | d0d06ad | 2003-05-31 07:32:01 +0000 | [diff] [blame] | 644 | // To find the return value (if any), we can get the LLVM return instr. |
| 645 | // from the return address register, which is the first operand |
| 646 | Value* tmpI = RetMI->getOperand(0).getVRegValue(); |
| 647 | ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0)); |
| 648 | if (const Value *RetVal = retI->getReturnValue()) |
| 649 | if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal)) |
| 650 | LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID |
| 651 | ? (unsigned) SparcIntRegClass::i0 |
| 652 | : (unsigned) SparcFloatRegClass::f0); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 653 | } |
| 654 | |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 655 | //--------------------------------------------------------------------------- |
| 656 | // Check if a specified register type needs a scratch register to be |
| 657 | // copied to/from memory. If it does, the reg. type that must be used |
| 658 | // for scratch registers is returned in scratchRegType. |
| 659 | // |
| 660 | // Only the int CC register needs such a scratch register. |
| 661 | // The FP CC registers can (and must) be copied directly to/from memory. |
| 662 | //--------------------------------------------------------------------------- |
| 663 | |
| 664 | bool |
| 665 | UltraSparcRegInfo::regTypeNeedsScratchReg(int RegType, |
| 666 | int& scratchRegType) const |
| 667 | { |
| 668 | if (RegType == IntCCRegType) |
| 669 | { |
| 670 | scratchRegType = IntRegType; |
| 671 | return true; |
| 672 | } |
| 673 | return false; |
| 674 | } |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 675 | |
| 676 | //--------------------------------------------------------------------------- |
| 677 | // Copy from a register to register. Register number must be the unified |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 678 | // register number. |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 679 | //--------------------------------------------------------------------------- |
| 680 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 681 | void |
Misha Brukman | ee563cb | 2003-05-21 17:59:06 +0000 | [diff] [blame] | 682 | UltraSparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 683 | unsigned SrcReg, |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 684 | unsigned DestReg, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 685 | int RegType) const { |
Misha Brukman | d36e30e | 2003-06-06 09:52:23 +0000 | [diff] [blame] | 686 | assert( ((int)SrcReg != getInvalidRegNum()) && |
| 687 | ((int)DestReg != getInvalidRegNum()) && |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 688 | "Invalid Register"); |
| 689 | |
| 690 | MachineInstr * MI = NULL; |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 691 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 692 | switch( RegType ) { |
| 693 | |
Ruchira Sasanka | 735d6e3 | 2001-10-18 22:38:52 +0000 | [diff] [blame] | 694 | case IntCCRegType: |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 695 | if (getRegType(DestReg) == IntRegType) { |
| 696 | // copy intCC reg to int reg |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 697 | MI = (BuildMI(V9::RDCCR, 2) |
| 698 | .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID, |
| 699 | SparcIntCCRegClass::ccr)) |
| 700 | .addMReg(DestReg,MOTy::Def)); |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 701 | } else { |
| 702 | // copy int reg to intCC reg |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 703 | assert(getRegType(SrcReg) == IntRegType |
| 704 | && "Can only copy CC reg to/from integer reg"); |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 705 | MI = (BuildMI(V9::WRCCRr, 3) |
| 706 | .addMReg(SrcReg) |
| 707 | .addMReg(SparcIntRegClass::g0) |
| 708 | .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID, |
| 709 | SparcIntCCRegClass::ccr), MOTy::Def)); |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 710 | } |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 711 | break; |
| 712 | |
Ruchira Sasanka | 735d6e3 | 2001-10-18 22:38:52 +0000 | [diff] [blame] | 713 | case FloatCCRegType: |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 714 | assert(0 && "Cannot copy FPCC register to any other register"); |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 715 | break; |
| 716 | |
| 717 | case IntRegType: |
Misha Brukman | af6f38e | 2003-05-27 22:40:34 +0000 | [diff] [blame] | 718 | MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum()) |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 719 | .addMReg(DestReg, MOTy::Def); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 720 | break; |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 721 | |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 722 | case FPSingleRegType: |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 723 | MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 724 | break; |
| 725 | |
| 726 | case FPDoubleRegType: |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 727 | MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def); |
Ruchira Sasanka | 9144228 | 2001-09-30 23:16:47 +0000 | [diff] [blame] | 728 | break; |
| 729 | |
| 730 | default: |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 731 | assert(0 && "Unknown RegType"); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 732 | break; |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 733 | } |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 734 | |
| 735 | if (MI) |
| 736 | mvec.push_back(MI); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 737 | } |
Chris Lattner | 20b1ea0 | 2001-09-14 03:47:57 +0000 | [diff] [blame] | 738 | |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 739 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | 7dcd612 | 2001-10-24 22:05:34 +0000 | [diff] [blame] | 740 | // Copy from a register to memory (i.e., Store). Register number must |
| 741 | // be the unified register number |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 742 | //--------------------------------------------------------------------------- |
| 743 | |
| 744 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 745 | void |
Misha Brukman | ee563cb | 2003-05-21 17:59:06 +0000 | [diff] [blame] | 746 | UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec, |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 747 | unsigned SrcReg, |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 748 | unsigned PtrReg, |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 749 | int Offset, int RegType, |
Chris Lattner | b82d97e | 2002-07-25 06:08:32 +0000 | [diff] [blame] | 750 | int scratchReg) const { |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 751 | MachineInstr * MI = NULL; |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 752 | int OffReg = -1; |
| 753 | |
| 754 | // If the Offset will not fit in the signed-immediate field, find an |
| 755 | // unused register to hold the offset value. This takes advantage of |
| 756 | // the fact that all the opcodes used below have the same size immed. field. |
| 757 | // Use the register allocator, PRA, to find an unused reg. at this MI. |
| 758 | // |
| 759 | if (RegType != IntCCRegType) // does not use offset below |
| 760 | if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) { |
| 761 | #ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY |
| 762 | RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType)); |
| 763 | OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef); |
| 764 | #else |
Brian Gaeke | 641271d | 2003-11-08 18:12:24 +0000 | [diff] [blame] | 765 | // Default to using register g4 for holding large offsets |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 766 | OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, |
| 767 | SparcIntRegClass::g4); |
| 768 | #endif |
| 769 | assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg."); |
| 770 | mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg)); |
| 771 | } |
| 772 | |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 773 | switch (RegType) { |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 774 | case IntRegType: |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 775 | if (target.getInstrInfo().constantFitsInImmedField(V9::STXi, Offset)) |
| 776 | MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset); |
| 777 | else |
| 778 | MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 779 | break; |
| 780 | |
| 781 | case FPSingleRegType: |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 782 | if (target.getInstrInfo().constantFitsInImmedField(V9::STFi, Offset)) |
| 783 | MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset); |
| 784 | else |
| 785 | MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 786 | break; |
| 787 | |
| 788 | case FPDoubleRegType: |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 789 | if (target.getInstrInfo().constantFitsInImmedField(V9::STDFi, Offset)) |
| 790 | MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset); |
| 791 | else |
| 792 | MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 793 | break; |
| 794 | |
Ruchira Sasanka | 3839e6e | 2001-11-03 19:59:59 +0000 | [diff] [blame] | 795 | case IntCCRegType: |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 796 | assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory"); |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 797 | assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 798 | MI = (BuildMI(V9::RDCCR, 2) |
| 799 | .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID, |
| 800 | SparcIntCCRegClass::ccr)) |
Vikram S. Adve | 786833a | 2003-07-06 20:13:59 +0000 | [diff] [blame] | 801 | .addMReg(scratchReg, MOTy::Def)); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 802 | mvec.push_back(MI); |
| 803 | |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 804 | cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType); |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 805 | return; |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 806 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 807 | case FloatCCRegType: { |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 808 | unsigned fsrReg = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID, |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 809 | SparcSpecialRegClass::fsr); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 810 | if (target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset)) |
| 811 | MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset); |
| 812 | else |
| 813 | MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 814 | break; |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 815 | } |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 816 | default: |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 817 | assert(0 && "Unknown RegType in cpReg2MemMI"); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 818 | } |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 819 | mvec.push_back(MI); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 820 | } |
| 821 | |
| 822 | |
| 823 | //--------------------------------------------------------------------------- |
Ruchira Sasanka | 7dcd612 | 2001-10-24 22:05:34 +0000 | [diff] [blame] | 824 | // Copy from memory to a reg (i.e., Load) Register number must be the unified |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 825 | // register number |
| 826 | //--------------------------------------------------------------------------- |
| 827 | |
| 828 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 829 | void |
Misha Brukman | ee563cb | 2003-05-21 17:59:06 +0000 | [diff] [blame] | 830 | UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec, |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 831 | unsigned PtrReg, |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 832 | int Offset, |
| 833 | unsigned DestReg, |
| 834 | int RegType, |
Chris Lattner | b82d97e | 2002-07-25 06:08:32 +0000 | [diff] [blame] | 835 | int scratchReg) const { |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 836 | MachineInstr * MI = NULL; |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 837 | int OffReg = -1; |
| 838 | |
| 839 | // If the Offset will not fit in the signed-immediate field, find an |
| 840 | // unused register to hold the offset value. This takes advantage of |
| 841 | // the fact that all the opcodes used below have the same size immed. field. |
| 842 | // Use the register allocator, PRA, to find an unused reg. at this MI. |
| 843 | // |
| 844 | if (RegType != IntCCRegType) // does not use offset below |
| 845 | if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) { |
| 846 | #ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY |
| 847 | RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType)); |
| 848 | OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef); |
| 849 | #else |
Brian Gaeke | 641271d | 2003-11-08 18:12:24 +0000 | [diff] [blame] | 850 | // Default to using register g4 for holding large offsets |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 851 | OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID, |
| 852 | SparcIntRegClass::g4); |
| 853 | #endif |
| 854 | assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg."); |
| 855 | mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg)); |
| 856 | } |
| 857 | |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 858 | switch (RegType) { |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 859 | case IntRegType: |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 860 | if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) |
| 861 | MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg, |
| 862 | MOTy::Def); |
| 863 | else |
| 864 | MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg, |
| 865 | MOTy::Def); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 866 | break; |
| 867 | |
| 868 | case FPSingleRegType: |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 869 | if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset)) |
| 870 | MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg, |
| 871 | MOTy::Def); |
| 872 | else |
| 873 | MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg, |
| 874 | MOTy::Def); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 875 | break; |
| 876 | |
| 877 | case FPDoubleRegType: |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 878 | if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset)) |
| 879 | MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg, |
| 880 | MOTy::Def); |
| 881 | else |
| 882 | MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg, |
| 883 | MOTy::Def); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 884 | break; |
| 885 | |
Ruchira Sasanka | 3839e6e | 2001-11-03 19:59:59 +0000 | [diff] [blame] | 886 | case IntCCRegType: |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 887 | assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory"); |
Chris Lattner | 9568568 | 2002-08-12 21:25:05 +0000 | [diff] [blame] | 888 | assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg"); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 889 | cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType); |
Vikram S. Adve | b15f8d4 | 2003-07-10 19:42:11 +0000 | [diff] [blame] | 890 | MI = (BuildMI(V9::WRCCRr, 3) |
| 891 | .addMReg(scratchReg) |
| 892 | .addMReg(SparcIntRegClass::g0) |
| 893 | .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID, |
| 894 | SparcIntCCRegClass::ccr), MOTy::Def)); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 895 | break; |
| 896 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 897 | case FloatCCRegType: { |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 898 | unsigned fsrRegNum = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID, |
| 899 | SparcSpecialRegClass::fsr); |
Vikram S. Adve | 83d30c8 | 2003-07-29 19:53:21 +0000 | [diff] [blame] | 900 | if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset)) |
| 901 | MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset) |
| 902 | .addMReg(fsrRegNum, MOTy::UseAndDef); |
| 903 | else |
| 904 | MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg) |
| 905 | .addMReg(fsrRegNum, MOTy::UseAndDef); |
Vikram S. Adve | 76ee6f7 | 2002-07-08 23:23:12 +0000 | [diff] [blame] | 906 | break; |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 907 | } |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 908 | default: |
Ruchira Sasanka | ae4bcd7 | 2001-11-10 21:20:43 +0000 | [diff] [blame] | 909 | assert(0 && "Unknown RegType in cpMem2RegMI"); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 910 | } |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 911 | mvec.push_back(MI); |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 912 | } |
| 913 | |
| 914 | |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 915 | //--------------------------------------------------------------------------- |
| 916 | // Generate a copy instruction to copy a value to another. Temporarily |
| 917 | // used by PhiElimination code. |
| 918 | //--------------------------------------------------------------------------- |
| 919 | |
| 920 | |
Vikram S. Adve | 242a808 | 2002-05-19 15:25:51 +0000 | [diff] [blame] | 921 | void |
Chris Lattner | 00dca91 | 2003-01-15 17:47:49 +0000 | [diff] [blame] | 922 | UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest, |
Misha Brukman | ee563cb | 2003-05-21 17:59:06 +0000 | [diff] [blame] | 923 | std::vector<MachineInstr*>& mvec) const { |
Vikram S. Adve | 7dc7de5 | 2003-07-25 21:12:15 +0000 | [diff] [blame] | 924 | int RegType = getRegTypeForDataType(Src->getType()); |
Ruchira Sasanka | ef1b0cb | 2001-11-03 17:13:27 +0000 | [diff] [blame] | 925 | MachineInstr * MI = NULL; |
| 926 | |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 927 | switch( RegType ) { |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 928 | case IntRegType: |
Misha Brukman | af6f38e | 2003-05-27 22:40:34 +0000 | [diff] [blame] | 929 | MI = BuildMI(V9::ADDr, 3).addReg(Src).addMReg(getZeroRegNum()) |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 930 | .addRegDef(Dest); |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 931 | break; |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 932 | case FPSingleRegType: |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 933 | MI = BuildMI(V9::FMOVS, 2).addReg(Src).addRegDef(Dest); |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 934 | break; |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 935 | case FPDoubleRegType: |
Misha Brukman | a98cd45 | 2003-05-20 20:32:24 +0000 | [diff] [blame] | 936 | MI = BuildMI(V9::FMOVD, 2).addReg(Src).addRegDef(Dest); |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 937 | break; |
Ruchira Sasanka | 67a463a | 2001-11-12 14:45:33 +0000 | [diff] [blame] | 938 | default: |
| 939 | assert(0 && "Unknow RegType in CpValu2Value"); |
| 940 | } |
Ruchira Sasanka | ef1b0cb | 2001-11-03 17:13:27 +0000 | [diff] [blame] | 941 | |
Chris Lattner | 0fa600d | 2002-10-28 20:10:56 +0000 | [diff] [blame] | 942 | mvec.push_back(MI); |
Ruchira Sasanka | ef1b0cb | 2001-11-03 17:13:27 +0000 | [diff] [blame] | 943 | } |
Ruchira Sasanka | c4d4b76 | 2001-10-16 01:23:19 +0000 | [diff] [blame] | 944 | |
| 945 | |
| 946 | |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 947 | //--------------------------------------------------------------------------- |
| 948 | // Print the register assigned to a LR |
| 949 | //--------------------------------------------------------------------------- |
| 950 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 951 | void UltraSparcRegInfo::printReg(const LiveRange *LR) const { |
Chris Lattner | 3c3c82d | 2003-01-15 21:14:32 +0000 | [diff] [blame] | 952 | unsigned RegClassID = LR->getRegClassID(); |
Chris Lattner | fdba393 | 2003-09-01 19:58:02 +0000 | [diff] [blame] | 953 | std::cerr << " Node "; |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 954 | |
Chris Lattner | 699683c | 2002-02-04 05:59:25 +0000 | [diff] [blame] | 955 | if (!LR->hasColor()) { |
Misha Brukman | ee563cb | 2003-05-21 17:59:06 +0000 | [diff] [blame] | 956 | std::cerr << " - could not find a color\n"; |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 957 | return; |
| 958 | } |
| 959 | |
| 960 | // if a color is found |
| 961 | |
Misha Brukman | ee563cb | 2003-05-21 17:59:06 +0000 | [diff] [blame] | 962 | std::cerr << " colored with color "<< LR->getColor(); |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 963 | |
Vikram S. Adve | 78a4f23 | 2003-05-27 00:02:22 +0000 | [diff] [blame] | 964 | unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor()); |
| 965 | |
| 966 | std::cerr << "["; |
| 967 | std::cerr<< getUnifiedRegName(uRegName); |
| 968 | if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy) |
| 969 | std::cerr << "+" << getUnifiedRegName(uRegName+1); |
| 970 | std::cerr << "]\n"; |
Ruchira Sasanka | 89fb46b | 2001-09-18 22:52:44 +0000 | [diff] [blame] | 971 | } |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame^] | 972 | |
| 973 | } // End llvm namespace |