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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 15e56ad8855ff2d135a79efa71b540852acf3b97 / . / lib / Target / Hexagon / HexagonInstrInfo.h
blob: 9682c05ea1a7f2da4d98ea2242eb8d6a3f93ba3a [file] [log] [blame]
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef HexagonINSTRUCTIONINFO_H
15#define HexagonINSTRUCTIONINFO_H
16
Craig Topper79aa3412012-03-17 18:46:09 +0000[diff] [blame]17#include "HexagonRegisterInfo.h"
Brendon Cahoonc635ebd2012-02-08 18:25:47 +0000[diff] [blame]18#include "MCTargetDesc/HexagonBaseInfo.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/TargetFrameLowering.h"
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]21
22
23#define GET_INSTRINFO_HEADER
24#include "HexagonGenInstrInfo.inc"
25
26namespace llvm {
27
28class HexagonInstrInfo : public HexagonGenInstrInfo {
29 const HexagonRegisterInfo RI;
30 const HexagonSubtarget& Subtarget;
31public:
32 explicit HexagonInstrInfo(HexagonSubtarget &ST);
33
34 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
35 /// such, whenever a client has an instance of instruction info, it should
36 /// always be able to get register info as well (through this method).
37 ///
38 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
39
40 /// isLoadFromStackSlot - If the specified machine instruction is a direct
41 /// load from a stack slot, return the virtual or physical register number of
42 /// the destination along with the FrameIndex of the loaded stack slot. If
43 /// not, return 0. This predicate must return 0 if the instruction has
44 /// any side effects other than loading from the stack slot.
45 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
46 int &FrameIndex) const;
47
48 /// isStoreToStackSlot - If the specified machine instruction is a direct
49 /// store to a stack slot, return the virtual or physical register number of
50 /// the source reg along with the FrameIndex of the loaded stack slot. If
51 /// not, return 0. This predicate must return 0 if the instruction has
52 /// any side effects other than storing to the stack slot.
53 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
54 int &FrameIndex) const;
55
56
57 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
58 MachineBasicBlock *&FBB,
59 SmallVectorImpl<MachineOperand> &Cond,
60 bool AllowModify) const;
61
62 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
63
64 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
65 MachineBasicBlock *FBB,
66 const SmallVectorImpl<MachineOperand> &Cond,
67 DebugLoc DL) const;
68
69 virtual void copyPhysReg(MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator I, DebugLoc DL,
71 unsigned DestReg, unsigned SrcReg,
72 bool KillSrc) const;
73
74 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator MBBI,
76 unsigned SrcReg, bool isKill, int FrameIndex,
77 const TargetRegisterClass *RC,
78 const TargetRegisterInfo *TRI) const;
79
80 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
81 SmallVectorImpl<MachineOperand> &Addr,
82 const TargetRegisterClass *RC,
83 SmallVectorImpl<MachineInstr*> &NewMIs) const;
84
85 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
86 MachineBasicBlock::iterator MBBI,
87 unsigned DestReg, int FrameIndex,
88 const TargetRegisterClass *RC,
89 const TargetRegisterInfo *TRI) const;
90
91 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
92 SmallVectorImpl<MachineOperand> &Addr,
93 const TargetRegisterClass *RC,
94 SmallVectorImpl<MachineInstr*> &NewMIs) const;
95
96 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
97 MachineInstr* MI,
98 const SmallVectorImpl<unsigned> &Ops,
99 int FrameIndex) const;
100
101 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
102 MachineInstr* MI,
103 const SmallVectorImpl<unsigned> &Ops,
104 MachineInstr* LoadMI) const {
105 return 0;
106 }
107
108 unsigned createVR(MachineFunction* MF, MVT VT) const;
109
Sirish Pande15e56ad2012-04-23 17:49:40 +0000[diff] [blame^]110 virtual bool isExtendable(const MachineInstr* MI) const;
111 virtual bool isExtended(const MachineInstr* MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]112 virtual bool isPredicable(MachineInstr *MI) const;
113 virtual bool
114 PredicateInstruction(MachineInstr *MI,
115 const SmallVectorImpl<MachineOperand> &Cond) const;
116
117 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
118 unsigned ExtraPredCycles,
119 const BranchProbability &Probability) const;
120
121 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
122 unsigned NumTCycles, unsigned ExtraTCycles,
123 MachineBasicBlock &FMBB,
124 unsigned NumFCycles, unsigned ExtraFCycles,
125 const BranchProbability &Probability) const;
126
127 virtual bool isPredicated(const MachineInstr *MI) const;
128 virtual bool DefinesPredicate(MachineInstr *MI,
129 std::vector<MachineOperand> &Pred) const;
130 virtual bool
131 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
132 const SmallVectorImpl<MachineOperand> &Pred2) const;
133
134 virtual bool
135 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
136
137 virtual bool
138 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
139 const BranchProbability &Probability) const;
140
Sirish Pande15e56ad2012-04-23 17:49:40 +0000[diff] [blame^]141 unsigned getInvertedPredicatedOpcode(const int Opcode) const;
142 unsigned getImmExtForm(const MachineInstr* MI) const;
143 unsigned getNormalBranchForm(const MachineInstr* MI) const;
144
Andrew Trickee498d32012-02-01 22:13:57 +0000[diff] [blame]145 virtual DFAPacketizer*
146 CreateTargetScheduleState(const TargetMachine *TM,
147 const ScheduleDAG *DAG) const;
148
149 virtual bool isSchedulingBoundary(const MachineInstr *MI,
150 const MachineBasicBlock *MBB,
151 const MachineFunction &MF) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]152 bool isValidOffset(const int Opcode, const int Offset) const;
153 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
154 bool isMemOp(const MachineInstr *MI) const;
155 bool isSpillPredRegOp(const MachineInstr *MI) const;
156 bool isU6_3Immediate(const int value) const;
157 bool isU6_2Immediate(const int value) const;
158 bool isU6_1Immediate(const int value) const;
159 bool isU6_0Immediate(const int value) const;
160 bool isS4_3Immediate(const int value) const;
161 bool isS4_2Immediate(const int value) const;
162 bool isS4_1Immediate(const int value) const;
163 bool isS4_0Immediate(const int value) const;
164 bool isS12_Immediate(const int value) const;
165 bool isU6_Immediate(const int value) const;
166 bool isS8_Immediate(const int value) const;
167 bool isS6_Immediate(const int value) const;
168
Sirish Pande0dac3912012-04-23 17:49:20 +0000[diff] [blame]169 bool isConditionalTransfer(const MachineInstr* MI) const;
Sirish Pande15e56ad2012-04-23 17:49:40 +0000[diff] [blame^]170 bool isConditionalALU32(const MachineInstr* MI) const;
171 bool isConditionalLoad(const MachineInstr* MI) const;
Sirish Pande0dac3912012-04-23 17:49:20 +0000[diff] [blame]172 bool isConditionalStore(const MachineInstr* MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]173 bool isDeallocRet(const MachineInstr *MI) const;
Sirish Pande1bfd2482012-04-23 17:49:28 +0000[diff] [blame]174 bool isNewValueJumpCandidate(const MachineInstr *MI) const;
Sirish Pande15e56ad2012-04-23 17:49:40 +0000[diff] [blame^]175 bool isNewValueJump(const MachineInstr* MI) const;
176 bool isNewValueStore(const MachineInstr* MI) const;
177 bool isPostIncrement(const MachineInstr* MI) const;
178 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]179
180private:
181 int getMatchingCondBranchOpcode(int Opc, bool sense) const;
182
183};
184
185}
186
187#endif