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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / ee498d3254b86bceb4f441741e9f442990647ce6 / . / lib / Target / Hexagon / HexagonInstrInfo.h
blob: 4f49b1f4b2e13a2bd487a8b0848e16d03da0fb1d [file] [log] [blame]
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]1//=- HexagonInstrInfo.h - Hexagon Instruction Information ---------*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef HexagonINSTRUCTIONINFO_H
15#define HexagonINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "llvm/Target/TargetFrameLowering.h"
19#include "HexagonRegisterInfo.h"
20
21
22#define GET_INSTRINFO_HEADER
23#include "HexagonGenInstrInfo.inc"
24
25namespace llvm {
26
27class HexagonInstrInfo : public HexagonGenInstrInfo {
28 const HexagonRegisterInfo RI;
29 const HexagonSubtarget& Subtarget;
30public:
31 explicit HexagonInstrInfo(HexagonSubtarget &ST);
32
33 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
34 /// such, whenever a client has an instance of instruction info, it should
35 /// always be able to get register info as well (through this method).
36 ///
37 virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
38
39 /// isLoadFromStackSlot - If the specified machine instruction is a direct
40 /// load from a stack slot, return the virtual or physical register number of
41 /// the destination along with the FrameIndex of the loaded stack slot. If
42 /// not, return 0. This predicate must return 0 if the instruction has
43 /// any side effects other than loading from the stack slot.
44 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
45 int &FrameIndex) const;
46
47 /// isStoreToStackSlot - If the specified machine instruction is a direct
48 /// store to a stack slot, return the virtual or physical register number of
49 /// the source reg along with the FrameIndex of the loaded stack slot. If
50 /// not, return 0. This predicate must return 0 if the instruction has
51 /// any side effects other than storing to the stack slot.
52 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
53 int &FrameIndex) const;
54
55
56 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
57 MachineBasicBlock *&FBB,
58 SmallVectorImpl<MachineOperand> &Cond,
59 bool AllowModify) const;
60
61 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
62
63 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
64 MachineBasicBlock *FBB,
65 const SmallVectorImpl<MachineOperand> &Cond,
66 DebugLoc DL) const;
67
68 virtual void copyPhysReg(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator I, DebugLoc DL,
70 unsigned DestReg, unsigned SrcReg,
71 bool KillSrc) const;
72
73 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
74 MachineBasicBlock::iterator MBBI,
75 unsigned SrcReg, bool isKill, int FrameIndex,
76 const TargetRegisterClass *RC,
77 const TargetRegisterInfo *TRI) const;
78
79 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
80 SmallVectorImpl<MachineOperand> &Addr,
81 const TargetRegisterClass *RC,
82 SmallVectorImpl<MachineInstr*> &NewMIs) const;
83
84 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
85 MachineBasicBlock::iterator MBBI,
86 unsigned DestReg, int FrameIndex,
87 const TargetRegisterClass *RC,
88 const TargetRegisterInfo *TRI) const;
89
90 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
91 SmallVectorImpl<MachineOperand> &Addr,
92 const TargetRegisterClass *RC,
93 SmallVectorImpl<MachineInstr*> &NewMIs) const;
94
95 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
96 MachineInstr* MI,
97 const SmallVectorImpl<unsigned> &Ops,
98 int FrameIndex) const;
99
100 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
101 MachineInstr* MI,
102 const SmallVectorImpl<unsigned> &Ops,
103 MachineInstr* LoadMI) const {
104 return 0;
105 }
106
107 unsigned createVR(MachineFunction* MF, MVT VT) const;
108
109 virtual bool isPredicable(MachineInstr *MI) const;
110 virtual bool
111 PredicateInstruction(MachineInstr *MI,
112 const SmallVectorImpl<MachineOperand> &Cond) const;
113
114 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
115 unsigned ExtraPredCycles,
116 const BranchProbability &Probability) const;
117
118 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
119 unsigned NumTCycles, unsigned ExtraTCycles,
120 MachineBasicBlock &FMBB,
121 unsigned NumFCycles, unsigned ExtraFCycles,
122 const BranchProbability &Probability) const;
123
124 virtual bool isPredicated(const MachineInstr *MI) const;
125 virtual bool DefinesPredicate(MachineInstr *MI,
126 std::vector<MachineOperand> &Pred) const;
127 virtual bool
128 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
129 const SmallVectorImpl<MachineOperand> &Pred2) const;
130
131 virtual bool
132 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
133
134 virtual bool
135 isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles,
136 const BranchProbability &Probability) const;
137
Andrew Trickee498d32012-02-01 22:13:57 +0000[diff] [blame^]138 virtual DFAPacketizer*
139 CreateTargetScheduleState(const TargetMachine *TM,
140 const ScheduleDAG *DAG) const;
141
142 virtual bool isSchedulingBoundary(const MachineInstr *MI,
143 const MachineBasicBlock *MBB,
144 const MachineFunction &MF) const;
Tony Linthicumb4b54152011-12-12 21:14:40 +0000[diff] [blame]145 bool isValidOffset(const int Opcode, const int Offset) const;
146 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
147 bool isMemOp(const MachineInstr *MI) const;
148 bool isSpillPredRegOp(const MachineInstr *MI) const;
149 bool isU6_3Immediate(const int value) const;
150 bool isU6_2Immediate(const int value) const;
151 bool isU6_1Immediate(const int value) const;
152 bool isU6_0Immediate(const int value) const;
153 bool isS4_3Immediate(const int value) const;
154 bool isS4_2Immediate(const int value) const;
155 bool isS4_1Immediate(const int value) const;
156 bool isS4_0Immediate(const int value) const;
157 bool isS12_Immediate(const int value) const;
158 bool isU6_Immediate(const int value) const;
159 bool isS8_Immediate(const int value) const;
160 bool isS6_Immediate(const int value) const;
161
162 bool isConditionalALU32 (const MachineInstr* MI) const;
163 bool isConditionalLoad (const MachineInstr* MI) const;
164 bool isDeallocRet(const MachineInstr *MI) const;
165
166private:
167 int getMatchingCondBranchOpcode(int Opc, bool sense) const;
168
169};
170
171}
172
173#endif