David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 1 | //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===// |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 10 | // This file contains the Thumb-1 implementation of the TargetInstrInfo class. |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "ARMInstrInfo.h" |
| 15 | #include "ARM.h" |
| 16 | #include "ARMGenInstrInfo.inc" |
| 17 | #include "ARMMachineFunctionInfo.h" |
| 18 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 19 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 20 | #include "llvm/ADT/SmallVector.h" |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 21 | #include "Thumb1InstrInfo.h" |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 22 | |
| 23 | using namespace llvm; |
| 24 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 25 | Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 26 | : ARMBaseInstrInfo(STI), RI(*this, STI) { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 27 | } |
| 28 | |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 29 | unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 30 | return 0; |
| 31 | } |
| 32 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 33 | bool |
| 34 | Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { |
| 35 | if (MBB.empty()) return false; |
| 36 | |
| 37 | switch (MBB.back().getOpcode()) { |
| 38 | case ARM::tBX_RET: |
| 39 | case ARM::tBX_RET_vararg: |
| 40 | case ARM::tPOP_RET: |
| 41 | case ARM::tB: |
| 42 | case ARM::tBR_JTr: |
| 43 | return true; |
| 44 | default: |
| 45 | break; |
| 46 | } |
| 47 | |
| 48 | return false; |
| 49 | } |
| 50 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 51 | bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 52 | MachineBasicBlock::iterator I, |
| 53 | unsigned DestReg, unsigned SrcReg, |
| 54 | const TargetRegisterClass *DestRC, |
| 55 | const TargetRegisterClass *SrcRC) const { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 56 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 57 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 58 | |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 59 | if (DestRC == ARM::GPRRegisterClass) { |
| 60 | if (SrcRC == ARM::GPRRegisterClass) { |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 61 | BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 62 | return true; |
| 63 | } else if (SrcRC == ARM::tGPRRegisterClass) { |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 64 | BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 65 | return true; |
| 66 | } |
| 67 | } else if (DestRC == ARM::tGPRRegisterClass) { |
| 68 | if (SrcRC == ARM::GPRRegisterClass) { |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 69 | BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 70 | return true; |
| 71 | } else if (SrcRC == ARM::tGPRRegisterClass) { |
| 72 | BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg); |
| 73 | return true; |
| 74 | } |
| 75 | } |
| 76 | |
| 77 | return false; |
| 78 | } |
| 79 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 80 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 81 | canFoldMemoryOperand(const MachineInstr *MI, |
| 82 | const SmallVectorImpl<unsigned> &Ops) const { |
| 83 | if (Ops.size() != 1) return false; |
| 84 | |
| 85 | unsigned OpNum = Ops[0]; |
| 86 | unsigned Opc = MI->getOpcode(); |
| 87 | switch (Opc) { |
| 88 | default: break; |
| 89 | case ARM::tMOVr: |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 90 | case ARM::tMOVtgpr2gpr: |
| 91 | case ARM::tMOVgpr2tgpr: |
| 92 | case ARM::tMOVgpr2gpr: { |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 93 | if (OpNum == 0) { // move -> store |
| 94 | unsigned SrcReg = MI->getOperand(1).getReg(); |
Anton Korobeynikov | 55ad1f2 | 2009-06-27 12:59:03 +0000 | [diff] [blame] | 95 | if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg)) |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 96 | // tSpill cannot take a high register operand. |
| 97 | return false; |
| 98 | } else { // move -> load |
| 99 | unsigned DstReg = MI->getOperand(0).getReg(); |
Anton Korobeynikov | 55ad1f2 | 2009-06-27 12:59:03 +0000 | [diff] [blame] | 100 | if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg)) |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 101 | // tRestore cannot target a high register operand. |
| 102 | return false; |
| 103 | } |
| 104 | return true; |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | return false; |
| 109 | } |
| 110 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 111 | void Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 112 | storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 113 | unsigned SrcReg, bool isKill, int FI, |
| 114 | const TargetRegisterClass *RC) const { |
| 115 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 116 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 117 | |
| 118 | assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!"); |
| 119 | |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 120 | if (RC == ARM::tGPRRegisterClass) { |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 121 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill)) |
| 122 | .addReg(SrcReg, getKillRegState(isKill)) |
| 123 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 124 | } |
| 125 | } |
| 126 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 127 | void Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 128 | loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 129 | unsigned DestReg, int FI, |
| 130 | const TargetRegisterClass *RC) const { |
| 131 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 132 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 133 | |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 134 | assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!"); |
| 135 | |
| 136 | if (RC == ARM::tGPRRegisterClass) { |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 137 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg) |
| 138 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 139 | } |
| 140 | } |
| 141 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 142 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 143 | spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 144 | MachineBasicBlock::iterator MI, |
| 145 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 146 | if (CSI.empty()) |
| 147 | return false; |
| 148 | |
| 149 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 150 | if (MI != MBB.end()) DL = MI->getDebugLoc(); |
| 151 | |
| 152 | MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH)); |
| 153 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 154 | unsigned Reg = CSI[i-1].getReg(); |
| 155 | // Add the callee-saved register as live-in. It's killed at the spill. |
| 156 | MBB.addLiveIn(Reg); |
| 157 | MIB.addReg(Reg, RegState::Kill); |
| 158 | } |
| 159 | return true; |
| 160 | } |
| 161 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 162 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 163 | restoreCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 164 | MachineBasicBlock::iterator MI, |
| 165 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 166 | MachineFunction &MF = *MBB.getParent(); |
| 167 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 168 | if (CSI.empty()) |
| 169 | return false; |
| 170 | |
| 171 | bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; |
| 172 | MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc()); |
| 173 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 174 | unsigned Reg = CSI[i-1].getReg(); |
| 175 | if (Reg == ARM::LR) { |
| 176 | // Special epilogue for vararg functions. See emitEpilogue |
| 177 | if (isVarArg) |
| 178 | continue; |
| 179 | Reg = ARM::PC; |
| 180 | PopMI->setDesc(get(ARM::tPOP_RET)); |
| 181 | MI = MBB.erase(MI); |
| 182 | } |
| 183 | PopMI->addOperand(MachineOperand::CreateReg(Reg, true)); |
| 184 | } |
| 185 | |
| 186 | // It's illegal to emit pop instruction without operands. |
| 187 | if (PopMI->getNumOperands() > 0) |
| 188 | MBB.insert(MI, PopMI); |
| 189 | |
| 190 | return true; |
| 191 | } |
| 192 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 193 | MachineInstr *Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 194 | foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, |
| 195 | const SmallVectorImpl<unsigned> &Ops, int FI) const { |
| 196 | if (Ops.size() != 1) return NULL; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 197 | |
| 198 | unsigned OpNum = Ops[0]; |
| 199 | unsigned Opc = MI->getOpcode(); |
| 200 | MachineInstr *NewMI = NULL; |
| 201 | switch (Opc) { |
| 202 | default: break; |
| 203 | case ARM::tMOVr: |
Evan Cheng | d833606 | 2009-07-26 23:59:01 +0000 | [diff] [blame] | 204 | case ARM::tMOVtgpr2gpr: |
| 205 | case ARM::tMOVgpr2tgpr: |
| 206 | case ARM::tMOVgpr2gpr: { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 207 | if (OpNum == 0) { // move -> store |
| 208 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 209 | bool isKill = MI->getOperand(1).isKill(); |
Anton Korobeynikov | 55ad1f2 | 2009-06-27 12:59:03 +0000 | [diff] [blame] | 210 | if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg)) |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 211 | // tSpill cannot take a high register operand. |
| 212 | break; |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 213 | NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill)) |
| 214 | .addReg(SrcReg, getKillRegState(isKill)) |
| 215 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 216 | } else { // move -> load |
| 217 | unsigned DstReg = MI->getOperand(0).getReg(); |
Anton Korobeynikov | 55ad1f2 | 2009-06-27 12:59:03 +0000 | [diff] [blame] | 218 | if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg)) |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 219 | // tRestore cannot target a high register operand. |
| 220 | break; |
| 221 | bool isDead = MI->getOperand(0).isDead(); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame] | 222 | NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore)) |
| 223 | .addReg(DstReg, |
| 224 | RegState::Define | getDeadRegState(isDead)) |
| 225 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 226 | } |
| 227 | break; |
| 228 | } |
| 229 | } |
| 230 | |
| 231 | return NewMI; |
| 232 | } |