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David Goodwinb50ea5c2009-07-02 22:18:33 +00001//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
Anton Korobeynikovd49ea772009-06-26 21:28:53 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
David Goodwinb50ea5c2009-07-02 22:18:33 +000010// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000011//
12//===----------------------------------------------------------------------===//
13
14#include "ARMInstrInfo.h"
15#include "ARM.h"
16#include "ARMGenInstrInfo.inc"
17#include "ARMMachineFunctionInfo.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/ADT/SmallVector.h"
David Goodwinb50ea5c2009-07-02 22:18:33 +000021#include "Thumb1InstrInfo.h"
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000022
23using namespace llvm;
24
David Goodwinb50ea5c2009-07-02 22:18:33 +000025Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
Anton Korobeynikova98cbc52009-06-27 12:16:40 +000026 : ARMBaseInstrInfo(STI), RI(*this, STI) {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000027}
28
Evan Cheng446c4282009-07-11 06:43:01 +000029unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
David Goodwin334c2642009-07-08 16:09:28 +000030 return 0;
31}
32
David Goodwin334c2642009-07-08 16:09:28 +000033bool
34Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
35 if (MBB.empty()) return false;
36
37 switch (MBB.back().getOpcode()) {
38 case ARM::tBX_RET:
39 case ARM::tBX_RET_vararg:
40 case ARM::tPOP_RET:
41 case ARM::tB:
42 case ARM::tBR_JTr:
43 return true;
44 default:
45 break;
46 }
47
48 return false;
49}
50
David Goodwinb50ea5c2009-07-02 22:18:33 +000051bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
52 MachineBasicBlock::iterator I,
53 unsigned DestReg, unsigned SrcReg,
54 const TargetRegisterClass *DestRC,
55 const TargetRegisterClass *SrcRC) const {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000056 DebugLoc DL = DebugLoc::getUnknownLoc();
57 if (I != MBB.end()) DL = I->getDebugLoc();
58
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000059 if (DestRC == ARM::GPRRegisterClass) {
60 if (SrcRC == ARM::GPRRegisterClass) {
Evan Chengd8336062009-07-26 23:59:01 +000061 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000062 return true;
63 } else if (SrcRC == ARM::tGPRRegisterClass) {
Evan Chengd8336062009-07-26 23:59:01 +000064 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000065 return true;
66 }
67 } else if (DestRC == ARM::tGPRRegisterClass) {
68 if (SrcRC == ARM::GPRRegisterClass) {
Evan Chengd8336062009-07-26 23:59:01 +000069 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
Anton Korobeynikovd49ea772009-06-26 21:28:53 +000070 return true;
71 } else if (SrcRC == ARM::tGPRRegisterClass) {
72 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
73 return true;
74 }
75 }
76
77 return false;
78}
79
David Goodwinb50ea5c2009-07-02 22:18:33 +000080bool Thumb1InstrInfo::
Anton Korobeynikova98cbc52009-06-27 12:16:40 +000081canFoldMemoryOperand(const MachineInstr *MI,
82 const SmallVectorImpl<unsigned> &Ops) const {
83 if (Ops.size() != 1) return false;
84
85 unsigned OpNum = Ops[0];
86 unsigned Opc = MI->getOpcode();
87 switch (Opc) {
88 default: break;
89 case ARM::tMOVr:
Evan Chengd8336062009-07-26 23:59:01 +000090 case ARM::tMOVtgpr2gpr:
91 case ARM::tMOVgpr2tgpr:
92 case ARM::tMOVgpr2gpr: {
Anton Korobeynikova98cbc52009-06-27 12:16:40 +000093 if (OpNum == 0) { // move -> store
94 unsigned SrcReg = MI->getOperand(1).getReg();
Anton Korobeynikov55ad1f22009-06-27 12:59:03 +000095 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
Anton Korobeynikova98cbc52009-06-27 12:16:40 +000096 // tSpill cannot take a high register operand.
97 return false;
98 } else { // move -> load
99 unsigned DstReg = MI->getOperand(0).getReg();
Anton Korobeynikov55ad1f22009-06-27 12:59:03 +0000100 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
Anton Korobeynikova98cbc52009-06-27 12:16:40 +0000101 // tRestore cannot target a high register operand.
102 return false;
103 }
104 return true;
105 }
106 }
107
108 return false;
109}
110
David Goodwinb50ea5c2009-07-02 22:18:33 +0000111void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000112storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
113 unsigned SrcReg, bool isKill, int FI,
114 const TargetRegisterClass *RC) const {
115 DebugLoc DL = DebugLoc::getUnknownLoc();
116 if (I != MBB.end()) DL = I->getDebugLoc();
117
118 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
119
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000120 if (RC == ARM::tGPRRegisterClass) {
Evan Cheng446c4282009-07-11 06:43:01 +0000121 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
122 .addReg(SrcReg, getKillRegState(isKill))
123 .addFrameIndex(FI).addImm(0));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000124 }
125}
126
David Goodwinb50ea5c2009-07-02 22:18:33 +0000127void Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000128loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
129 unsigned DestReg, int FI,
130 const TargetRegisterClass *RC) const {
131 DebugLoc DL = DebugLoc::getUnknownLoc();
132 if (I != MBB.end()) DL = I->getDebugLoc();
133
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000134 assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
135
136 if (RC == ARM::tGPRRegisterClass) {
Evan Cheng446c4282009-07-11 06:43:01 +0000137 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
138 .addFrameIndex(FI).addImm(0));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000139 }
140}
141
David Goodwinb50ea5c2009-07-02 22:18:33 +0000142bool Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000143spillCalleeSavedRegisters(MachineBasicBlock &MBB,
144 MachineBasicBlock::iterator MI,
145 const std::vector<CalleeSavedInfo> &CSI) const {
146 if (CSI.empty())
147 return false;
148
149 DebugLoc DL = DebugLoc::getUnknownLoc();
150 if (MI != MBB.end()) DL = MI->getDebugLoc();
151
152 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
153 for (unsigned i = CSI.size(); i != 0; --i) {
154 unsigned Reg = CSI[i-1].getReg();
155 // Add the callee-saved register as live-in. It's killed at the spill.
156 MBB.addLiveIn(Reg);
157 MIB.addReg(Reg, RegState::Kill);
158 }
159 return true;
160}
161
David Goodwinb50ea5c2009-07-02 22:18:33 +0000162bool Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000163restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
164 MachineBasicBlock::iterator MI,
165 const std::vector<CalleeSavedInfo> &CSI) const {
166 MachineFunction &MF = *MBB.getParent();
167 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
168 if (CSI.empty())
169 return false;
170
171 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
172 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
173 for (unsigned i = CSI.size(); i != 0; --i) {
174 unsigned Reg = CSI[i-1].getReg();
175 if (Reg == ARM::LR) {
176 // Special epilogue for vararg functions. See emitEpilogue
177 if (isVarArg)
178 continue;
179 Reg = ARM::PC;
180 PopMI->setDesc(get(ARM::tPOP_RET));
181 MI = MBB.erase(MI);
182 }
183 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
184 }
185
186 // It's illegal to emit pop instruction without operands.
187 if (PopMI->getNumOperands() > 0)
188 MBB.insert(MI, PopMI);
189
190 return true;
191}
192
David Goodwinb50ea5c2009-07-02 22:18:33 +0000193MachineInstr *Thumb1InstrInfo::
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000194foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
195 const SmallVectorImpl<unsigned> &Ops, int FI) const {
196 if (Ops.size() != 1) return NULL;
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000197
198 unsigned OpNum = Ops[0];
199 unsigned Opc = MI->getOpcode();
200 MachineInstr *NewMI = NULL;
201 switch (Opc) {
202 default: break;
203 case ARM::tMOVr:
Evan Chengd8336062009-07-26 23:59:01 +0000204 case ARM::tMOVtgpr2gpr:
205 case ARM::tMOVgpr2tgpr:
206 case ARM::tMOVgpr2gpr: {
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000207 if (OpNum == 0) { // move -> store
208 unsigned SrcReg = MI->getOperand(1).getReg();
209 bool isKill = MI->getOperand(1).isKill();
Anton Korobeynikov55ad1f22009-06-27 12:59:03 +0000210 if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000211 // tSpill cannot take a high register operand.
212 break;
Evan Cheng446c4282009-07-11 06:43:01 +0000213 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
214 .addReg(SrcReg, getKillRegState(isKill))
215 .addFrameIndex(FI).addImm(0));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000216 } else { // move -> load
217 unsigned DstReg = MI->getOperand(0).getReg();
Anton Korobeynikov55ad1f22009-06-27 12:59:03 +0000218 if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000219 // tRestore cannot target a high register operand.
220 break;
221 bool isDead = MI->getOperand(0).isDead();
Evan Cheng446c4282009-07-11 06:43:01 +0000222 NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
223 .addReg(DstReg,
224 RegState::Define | getDeadRegState(isDead))
225 .addFrameIndex(FI).addImm(0));
Anton Korobeynikovd49ea772009-06-26 21:28:53 +0000226 }
227 break;
228 }
229 }
230
231 return NewMI;
232}