David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 1 | //===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===// |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 10 | // This file contains the Thumb-1 implementation of the TargetInstrInfo class. |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "ARMInstrInfo.h" |
| 15 | #include "ARM.h" |
| 16 | #include "ARMGenInstrInfo.inc" |
| 17 | #include "ARMMachineFunctionInfo.h" |
| 18 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 19 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 20 | #include "llvm/ADT/SmallVector.h" |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 21 | #include "Thumb1InstrInfo.h" |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 22 | |
| 23 | using namespace llvm; |
| 24 | |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame^] | 25 | static inline |
| 26 | const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { |
| 27 | return MIB.addImm((int64_t)ARMCC::AL).addReg(0); |
| 28 | } |
| 29 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 30 | Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 31 | : ARMBaseInstrInfo(STI), RI(*this, STI) { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 32 | } |
| 33 | |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame^] | 34 | unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 35 | return 0; |
| 36 | } |
| 37 | |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame^] | 38 | unsigned Thumb1InstrInfo::getOpcode(ARMII::Op Op) const { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 39 | switch (Op) { |
| 40 | case ARMII::ADDri: return ARM::tADDi8; |
| 41 | case ARMII::ADDrs: return 0; |
| 42 | case ARMII::ADDrr: return ARM::tADDrr; |
| 43 | case ARMII::B: return ARM::tB; |
| 44 | case ARMII::Bcc: return ARM::tBcc; |
| 45 | case ARMII::BR_JTr: return ARM::tBR_JTr; |
| 46 | case ARMII::BR_JTm: return 0; |
| 47 | case ARMII::BR_JTadd: return 0; |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 48 | case ARMII::BX_RET: return ARM::tBX_RET; |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 49 | case ARMII::FCPYS: return 0; |
| 50 | case ARMII::FCPYD: return 0; |
| 51 | case ARMII::FLDD: return 0; |
| 52 | case ARMII::FLDS: return 0; |
| 53 | case ARMII::FSTD: return 0; |
| 54 | case ARMII::FSTS: return 0; |
| 55 | case ARMII::LDR: return ARM::tLDR; |
| 56 | case ARMII::MOVr: return ARM::tMOVr; |
| 57 | case ARMII::STR: return ARM::tSTR; |
| 58 | case ARMII::SUBri: return ARM::tSUBi8; |
| 59 | case ARMII::SUBrs: return 0; |
| 60 | case ARMII::SUBrr: return ARM::tSUBrr; |
| 61 | case ARMII::VMOVD: return 0; |
| 62 | case ARMII::VMOVQ: return 0; |
| 63 | default: |
| 64 | break; |
| 65 | } |
| 66 | |
| 67 | return 0; |
| 68 | } |
| 69 | |
| 70 | bool |
| 71 | Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { |
| 72 | if (MBB.empty()) return false; |
| 73 | |
| 74 | switch (MBB.back().getOpcode()) { |
| 75 | case ARM::tBX_RET: |
| 76 | case ARM::tBX_RET_vararg: |
| 77 | case ARM::tPOP_RET: |
| 78 | case ARM::tB: |
| 79 | case ARM::tBR_JTr: |
| 80 | return true; |
| 81 | default: |
| 82 | break; |
| 83 | } |
| 84 | |
| 85 | return false; |
| 86 | } |
| 87 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 88 | bool Thumb1InstrInfo::isMoveInstr(const MachineInstr &MI, |
| 89 | unsigned &SrcReg, unsigned &DstReg, |
| 90 | unsigned& SrcSubIdx, unsigned& DstSubIdx) const { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 91 | SrcSubIdx = DstSubIdx = 0; // No sub-registers. |
| 92 | |
| 93 | unsigned oc = MI.getOpcode(); |
| 94 | switch (oc) { |
| 95 | default: |
| 96 | return false; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 97 | case ARM::tMOVr: |
| 98 | case ARM::tMOVhir2lor: |
| 99 | case ARM::tMOVlor2hir: |
| 100 | case ARM::tMOVhir2hir: |
| 101 | assert(MI.getDesc().getNumOperands() >= 2 && |
| 102 | MI.getOperand(0).isReg() && |
| 103 | MI.getOperand(1).isReg() && |
| 104 | "Invalid Thumb MOV instruction"); |
| 105 | SrcReg = MI.getOperand(1).getReg(); |
| 106 | DstReg = MI.getOperand(0).getReg(); |
| 107 | return true; |
| 108 | } |
| 109 | } |
| 110 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 111 | unsigned Thumb1InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, |
| 112 | int &FrameIndex) const { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 113 | switch (MI->getOpcode()) { |
| 114 | default: break; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 115 | case ARM::tRestore: |
| 116 | if (MI->getOperand(1).isFI() && |
| 117 | MI->getOperand(2).isImm() && |
| 118 | MI->getOperand(2).getImm() == 0) { |
| 119 | FrameIndex = MI->getOperand(1).getIndex(); |
| 120 | return MI->getOperand(0).getReg(); |
| 121 | } |
| 122 | break; |
| 123 | } |
| 124 | return 0; |
| 125 | } |
| 126 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 127 | unsigned Thumb1InstrInfo::isStoreToStackSlot(const MachineInstr *MI, |
| 128 | int &FrameIndex) const { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 129 | switch (MI->getOpcode()) { |
| 130 | default: break; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 131 | case ARM::tSpill: |
| 132 | if (MI->getOperand(1).isFI() && |
| 133 | MI->getOperand(2).isImm() && |
| 134 | MI->getOperand(2).getImm() == 0) { |
| 135 | FrameIndex = MI->getOperand(1).getIndex(); |
| 136 | return MI->getOperand(0).getReg(); |
| 137 | } |
| 138 | break; |
| 139 | } |
| 140 | return 0; |
| 141 | } |
| 142 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 143 | bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 144 | MachineBasicBlock::iterator I, |
| 145 | unsigned DestReg, unsigned SrcReg, |
| 146 | const TargetRegisterClass *DestRC, |
| 147 | const TargetRegisterClass *SrcRC) const { |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 148 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 149 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 150 | |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 151 | if (DestRC == ARM::GPRRegisterClass) { |
| 152 | if (SrcRC == ARM::GPRRegisterClass) { |
| 153 | BuildMI(MBB, I, DL, get(ARM::tMOVhir2hir), DestReg).addReg(SrcReg); |
| 154 | return true; |
| 155 | } else if (SrcRC == ARM::tGPRRegisterClass) { |
| 156 | BuildMI(MBB, I, DL, get(ARM::tMOVlor2hir), DestReg).addReg(SrcReg); |
| 157 | return true; |
| 158 | } |
| 159 | } else if (DestRC == ARM::tGPRRegisterClass) { |
| 160 | if (SrcRC == ARM::GPRRegisterClass) { |
| 161 | BuildMI(MBB, I, DL, get(ARM::tMOVhir2lor), DestReg).addReg(SrcReg); |
| 162 | return true; |
| 163 | } else if (SrcRC == ARM::tGPRRegisterClass) { |
| 164 | BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg); |
| 165 | return true; |
| 166 | } |
| 167 | } |
| 168 | |
| 169 | return false; |
| 170 | } |
| 171 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 172 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 173 | canFoldMemoryOperand(const MachineInstr *MI, |
| 174 | const SmallVectorImpl<unsigned> &Ops) const { |
| 175 | if (Ops.size() != 1) return false; |
| 176 | |
| 177 | unsigned OpNum = Ops[0]; |
| 178 | unsigned Opc = MI->getOpcode(); |
| 179 | switch (Opc) { |
| 180 | default: break; |
| 181 | case ARM::tMOVr: |
| 182 | case ARM::tMOVlor2hir: |
| 183 | case ARM::tMOVhir2lor: |
| 184 | case ARM::tMOVhir2hir: { |
| 185 | if (OpNum == 0) { // move -> store |
| 186 | unsigned SrcReg = MI->getOperand(1).getReg(); |
Anton Korobeynikov | 55ad1f2 | 2009-06-27 12:59:03 +0000 | [diff] [blame] | 187 | if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg)) |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 188 | // tSpill cannot take a high register operand. |
| 189 | return false; |
| 190 | } else { // move -> load |
| 191 | unsigned DstReg = MI->getOperand(0).getReg(); |
Anton Korobeynikov | 55ad1f2 | 2009-06-27 12:59:03 +0000 | [diff] [blame] | 192 | if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg)) |
Anton Korobeynikov | a98cbc5 | 2009-06-27 12:16:40 +0000 | [diff] [blame] | 193 | // tRestore cannot target a high register operand. |
| 194 | return false; |
| 195 | } |
| 196 | return true; |
| 197 | } |
| 198 | } |
| 199 | |
| 200 | return false; |
| 201 | } |
| 202 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 203 | void Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 204 | storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 205 | unsigned SrcReg, bool isKill, int FI, |
| 206 | const TargetRegisterClass *RC) const { |
| 207 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 208 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 209 | |
| 210 | assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!"); |
| 211 | |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 212 | if (RC == ARM::tGPRRegisterClass) { |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame^] | 213 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill)) |
| 214 | .addReg(SrcReg, getKillRegState(isKill)) |
| 215 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 216 | } |
| 217 | } |
| 218 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 219 | void Thumb1InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, |
| 220 | bool isKill, |
| 221 | SmallVectorImpl<MachineOperand> &Addr, |
| 222 | const TargetRegisterClass *RC, |
| 223 | SmallVectorImpl<MachineInstr*> &NewMIs) const{ |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 224 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 225 | unsigned Opc = 0; |
| 226 | |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 227 | assert(RC == ARM::GPRRegisterClass && "Unknown regclass!"); |
| 228 | if (RC == ARM::GPRRegisterClass) { |
| 229 | Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR; |
| 230 | } |
| 231 | |
| 232 | MachineInstrBuilder MIB = |
| 233 | BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)); |
| 234 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) |
| 235 | MIB.addOperand(Addr[i]); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame^] | 236 | AddDefaultPred(MIB); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 237 | NewMIs.push_back(MIB); |
| 238 | return; |
| 239 | } |
| 240 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 241 | void Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 242 | loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 243 | unsigned DestReg, int FI, |
| 244 | const TargetRegisterClass *RC) const { |
| 245 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 246 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 247 | |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 248 | assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!"); |
| 249 | |
| 250 | if (RC == ARM::tGPRRegisterClass) { |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame^] | 251 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg) |
| 252 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 253 | } |
| 254 | } |
| 255 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 256 | void Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 257 | loadRegFromAddr(MachineFunction &MF, unsigned DestReg, |
| 258 | SmallVectorImpl<MachineOperand> &Addr, |
| 259 | const TargetRegisterClass *RC, |
| 260 | SmallVectorImpl<MachineInstr*> &NewMIs) const { |
| 261 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 262 | unsigned Opc = 0; |
| 263 | |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 264 | if (RC == ARM::GPRRegisterClass) { |
| 265 | Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR; |
| 266 | } |
| 267 | |
| 268 | MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); |
| 269 | for (unsigned i = 0, e = Addr.size(); i != e; ++i) |
| 270 | MIB.addOperand(Addr[i]); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame^] | 271 | AddDefaultPred(MIB); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 272 | NewMIs.push_back(MIB); |
| 273 | return; |
| 274 | } |
| 275 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 276 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 277 | spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 278 | MachineBasicBlock::iterator MI, |
| 279 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 280 | if (CSI.empty()) |
| 281 | return false; |
| 282 | |
| 283 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 284 | if (MI != MBB.end()) DL = MI->getDebugLoc(); |
| 285 | |
| 286 | MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH)); |
| 287 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 288 | unsigned Reg = CSI[i-1].getReg(); |
| 289 | // Add the callee-saved register as live-in. It's killed at the spill. |
| 290 | MBB.addLiveIn(Reg); |
| 291 | MIB.addReg(Reg, RegState::Kill); |
| 292 | } |
| 293 | return true; |
| 294 | } |
| 295 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 296 | bool Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 297 | restoreCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 298 | MachineBasicBlock::iterator MI, |
| 299 | const std::vector<CalleeSavedInfo> &CSI) const { |
| 300 | MachineFunction &MF = *MBB.getParent(); |
| 301 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 302 | if (CSI.empty()) |
| 303 | return false; |
| 304 | |
| 305 | bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; |
| 306 | MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc()); |
| 307 | for (unsigned i = CSI.size(); i != 0; --i) { |
| 308 | unsigned Reg = CSI[i-1].getReg(); |
| 309 | if (Reg == ARM::LR) { |
| 310 | // Special epilogue for vararg functions. See emitEpilogue |
| 311 | if (isVarArg) |
| 312 | continue; |
| 313 | Reg = ARM::PC; |
| 314 | PopMI->setDesc(get(ARM::tPOP_RET)); |
| 315 | MI = MBB.erase(MI); |
| 316 | } |
| 317 | PopMI->addOperand(MachineOperand::CreateReg(Reg, true)); |
| 318 | } |
| 319 | |
| 320 | // It's illegal to emit pop instruction without operands. |
| 321 | if (PopMI->getNumOperands() > 0) |
| 322 | MBB.insert(MI, PopMI); |
| 323 | |
| 324 | return true; |
| 325 | } |
| 326 | |
David Goodwin | b50ea5c | 2009-07-02 22:18:33 +0000 | [diff] [blame] | 327 | MachineInstr *Thumb1InstrInfo:: |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 328 | foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, |
| 329 | const SmallVectorImpl<unsigned> &Ops, int FI) const { |
| 330 | if (Ops.size() != 1) return NULL; |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 331 | |
| 332 | unsigned OpNum = Ops[0]; |
| 333 | unsigned Opc = MI->getOpcode(); |
| 334 | MachineInstr *NewMI = NULL; |
| 335 | switch (Opc) { |
| 336 | default: break; |
| 337 | case ARM::tMOVr: |
| 338 | case ARM::tMOVlor2hir: |
| 339 | case ARM::tMOVhir2lor: |
| 340 | case ARM::tMOVhir2hir: { |
| 341 | if (OpNum == 0) { // move -> store |
| 342 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 343 | bool isKill = MI->getOperand(1).isKill(); |
Anton Korobeynikov | 55ad1f2 | 2009-06-27 12:59:03 +0000 | [diff] [blame] | 344 | if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg)) |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 345 | // tSpill cannot take a high register operand. |
| 346 | break; |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame^] | 347 | NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill)) |
| 348 | .addReg(SrcReg, getKillRegState(isKill)) |
| 349 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 350 | } else { // move -> load |
| 351 | unsigned DstReg = MI->getOperand(0).getReg(); |
Anton Korobeynikov | 55ad1f2 | 2009-06-27 12:59:03 +0000 | [diff] [blame] | 352 | if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg)) |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 353 | // tRestore cannot target a high register operand. |
| 354 | break; |
| 355 | bool isDead = MI->getOperand(0).isDead(); |
Evan Cheng | 446c428 | 2009-07-11 06:43:01 +0000 | [diff] [blame^] | 356 | NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore)) |
| 357 | .addReg(DstReg, |
| 358 | RegState::Define | getDeadRegState(isDead)) |
| 359 | .addFrameIndex(FI).addImm(0)); |
Anton Korobeynikov | d49ea77 | 2009-06-26 21:28:53 +0000 | [diff] [blame] | 360 | } |
| 361 | break; |
| 362 | } |
| 363 | } |
| 364 | |
| 365 | return NewMI; |
| 366 | } |