David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1 | //===- ARMBaseRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the base ARM implementation of TargetRegisterInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "ARM.h" |
| 15 | #include "ARMAddressingModes.h" |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 16 | #include "ARMBaseInstrInfo.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 17 | #include "ARMBaseRegisterInfo.h" |
| 18 | #include "ARMInstrInfo.h" |
| 19 | #include "ARMMachineFunctionInfo.h" |
| 20 | #include "ARMSubtarget.h" |
| 21 | #include "llvm/Constants.h" |
| 22 | #include "llvm/DerivedTypes.h" |
| 23 | #include "llvm/CodeGen/MachineConstantPool.h" |
| 24 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 25 | #include "llvm/CodeGen/MachineFunction.h" |
| 26 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 27 | #include "llvm/CodeGen/MachineLocation.h" |
| 28 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
| 29 | #include "llvm/CodeGen/RegisterScavenging.h" |
Torok Edwin | ab7c09b | 2009-07-08 18:01:40 +0000 | [diff] [blame] | 30 | #include "llvm/Support/ErrorHandling.h" |
Torok Edwin | dac237e | 2009-07-08 20:53:28 +0000 | [diff] [blame^] | 31 | #include "llvm/Support/raw_ostream.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 32 | #include "llvm/Target/TargetFrameInfo.h" |
| 33 | #include "llvm/Target/TargetMachine.h" |
| 34 | #include "llvm/Target/TargetOptions.h" |
| 35 | #include "llvm/ADT/BitVector.h" |
| 36 | #include "llvm/ADT/SmallVector.h" |
| 37 | using namespace llvm; |
| 38 | |
| 39 | unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum) { |
| 40 | using namespace ARM; |
| 41 | switch (RegEnum) { |
| 42 | case R0: case S0: case D0: return 0; |
| 43 | case R1: case S1: case D1: return 1; |
| 44 | case R2: case S2: case D2: return 2; |
| 45 | case R3: case S3: case D3: return 3; |
| 46 | case R4: case S4: case D4: return 4; |
| 47 | case R5: case S5: case D5: return 5; |
| 48 | case R6: case S6: case D6: return 6; |
| 49 | case R7: case S7: case D7: return 7; |
| 50 | case R8: case S8: case D8: return 8; |
| 51 | case R9: case S9: case D9: return 9; |
| 52 | case R10: case S10: case D10: return 10; |
| 53 | case R11: case S11: case D11: return 11; |
| 54 | case R12: case S12: case D12: return 12; |
| 55 | case SP: case S13: case D13: return 13; |
| 56 | case LR: case S14: case D14: return 14; |
| 57 | case PC: case S15: case D15: return 15; |
| 58 | case S16: return 16; |
| 59 | case S17: return 17; |
| 60 | case S18: return 18; |
| 61 | case S19: return 19; |
| 62 | case S20: return 20; |
| 63 | case S21: return 21; |
| 64 | case S22: return 22; |
| 65 | case S23: return 23; |
| 66 | case S24: return 24; |
| 67 | case S25: return 25; |
| 68 | case S26: return 26; |
| 69 | case S27: return 27; |
| 70 | case S28: return 28; |
| 71 | case S29: return 29; |
| 72 | case S30: return 30; |
| 73 | case S31: return 31; |
| 74 | default: |
Torok Edwin | ab7c09b | 2009-07-08 18:01:40 +0000 | [diff] [blame] | 75 | LLVM_UNREACHABLE("Unknown ARM register!"); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 76 | } |
| 77 | } |
| 78 | |
| 79 | unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, |
| 80 | bool &isSPVFP) { |
| 81 | isSPVFP = false; |
| 82 | |
| 83 | using namespace ARM; |
| 84 | switch (RegEnum) { |
| 85 | default: |
Torok Edwin | ab7c09b | 2009-07-08 18:01:40 +0000 | [diff] [blame] | 86 | LLVM_UNREACHABLE("Unknown ARM register!"); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 87 | case R0: case D0: return 0; |
| 88 | case R1: case D1: return 1; |
| 89 | case R2: case D2: return 2; |
| 90 | case R3: case D3: return 3; |
| 91 | case R4: case D4: return 4; |
| 92 | case R5: case D5: return 5; |
| 93 | case R6: case D6: return 6; |
| 94 | case R7: case D7: return 7; |
| 95 | case R8: case D8: return 8; |
| 96 | case R9: case D9: return 9; |
| 97 | case R10: case D10: return 10; |
| 98 | case R11: case D11: return 11; |
| 99 | case R12: case D12: return 12; |
| 100 | case SP: case D13: return 13; |
| 101 | case LR: case D14: return 14; |
| 102 | case PC: case D15: return 15; |
| 103 | |
| 104 | case S0: case S1: case S2: case S3: |
| 105 | case S4: case S5: case S6: case S7: |
| 106 | case S8: case S9: case S10: case S11: |
| 107 | case S12: case S13: case S14: case S15: |
| 108 | case S16: case S17: case S18: case S19: |
| 109 | case S20: case S21: case S22: case S23: |
| 110 | case S24: case S25: case S26: case S27: |
| 111 | case S28: case S29: case S30: case S31: { |
| 112 | isSPVFP = true; |
| 113 | switch (RegEnum) { |
| 114 | default: return 0; // Avoid compile time warning. |
| 115 | case S0: return 0; |
| 116 | case S1: return 1; |
| 117 | case S2: return 2; |
| 118 | case S3: return 3; |
| 119 | case S4: return 4; |
| 120 | case S5: return 5; |
| 121 | case S6: return 6; |
| 122 | case S7: return 7; |
| 123 | case S8: return 8; |
| 124 | case S9: return 9; |
| 125 | case S10: return 10; |
| 126 | case S11: return 11; |
| 127 | case S12: return 12; |
| 128 | case S13: return 13; |
| 129 | case S14: return 14; |
| 130 | case S15: return 15; |
| 131 | case S16: return 16; |
| 132 | case S17: return 17; |
| 133 | case S18: return 18; |
| 134 | case S19: return 19; |
| 135 | case S20: return 20; |
| 136 | case S21: return 21; |
| 137 | case S22: return 22; |
| 138 | case S23: return 23; |
| 139 | case S24: return 24; |
| 140 | case S25: return 25; |
| 141 | case S26: return 26; |
| 142 | case S27: return 27; |
| 143 | case S28: return 28; |
| 144 | case S29: return 29; |
| 145 | case S30: return 30; |
| 146 | case S31: return 31; |
| 147 | } |
| 148 | } |
| 149 | } |
| 150 | } |
| 151 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 152 | ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 153 | const ARMSubtarget &sti) |
| 154 | : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), |
| 155 | TII(tii), STI(sti), |
| 156 | FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) { |
| 157 | } |
| 158 | |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 159 | unsigned ARMBaseRegisterInfo:: |
| 160 | getOpcode(int Op) const { |
| 161 | return TII.getOpcode((ARMII::Op)Op); |
| 162 | } |
| 163 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 164 | const unsigned* |
| 165 | ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
| 166 | static const unsigned CalleeSavedRegs[] = { |
| 167 | ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, |
| 168 | ARM::R7, ARM::R6, ARM::R5, ARM::R4, |
| 169 | |
| 170 | ARM::D15, ARM::D14, ARM::D13, ARM::D12, |
| 171 | ARM::D11, ARM::D10, ARM::D9, ARM::D8, |
| 172 | 0 |
| 173 | }; |
| 174 | |
| 175 | static const unsigned DarwinCalleeSavedRegs[] = { |
| 176 | // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved |
| 177 | // register. |
| 178 | ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, |
| 179 | ARM::R11, ARM::R10, ARM::R8, |
| 180 | |
| 181 | ARM::D15, ARM::D14, ARM::D13, ARM::D12, |
| 182 | ARM::D11, ARM::D10, ARM::D9, ARM::D8, |
| 183 | 0 |
| 184 | }; |
| 185 | return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs; |
| 186 | } |
| 187 | |
| 188 | const TargetRegisterClass* const * |
| 189 | ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { |
| 190 | static const TargetRegisterClass * const CalleeSavedRegClasses[] = { |
| 191 | &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, |
| 192 | &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, |
| 193 | &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, |
| 194 | |
| 195 | &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, |
| 196 | &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, |
| 197 | 0 |
| 198 | }; |
| 199 | |
| 200 | static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = { |
| 201 | &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, |
| 202 | &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass, |
| 203 | &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass, |
| 204 | |
| 205 | &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, |
| 206 | &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, |
| 207 | 0 |
| 208 | }; |
| 209 | |
| 210 | static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = { |
| 211 | &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, |
| 212 | &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass, |
| 213 | &ARM::GPRRegClass, &ARM::GPRRegClass, |
| 214 | |
| 215 | &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, |
| 216 | &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, |
| 217 | 0 |
| 218 | }; |
| 219 | |
| 220 | static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={ |
| 221 | &ARM::GPRRegClass, &ARM::tGPRRegClass, &ARM::tGPRRegClass, |
| 222 | &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass, |
| 223 | &ARM::GPRRegClass, &ARM::GPRRegClass, |
| 224 | |
| 225 | &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, |
| 226 | &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, |
| 227 | 0 |
| 228 | }; |
| 229 | |
| 230 | if (STI.isThumb()) { |
| 231 | return STI.isTargetDarwin() |
| 232 | ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses; |
| 233 | } |
| 234 | return STI.isTargetDarwin() |
| 235 | ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses; |
| 236 | } |
| 237 | |
| 238 | BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| 239 | // FIXME: avoid re-calculating this everytime. |
| 240 | BitVector Reserved(getNumRegs()); |
| 241 | Reserved.set(ARM::SP); |
| 242 | Reserved.set(ARM::PC); |
| 243 | if (STI.isTargetDarwin() || hasFP(MF)) |
| 244 | Reserved.set(FramePtr); |
| 245 | // Some targets reserve R9. |
| 246 | if (STI.isR9Reserved()) |
| 247 | Reserved.set(ARM::R9); |
| 248 | return Reserved; |
| 249 | } |
| 250 | |
| 251 | bool |
| 252 | ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { |
| 253 | switch (Reg) { |
| 254 | default: break; |
| 255 | case ARM::SP: |
| 256 | case ARM::PC: |
| 257 | return true; |
| 258 | case ARM::R7: |
| 259 | case ARM::R11: |
| 260 | if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF))) |
| 261 | return true; |
| 262 | break; |
| 263 | case ARM::R9: |
| 264 | return STI.isR9Reserved(); |
| 265 | } |
| 266 | |
| 267 | return false; |
| 268 | } |
| 269 | |
| 270 | const TargetRegisterClass *ARMBaseRegisterInfo::getPointerRegClass() const { |
| 271 | return &ARM::GPRRegClass; |
| 272 | } |
| 273 | |
| 274 | /// getAllocationOrder - Returns the register allocation order for a specified |
| 275 | /// register class in the form of a pair of TargetRegisterClass iterators. |
| 276 | std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator> |
| 277 | ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, |
| 278 | unsigned HintType, unsigned HintReg, |
| 279 | const MachineFunction &MF) const { |
| 280 | // Alternative register allocation orders when favoring even / odd registers |
| 281 | // of register pairs. |
| 282 | |
| 283 | // No FP, R9 is available. |
| 284 | static const unsigned GPREven1[] = { |
| 285 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, |
| 286 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, |
| 287 | ARM::R9, ARM::R11 |
| 288 | }; |
| 289 | static const unsigned GPROdd1[] = { |
| 290 | ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, |
| 291 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, |
| 292 | ARM::R8, ARM::R10 |
| 293 | }; |
| 294 | |
| 295 | // FP is R7, R9 is available. |
| 296 | static const unsigned GPREven2[] = { |
| 297 | ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, |
| 298 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, |
| 299 | ARM::R9, ARM::R11 |
| 300 | }; |
| 301 | static const unsigned GPROdd2[] = { |
| 302 | ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, |
| 303 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, |
| 304 | ARM::R8, ARM::R10 |
| 305 | }; |
| 306 | |
| 307 | // FP is R11, R9 is available. |
| 308 | static const unsigned GPREven3[] = { |
| 309 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, |
| 310 | ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, |
| 311 | ARM::R9 |
| 312 | }; |
| 313 | static const unsigned GPROdd3[] = { |
| 314 | ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, |
| 315 | ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, |
| 316 | ARM::R8 |
| 317 | }; |
| 318 | |
| 319 | // No FP, R9 is not available. |
| 320 | static const unsigned GPREven4[] = { |
| 321 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, |
| 322 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, |
| 323 | ARM::R11 |
| 324 | }; |
| 325 | static const unsigned GPROdd4[] = { |
| 326 | ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, |
| 327 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, |
| 328 | ARM::R10 |
| 329 | }; |
| 330 | |
| 331 | // FP is R7, R9 is not available. |
| 332 | static const unsigned GPREven5[] = { |
| 333 | ARM::R0, ARM::R2, ARM::R4, ARM::R10, |
| 334 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, |
| 335 | ARM::R11 |
| 336 | }; |
| 337 | static const unsigned GPROdd5[] = { |
| 338 | ARM::R1, ARM::R3, ARM::R5, ARM::R11, |
| 339 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, |
| 340 | ARM::R10 |
| 341 | }; |
| 342 | |
| 343 | // FP is R11, R9 is not available. |
| 344 | static const unsigned GPREven6[] = { |
| 345 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, |
| 346 | ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 |
| 347 | }; |
| 348 | static const unsigned GPROdd6[] = { |
| 349 | ARM::R1, ARM::R3, ARM::R5, ARM::R7, |
| 350 | ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 |
| 351 | }; |
| 352 | |
| 353 | |
| 354 | if (HintType == ARMRI::RegPairEven) { |
| 355 | if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) |
| 356 | // It's no longer possible to fulfill this hint. Return the default |
| 357 | // allocation order. |
| 358 | return std::make_pair(RC->allocation_order_begin(MF), |
| 359 | RC->allocation_order_end(MF)); |
| 360 | |
| 361 | if (!STI.isTargetDarwin() && !hasFP(MF)) { |
| 362 | if (!STI.isR9Reserved()) |
| 363 | return std::make_pair(GPREven1, |
| 364 | GPREven1 + (sizeof(GPREven1)/sizeof(unsigned))); |
| 365 | else |
| 366 | return std::make_pair(GPREven4, |
| 367 | GPREven4 + (sizeof(GPREven4)/sizeof(unsigned))); |
| 368 | } else if (FramePtr == ARM::R7) { |
| 369 | if (!STI.isR9Reserved()) |
| 370 | return std::make_pair(GPREven2, |
| 371 | GPREven2 + (sizeof(GPREven2)/sizeof(unsigned))); |
| 372 | else |
| 373 | return std::make_pair(GPREven5, |
| 374 | GPREven5 + (sizeof(GPREven5)/sizeof(unsigned))); |
| 375 | } else { // FramePtr == ARM::R11 |
| 376 | if (!STI.isR9Reserved()) |
| 377 | return std::make_pair(GPREven3, |
| 378 | GPREven3 + (sizeof(GPREven3)/sizeof(unsigned))); |
| 379 | else |
| 380 | return std::make_pair(GPREven6, |
| 381 | GPREven6 + (sizeof(GPREven6)/sizeof(unsigned))); |
| 382 | } |
| 383 | } else if (HintType == ARMRI::RegPairOdd) { |
| 384 | if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) |
| 385 | // It's no longer possible to fulfill this hint. Return the default |
| 386 | // allocation order. |
| 387 | return std::make_pair(RC->allocation_order_begin(MF), |
| 388 | RC->allocation_order_end(MF)); |
| 389 | |
| 390 | if (!STI.isTargetDarwin() && !hasFP(MF)) { |
| 391 | if (!STI.isR9Reserved()) |
| 392 | return std::make_pair(GPROdd1, |
| 393 | GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned))); |
| 394 | else |
| 395 | return std::make_pair(GPROdd4, |
| 396 | GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned))); |
| 397 | } else if (FramePtr == ARM::R7) { |
| 398 | if (!STI.isR9Reserved()) |
| 399 | return std::make_pair(GPROdd2, |
| 400 | GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned))); |
| 401 | else |
| 402 | return std::make_pair(GPROdd5, |
| 403 | GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned))); |
| 404 | } else { // FramePtr == ARM::R11 |
| 405 | if (!STI.isR9Reserved()) |
| 406 | return std::make_pair(GPROdd3, |
| 407 | GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned))); |
| 408 | else |
| 409 | return std::make_pair(GPROdd6, |
| 410 | GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned))); |
| 411 | } |
| 412 | } |
| 413 | return std::make_pair(RC->allocation_order_begin(MF), |
| 414 | RC->allocation_order_end(MF)); |
| 415 | } |
| 416 | |
| 417 | /// ResolveRegAllocHint - Resolves the specified register allocation hint |
| 418 | /// to a physical register. Returns the physical register if it is successful. |
| 419 | unsigned |
| 420 | ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, |
| 421 | const MachineFunction &MF) const { |
| 422 | if (Reg == 0 || !isPhysicalRegister(Reg)) |
| 423 | return 0; |
| 424 | if (Type == 0) |
| 425 | return Reg; |
| 426 | else if (Type == (unsigned)ARMRI::RegPairOdd) |
| 427 | // Odd register. |
| 428 | return getRegisterPairOdd(Reg, MF); |
| 429 | else if (Type == (unsigned)ARMRI::RegPairEven) |
| 430 | // Even register. |
| 431 | return getRegisterPairEven(Reg, MF); |
| 432 | return 0; |
| 433 | } |
| 434 | |
| 435 | void |
| 436 | ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, |
| 437 | MachineFunction &MF) const { |
| 438 | MachineRegisterInfo *MRI = &MF.getRegInfo(); |
| 439 | std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); |
| 440 | if ((Hint.first == (unsigned)ARMRI::RegPairOdd || |
| 441 | Hint.first == (unsigned)ARMRI::RegPairEven) && |
| 442 | Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) { |
| 443 | // If 'Reg' is one of the even / odd register pair and it's now changed |
| 444 | // (e.g. coalesced) into a different register. The other register of the |
| 445 | // pair allocation hint must be updated to reflect the relationship |
| 446 | // change. |
| 447 | unsigned OtherReg = Hint.second; |
| 448 | Hint = MRI->getRegAllocationHint(OtherReg); |
| 449 | if (Hint.second == Reg) |
| 450 | // Make sure the pair has not already divorced. |
| 451 | MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); |
| 452 | } |
| 453 | } |
| 454 | |
| 455 | /// hasFP - Return true if the specified function should have a dedicated frame |
| 456 | /// pointer register. This is true if the function has variable sized allocas |
| 457 | /// or if frame pointer elimination is disabled. |
| 458 | /// |
| 459 | bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const { |
| 460 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 461 | return (NoFramePointerElim || |
| 462 | MFI->hasVarSizedObjects() || |
| 463 | MFI->isFrameAddressTaken()); |
| 464 | } |
| 465 | |
| 466 | static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) { |
| 467 | const MachineFrameInfo *FFI = MF.getFrameInfo(); |
| 468 | int Offset = 0; |
| 469 | for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { |
| 470 | int FixedOff = -FFI->getObjectOffset(i); |
| 471 | if (FixedOff > Offset) Offset = FixedOff; |
| 472 | } |
| 473 | for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { |
| 474 | if (FFI->isDeadObjectIndex(i)) |
| 475 | continue; |
| 476 | Offset += FFI->getObjectSize(i); |
| 477 | unsigned Align = FFI->getObjectAlignment(i); |
| 478 | // Adjust to alignment boundary |
| 479 | Offset = (Offset+Align-1)/Align*Align; |
| 480 | } |
| 481 | return (unsigned)Offset; |
| 482 | } |
| 483 | |
| 484 | void |
| 485 | ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, |
| 486 | RegScavenger *RS) const { |
| 487 | // This tells PEI to spill the FP as if it is any other callee-save register |
| 488 | // to take advantage the eliminateFrameIndex machinery. This also ensures it |
| 489 | // is spilled in the order specified by getCalleeSavedRegs() to make it easier |
| 490 | // to combine multiple loads / stores. |
| 491 | bool CanEliminateFrame = true; |
| 492 | bool CS1Spilled = false; |
| 493 | bool LRSpilled = false; |
| 494 | unsigned NumGPRSpills = 0; |
| 495 | SmallVector<unsigned, 4> UnspilledCS1GPRs; |
| 496 | SmallVector<unsigned, 4> UnspilledCS2GPRs; |
| 497 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 498 | |
| 499 | // Don't spill FP if the frame can be eliminated. This is determined |
| 500 | // by scanning the callee-save registers to see if any is used. |
| 501 | const unsigned *CSRegs = getCalleeSavedRegs(); |
| 502 | const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses(); |
| 503 | for (unsigned i = 0; CSRegs[i]; ++i) { |
| 504 | unsigned Reg = CSRegs[i]; |
| 505 | bool Spilled = false; |
| 506 | if (MF.getRegInfo().isPhysRegUsed(Reg)) { |
| 507 | AFI->setCSRegisterIsSpilled(Reg); |
| 508 | Spilled = true; |
| 509 | CanEliminateFrame = false; |
| 510 | } else { |
| 511 | // Check alias registers too. |
| 512 | for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) { |
| 513 | if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { |
| 514 | Spilled = true; |
| 515 | CanEliminateFrame = false; |
| 516 | } |
| 517 | } |
| 518 | } |
| 519 | |
| 520 | if (CSRegClasses[i] == &ARM::GPRRegClass) { |
| 521 | if (Spilled) { |
| 522 | NumGPRSpills++; |
| 523 | |
| 524 | if (!STI.isTargetDarwin()) { |
| 525 | if (Reg == ARM::LR) |
| 526 | LRSpilled = true; |
| 527 | CS1Spilled = true; |
| 528 | continue; |
| 529 | } |
| 530 | |
| 531 | // Keep track if LR and any of R4, R5, R6, and R7 is spilled. |
| 532 | switch (Reg) { |
| 533 | case ARM::LR: |
| 534 | LRSpilled = true; |
| 535 | // Fallthrough |
| 536 | case ARM::R4: |
| 537 | case ARM::R5: |
| 538 | case ARM::R6: |
| 539 | case ARM::R7: |
| 540 | CS1Spilled = true; |
| 541 | break; |
| 542 | default: |
| 543 | break; |
| 544 | } |
| 545 | } else { |
| 546 | if (!STI.isTargetDarwin()) { |
| 547 | UnspilledCS1GPRs.push_back(Reg); |
| 548 | continue; |
| 549 | } |
| 550 | |
| 551 | switch (Reg) { |
| 552 | case ARM::R4: |
| 553 | case ARM::R5: |
| 554 | case ARM::R6: |
| 555 | case ARM::R7: |
| 556 | case ARM::LR: |
| 557 | UnspilledCS1GPRs.push_back(Reg); |
| 558 | break; |
| 559 | default: |
| 560 | UnspilledCS2GPRs.push_back(Reg); |
| 561 | break; |
| 562 | } |
| 563 | } |
| 564 | } |
| 565 | } |
| 566 | |
| 567 | bool ForceLRSpill = false; |
| 568 | if (!LRSpilled && AFI->isThumbFunction()) { |
| 569 | unsigned FnSize = TII.GetFunctionSizeInBytes(MF); |
| 570 | // Force LR to be spilled if the Thumb function size is > 2048. This enables |
| 571 | // use of BL to implement far jump. If it turns out that it's not needed |
| 572 | // then the branch fix up path will undo it. |
| 573 | if (FnSize >= (1 << 11)) { |
| 574 | CanEliminateFrame = false; |
| 575 | ForceLRSpill = true; |
| 576 | } |
| 577 | } |
| 578 | |
| 579 | bool ExtraCSSpill = false; |
| 580 | if (!CanEliminateFrame || hasFP(MF)) { |
| 581 | AFI->setHasStackFrame(true); |
| 582 | |
| 583 | // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. |
| 584 | // Spill LR as well so we can fold BX_RET to the registers restore (LDM). |
| 585 | if (!LRSpilled && CS1Spilled) { |
| 586 | MF.getRegInfo().setPhysRegUsed(ARM::LR); |
| 587 | AFI->setCSRegisterIsSpilled(ARM::LR); |
| 588 | NumGPRSpills++; |
| 589 | UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), |
| 590 | UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); |
| 591 | ForceLRSpill = false; |
| 592 | ExtraCSSpill = true; |
| 593 | } |
| 594 | |
| 595 | // Darwin ABI requires FP to point to the stack slot that contains the |
| 596 | // previous FP. |
| 597 | if (STI.isTargetDarwin() || hasFP(MF)) { |
| 598 | MF.getRegInfo().setPhysRegUsed(FramePtr); |
| 599 | NumGPRSpills++; |
| 600 | } |
| 601 | |
| 602 | // If stack and double are 8-byte aligned and we are spilling an odd number |
| 603 | // of GPRs. Spill one extra callee save GPR so we won't have to pad between |
| 604 | // the integer and double callee save areas. |
| 605 | unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 606 | if (TargetAlign == 8 && (NumGPRSpills & 1)) { |
| 607 | if (CS1Spilled && !UnspilledCS1GPRs.empty()) { |
| 608 | for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { |
| 609 | unsigned Reg = UnspilledCS1GPRs[i]; |
| 610 | // Don't spiil high register if the function is thumb |
| 611 | if (!AFI->isThumbFunction() || |
| 612 | isARMLowRegister(Reg) || Reg == ARM::LR) { |
| 613 | MF.getRegInfo().setPhysRegUsed(Reg); |
| 614 | AFI->setCSRegisterIsSpilled(Reg); |
| 615 | if (!isReservedReg(MF, Reg)) |
| 616 | ExtraCSSpill = true; |
| 617 | break; |
| 618 | } |
| 619 | } |
| 620 | } else if (!UnspilledCS2GPRs.empty() && |
| 621 | !AFI->isThumbFunction()) { |
| 622 | unsigned Reg = UnspilledCS2GPRs.front(); |
| 623 | MF.getRegInfo().setPhysRegUsed(Reg); |
| 624 | AFI->setCSRegisterIsSpilled(Reg); |
| 625 | if (!isReservedReg(MF, Reg)) |
| 626 | ExtraCSSpill = true; |
| 627 | } |
| 628 | } |
| 629 | |
| 630 | // Estimate if we might need to scavenge a register at some point in order |
| 631 | // to materialize a stack offset. If so, either spill one additional |
| 632 | // callee-saved register or reserve a special spill slot to facilitate |
| 633 | // register scavenging. |
| 634 | if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) { |
| 635 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 636 | unsigned Size = estimateStackSize(MF, MFI); |
| 637 | unsigned Limit = (1 << 12) - 1; |
| 638 | for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB) |
| 639 | for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) { |
| 640 | for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) |
| 641 | if (I->getOperand(i).isFI()) { |
| 642 | unsigned Opcode = I->getOpcode(); |
| 643 | const TargetInstrDesc &Desc = TII.get(Opcode); |
| 644 | unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); |
| 645 | if (AddrMode == ARMII::AddrMode3) { |
| 646 | Limit = (1 << 8) - 1; |
| 647 | goto DoneEstimating; |
| 648 | } else if (AddrMode == ARMII::AddrMode5) { |
| 649 | unsigned ThisLimit = ((1 << 8) - 1) * 4; |
| 650 | if (ThisLimit < Limit) |
| 651 | Limit = ThisLimit; |
| 652 | } |
| 653 | } |
| 654 | } |
| 655 | DoneEstimating: |
| 656 | if (Size >= Limit) { |
| 657 | // If any non-reserved CS register isn't spilled, just spill one or two |
| 658 | // extra. That should take care of it! |
| 659 | unsigned NumExtras = TargetAlign / 4; |
| 660 | SmallVector<unsigned, 2> Extras; |
| 661 | while (NumExtras && !UnspilledCS1GPRs.empty()) { |
| 662 | unsigned Reg = UnspilledCS1GPRs.back(); |
| 663 | UnspilledCS1GPRs.pop_back(); |
| 664 | if (!isReservedReg(MF, Reg)) { |
| 665 | Extras.push_back(Reg); |
| 666 | NumExtras--; |
| 667 | } |
| 668 | } |
| 669 | while (NumExtras && !UnspilledCS2GPRs.empty()) { |
| 670 | unsigned Reg = UnspilledCS2GPRs.back(); |
| 671 | UnspilledCS2GPRs.pop_back(); |
| 672 | if (!isReservedReg(MF, Reg)) { |
| 673 | Extras.push_back(Reg); |
| 674 | NumExtras--; |
| 675 | } |
| 676 | } |
| 677 | if (Extras.size() && NumExtras == 0) { |
| 678 | for (unsigned i = 0, e = Extras.size(); i != e; ++i) { |
| 679 | MF.getRegInfo().setPhysRegUsed(Extras[i]); |
| 680 | AFI->setCSRegisterIsSpilled(Extras[i]); |
| 681 | } |
| 682 | } else { |
| 683 | // Reserve a slot closest to SP or frame pointer. |
| 684 | const TargetRegisterClass *RC = &ARM::GPRRegClass; |
| 685 | RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), |
| 686 | RC->getAlignment())); |
| 687 | } |
| 688 | } |
| 689 | } |
| 690 | } |
| 691 | |
| 692 | if (ForceLRSpill) { |
| 693 | MF.getRegInfo().setPhysRegUsed(ARM::LR); |
| 694 | AFI->setCSRegisterIsSpilled(ARM::LR); |
| 695 | AFI->setLRIsSpilledForFarJump(true); |
| 696 | } |
| 697 | } |
| 698 | |
| 699 | unsigned ARMBaseRegisterInfo::getRARegister() const { |
| 700 | return ARM::LR; |
| 701 | } |
| 702 | |
| 703 | unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const { |
| 704 | if (STI.isTargetDarwin() || hasFP(MF)) |
| 705 | return FramePtr; |
| 706 | return ARM::SP; |
| 707 | } |
| 708 | |
| 709 | unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { |
| 710 | assert(0 && "What is the exception register"); |
| 711 | return 0; |
| 712 | } |
| 713 | |
| 714 | unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { |
| 715 | assert(0 && "What is the exception handler register"); |
| 716 | return 0; |
| 717 | } |
| 718 | |
| 719 | int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { |
| 720 | return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); |
| 721 | } |
| 722 | |
| 723 | unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, |
| 724 | const MachineFunction &MF) const { |
| 725 | switch (Reg) { |
| 726 | default: break; |
| 727 | // Return 0 if either register of the pair is a special register. |
| 728 | // So no R12, etc. |
| 729 | case ARM::R1: |
| 730 | return ARM::R0; |
| 731 | case ARM::R3: |
| 732 | // FIXME! |
| 733 | return STI.isThumb() ? 0 : ARM::R2; |
| 734 | case ARM::R5: |
| 735 | return ARM::R4; |
| 736 | case ARM::R7: |
| 737 | return isReservedReg(MF, ARM::R7) ? 0 : ARM::R6; |
| 738 | case ARM::R9: |
| 739 | return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; |
| 740 | case ARM::R11: |
| 741 | return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; |
| 742 | |
| 743 | case ARM::S1: |
| 744 | return ARM::S0; |
| 745 | case ARM::S3: |
| 746 | return ARM::S2; |
| 747 | case ARM::S5: |
| 748 | return ARM::S4; |
| 749 | case ARM::S7: |
| 750 | return ARM::S6; |
| 751 | case ARM::S9: |
| 752 | return ARM::S8; |
| 753 | case ARM::S11: |
| 754 | return ARM::S10; |
| 755 | case ARM::S13: |
| 756 | return ARM::S12; |
| 757 | case ARM::S15: |
| 758 | return ARM::S14; |
| 759 | case ARM::S17: |
| 760 | return ARM::S16; |
| 761 | case ARM::S19: |
| 762 | return ARM::S18; |
| 763 | case ARM::S21: |
| 764 | return ARM::S20; |
| 765 | case ARM::S23: |
| 766 | return ARM::S22; |
| 767 | case ARM::S25: |
| 768 | return ARM::S24; |
| 769 | case ARM::S27: |
| 770 | return ARM::S26; |
| 771 | case ARM::S29: |
| 772 | return ARM::S28; |
| 773 | case ARM::S31: |
| 774 | return ARM::S30; |
| 775 | |
| 776 | case ARM::D1: |
| 777 | return ARM::D0; |
| 778 | case ARM::D3: |
| 779 | return ARM::D2; |
| 780 | case ARM::D5: |
| 781 | return ARM::D4; |
| 782 | case ARM::D7: |
| 783 | return ARM::D6; |
| 784 | case ARM::D9: |
| 785 | return ARM::D8; |
| 786 | case ARM::D11: |
| 787 | return ARM::D10; |
| 788 | case ARM::D13: |
| 789 | return ARM::D12; |
| 790 | case ARM::D15: |
| 791 | return ARM::D14; |
| 792 | } |
| 793 | |
| 794 | return 0; |
| 795 | } |
| 796 | |
| 797 | unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, |
| 798 | const MachineFunction &MF) const { |
| 799 | switch (Reg) { |
| 800 | default: break; |
| 801 | // Return 0 if either register of the pair is a special register. |
| 802 | // So no R12, etc. |
| 803 | case ARM::R0: |
| 804 | return ARM::R1; |
| 805 | case ARM::R2: |
| 806 | // FIXME! |
| 807 | return STI.isThumb() ? 0 : ARM::R3; |
| 808 | case ARM::R4: |
| 809 | return ARM::R5; |
| 810 | case ARM::R6: |
| 811 | return isReservedReg(MF, ARM::R7) ? 0 : ARM::R7; |
| 812 | case ARM::R8: |
| 813 | return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; |
| 814 | case ARM::R10: |
| 815 | return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; |
| 816 | |
| 817 | case ARM::S0: |
| 818 | return ARM::S1; |
| 819 | case ARM::S2: |
| 820 | return ARM::S3; |
| 821 | case ARM::S4: |
| 822 | return ARM::S5; |
| 823 | case ARM::S6: |
| 824 | return ARM::S7; |
| 825 | case ARM::S8: |
| 826 | return ARM::S9; |
| 827 | case ARM::S10: |
| 828 | return ARM::S11; |
| 829 | case ARM::S12: |
| 830 | return ARM::S13; |
| 831 | case ARM::S14: |
| 832 | return ARM::S15; |
| 833 | case ARM::S16: |
| 834 | return ARM::S17; |
| 835 | case ARM::S18: |
| 836 | return ARM::S19; |
| 837 | case ARM::S20: |
| 838 | return ARM::S21; |
| 839 | case ARM::S22: |
| 840 | return ARM::S23; |
| 841 | case ARM::S24: |
| 842 | return ARM::S25; |
| 843 | case ARM::S26: |
| 844 | return ARM::S27; |
| 845 | case ARM::S28: |
| 846 | return ARM::S29; |
| 847 | case ARM::S30: |
| 848 | return ARM::S31; |
| 849 | |
| 850 | case ARM::D0: |
| 851 | return ARM::D1; |
| 852 | case ARM::D2: |
| 853 | return ARM::D3; |
| 854 | case ARM::D4: |
| 855 | return ARM::D5; |
| 856 | case ARM::D6: |
| 857 | return ARM::D7; |
| 858 | case ARM::D8: |
| 859 | return ARM::D9; |
| 860 | case ARM::D10: |
| 861 | return ARM::D11; |
| 862 | case ARM::D12: |
| 863 | return ARM::D13; |
| 864 | case ARM::D14: |
| 865 | return ARM::D15; |
| 866 | } |
| 867 | |
| 868 | return 0; |
| 869 | } |
| 870 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 871 | |
| 872 | static inline |
| 873 | const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { |
| 874 | return MIB.addImm((int64_t)ARMCC::AL).addReg(0); |
| 875 | } |
| 876 | |
| 877 | static inline |
| 878 | const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { |
| 879 | return MIB.addReg(0); |
| 880 | } |
| 881 | |
| 882 | /// emitLoadConstPool - Emits a load from constpool to materialize the |
| 883 | /// specified immediate. |
| 884 | void ARMBaseRegisterInfo:: |
| 885 | emitLoadConstPool(MachineBasicBlock &MBB, |
| 886 | MachineBasicBlock::iterator &MBBI, |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 887 | DebugLoc dl, |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 888 | unsigned DestReg, int Val, |
| 889 | ARMCC::CondCodes Pred, |
| 890 | unsigned PredReg) const { |
| 891 | MachineFunction &MF = *MBB.getParent(); |
| 892 | MachineConstantPool *ConstantPool = MF.getConstantPool(); |
| 893 | Constant *C = ConstantInt::get(Type::Int32Ty, Val); |
| 894 | unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); |
| 895 | |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 896 | BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp), DestReg) |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 897 | .addConstantPoolIndex(Idx) |
| 898 | .addReg(0).addImm(0).addImm(Pred).addReg(PredReg); |
| 899 | } |
| 900 | |
| 901 | bool ARMBaseRegisterInfo:: |
| 902 | requiresRegisterScavenging(const MachineFunction &MF) const { |
| 903 | return true; |
| 904 | } |
| 905 | |
| 906 | // hasReservedCallFrame - Under normal circumstances, when a frame pointer is |
| 907 | // not required, we reserve argument space for call sites in the function |
| 908 | // immediately on entry to the current function. This eliminates the need for |
| 909 | // add/sub sp brackets around call sites. Returns true if the call frame is |
| 910 | // included as part of the stack frame. |
| 911 | bool ARMBaseRegisterInfo:: |
| 912 | hasReservedCallFrame(MachineFunction &MF) const { |
| 913 | const MachineFrameInfo *FFI = MF.getFrameInfo(); |
| 914 | unsigned CFSize = FFI->getMaxCallFrameSize(); |
| 915 | // It's not always a good idea to include the call frame as part of the |
| 916 | // stack frame. ARM (especially Thumb) has small immediate offset to |
| 917 | // address the stack frame. So a large call frame can cause poor codegen |
| 918 | // and may even makes it impossible to scavenge a register. |
| 919 | if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 |
| 920 | return false; |
| 921 | |
| 922 | return !MF.getFrameInfo()->hasVarSizedObjects(); |
| 923 | } |
| 924 | |
| 925 | /// emitARMRegPlusImmediate - Emits a series of instructions to materialize |
| 926 | /// a destreg = basereg + immediate in ARM code. |
| 927 | static |
| 928 | void emitARMRegPlusImmediate(MachineBasicBlock &MBB, |
| 929 | MachineBasicBlock::iterator &MBBI, |
| 930 | unsigned DestReg, unsigned BaseReg, int NumBytes, |
| 931 | ARMCC::CondCodes Pred, unsigned PredReg, |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 932 | const ARMBaseInstrInfo &TII, |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 933 | DebugLoc dl) { |
| 934 | bool isSub = NumBytes < 0; |
| 935 | if (isSub) NumBytes = -NumBytes; |
| 936 | |
| 937 | while (NumBytes) { |
| 938 | unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); |
| 939 | unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); |
| 940 | assert(ThisVal && "Didn't extract field correctly"); |
| 941 | |
| 942 | // We will handle these bits from offset, clear them. |
| 943 | NumBytes &= ~ThisVal; |
| 944 | |
| 945 | // Get the properly encoded SOImmVal field. |
| 946 | int SOImmVal = ARM_AM::getSOImmVal(ThisVal); |
| 947 | assert(SOImmVal != -1 && "Bit extraction didn't work?"); |
| 948 | |
| 949 | // Build the new ADD / SUB. |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 950 | BuildMI(MBB, MBBI, dl, TII.get(TII.getOpcode(isSub ? ARMII::SUBri : ARMII::ADDri)), DestReg) |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 951 | .addReg(BaseReg, RegState::Kill).addImm(SOImmVal) |
| 952 | .addImm((unsigned)Pred).addReg(PredReg).addReg(0); |
| 953 | BaseReg = DestReg; |
| 954 | } |
| 955 | } |
| 956 | |
| 957 | static void |
| 958 | emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 959 | const ARMBaseInstrInfo &TII, DebugLoc dl, |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 960 | int NumBytes, |
| 961 | ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { |
| 962 | emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, |
| 963 | Pred, PredReg, TII, dl); |
| 964 | } |
| 965 | |
| 966 | void ARMBaseRegisterInfo:: |
| 967 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 968 | MachineBasicBlock::iterator I) const { |
| 969 | if (!hasReservedCallFrame(MF)) { |
| 970 | // If we have alloca, convert as follows: |
| 971 | // ADJCALLSTACKDOWN -> sub, sp, sp, amount |
| 972 | // ADJCALLSTACKUP -> add, sp, sp, amount |
| 973 | MachineInstr *Old = I; |
| 974 | DebugLoc dl = Old->getDebugLoc(); |
| 975 | unsigned Amount = Old->getOperand(0).getImm(); |
| 976 | if (Amount != 0) { |
| 977 | // We need to keep the stack aligned properly. To do this, we round the |
| 978 | // amount of space needed for the outgoing arguments up to the next |
| 979 | // alignment boundary. |
| 980 | unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); |
| 981 | Amount = (Amount+Align-1)/Align*Align; |
| 982 | |
| 983 | // Replace the pseudo instruction with a new instruction... |
| 984 | unsigned Opc = Old->getOpcode(); |
| 985 | ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm(); |
| 986 | if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { |
| 987 | // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. |
| 988 | unsigned PredReg = Old->getOperand(2).getReg(); |
| 989 | emitSPUpdate(MBB, I, TII, dl, -Amount, Pred, PredReg); |
| 990 | } else { |
| 991 | // Note: PredReg is operand 3 for ADJCALLSTACKUP. |
| 992 | unsigned PredReg = Old->getOperand(3).getReg(); |
| 993 | assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); |
| 994 | emitSPUpdate(MBB, I, TII, dl, Amount, Pred, PredReg); |
| 995 | } |
| 996 | } |
| 997 | } |
| 998 | MBB.erase(I); |
| 999 | } |
| 1000 | |
| 1001 | /// findScratchRegister - Find a 'free' ARM register. If register scavenger |
| 1002 | /// is not being used, R12 is available. Otherwise, try for a call-clobbered |
| 1003 | /// register first and then a spilled callee-saved register if that fails. |
| 1004 | static |
| 1005 | unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC, |
| 1006 | ARMFunctionInfo *AFI) { |
| 1007 | unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12; |
| 1008 | assert (!AFI->isThumbFunction()); |
| 1009 | if (Reg == 0) |
| 1010 | // Try a already spilled CS register. |
| 1011 | Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters()); |
| 1012 | |
| 1013 | return Reg; |
| 1014 | } |
| 1015 | |
| 1016 | void ARMBaseRegisterInfo:: |
| 1017 | eliminateFrameIndex(MachineBasicBlock::iterator II, |
| 1018 | int SPAdj, RegScavenger *RS) const{ |
| 1019 | unsigned i = 0; |
| 1020 | MachineInstr &MI = *II; |
| 1021 | MachineBasicBlock &MBB = *MI.getParent(); |
| 1022 | MachineFunction &MF = *MBB.getParent(); |
| 1023 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 1024 | DebugLoc dl = MI.getDebugLoc(); |
| 1025 | |
| 1026 | while (!MI.getOperand(i).isFI()) { |
| 1027 | ++i; |
| 1028 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 1029 | } |
| 1030 | |
| 1031 | unsigned FrameReg = ARM::SP; |
| 1032 | int FrameIndex = MI.getOperand(i).getIndex(); |
| 1033 | int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + |
| 1034 | MF.getFrameInfo()->getStackSize() + SPAdj; |
| 1035 | |
| 1036 | if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) |
| 1037 | Offset -= AFI->getGPRCalleeSavedArea1Offset(); |
| 1038 | else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) |
| 1039 | Offset -= AFI->getGPRCalleeSavedArea2Offset(); |
| 1040 | else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex)) |
| 1041 | Offset -= AFI->getDPRCalleeSavedAreaOffset(); |
| 1042 | else if (hasFP(MF)) { |
| 1043 | assert(SPAdj == 0 && "Unexpected"); |
| 1044 | // There is alloca()'s in this function, must reference off the frame |
| 1045 | // pointer instead. |
| 1046 | FrameReg = getFrameRegister(MF); |
| 1047 | Offset -= AFI->getFramePtrSpillOffset(); |
| 1048 | } |
| 1049 | |
| 1050 | unsigned Opcode = MI.getOpcode(); |
| 1051 | const TargetInstrDesc &Desc = MI.getDesc(); |
| 1052 | unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); |
| 1053 | bool isSub = false; |
| 1054 | |
| 1055 | // Memory operands in inline assembly always use AddrMode2. |
| 1056 | if (Opcode == ARM::INLINEASM) |
| 1057 | AddrMode = ARMII::AddrMode2; |
| 1058 | |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1059 | if (Opcode == getOpcode(ARMII::ADDri)) { |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1060 | Offset += MI.getOperand(i+1).getImm(); |
| 1061 | if (Offset == 0) { |
| 1062 | // Turn it into a move. |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1063 | MI.setDesc(TII.get(getOpcode(ARMII::MOVr))); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1064 | MI.getOperand(i).ChangeToRegister(FrameReg, false); |
| 1065 | MI.RemoveOperand(i+1); |
| 1066 | return; |
| 1067 | } else if (Offset < 0) { |
| 1068 | Offset = -Offset; |
| 1069 | isSub = true; |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1070 | MI.setDesc(TII.get(getOpcode(ARMII::SUBri))); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1071 | } |
| 1072 | |
| 1073 | // Common case: small offset, fits into instruction. |
| 1074 | int ImmedOffset = ARM_AM::getSOImmVal(Offset); |
| 1075 | if (ImmedOffset != -1) { |
| 1076 | // Replace the FrameIndex with sp / fp |
| 1077 | MI.getOperand(i).ChangeToRegister(FrameReg, false); |
| 1078 | MI.getOperand(i+1).ChangeToImmediate(ImmedOffset); |
| 1079 | return; |
| 1080 | } |
| 1081 | |
| 1082 | // Otherwise, we fallback to common code below to form the imm offset with |
| 1083 | // a sequence of ADDri instructions. First though, pull as much of the imm |
| 1084 | // into this ADDri as possible. |
| 1085 | unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); |
| 1086 | unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); |
| 1087 | |
| 1088 | // We will handle these bits from offset, clear them. |
| 1089 | Offset &= ~ThisImmVal; |
| 1090 | |
| 1091 | // Get the properly encoded SOImmVal field. |
| 1092 | int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal); |
| 1093 | assert(ThisSOImmVal != -1 && "Bit extraction didn't work?"); |
| 1094 | MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal); |
| 1095 | } else { |
| 1096 | unsigned ImmIdx = 0; |
| 1097 | int InstrOffs = 0; |
| 1098 | unsigned NumBits = 0; |
| 1099 | unsigned Scale = 1; |
| 1100 | switch (AddrMode) { |
| 1101 | case ARMII::AddrMode2: { |
| 1102 | ImmIdx = i+2; |
| 1103 | InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); |
| 1104 | if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 1105 | InstrOffs *= -1; |
| 1106 | NumBits = 12; |
| 1107 | break; |
| 1108 | } |
| 1109 | case ARMII::AddrMode3: { |
| 1110 | ImmIdx = i+2; |
| 1111 | InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); |
| 1112 | if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 1113 | InstrOffs *= -1; |
| 1114 | NumBits = 8; |
| 1115 | break; |
| 1116 | } |
| 1117 | case ARMII::AddrMode5: { |
| 1118 | ImmIdx = i+1; |
| 1119 | InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); |
| 1120 | if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 1121 | InstrOffs *= -1; |
| 1122 | NumBits = 8; |
| 1123 | Scale = 4; |
| 1124 | break; |
| 1125 | } |
| 1126 | default: |
| 1127 | LLVM_UNREACHABLE("Unsupported addressing mode!"); |
| 1128 | break; |
| 1129 | } |
| 1130 | |
| 1131 | Offset += InstrOffs * Scale; |
| 1132 | assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); |
| 1133 | if (Offset < 0) { |
| 1134 | Offset = -Offset; |
| 1135 | isSub = true; |
| 1136 | } |
| 1137 | |
| 1138 | // Common case: small offset, fits into instruction. |
| 1139 | MachineOperand &ImmOp = MI.getOperand(ImmIdx); |
| 1140 | int ImmedOffset = Offset / Scale; |
| 1141 | unsigned Mask = (1 << NumBits) - 1; |
| 1142 | if ((unsigned)Offset <= Mask * Scale) { |
| 1143 | // Replace the FrameIndex with sp |
| 1144 | MI.getOperand(i).ChangeToRegister(FrameReg, false); |
| 1145 | if (isSub) |
| 1146 | ImmedOffset |= 1 << NumBits; |
| 1147 | ImmOp.ChangeToImmediate(ImmedOffset); |
| 1148 | return; |
| 1149 | } |
| 1150 | |
| 1151 | // Otherwise, it didn't fit. Pull in what we can to simplify the immed. |
| 1152 | ImmedOffset = ImmedOffset & Mask; |
| 1153 | if (isSub) |
| 1154 | ImmedOffset |= 1 << NumBits; |
| 1155 | ImmOp.ChangeToImmediate(ImmedOffset); |
| 1156 | Offset &= ~(Mask*Scale); |
| 1157 | } |
| 1158 | |
| 1159 | // If we get here, the immediate doesn't fit into the instruction. We folded |
| 1160 | // as much as possible above, handle the rest, providing a register that is |
| 1161 | // SP+LargeImm. |
| 1162 | assert(Offset && "This code isn't needed if offset already handled!"); |
| 1163 | |
| 1164 | // Insert a set of r12 with the full address: r12 = sp + offset |
| 1165 | // If the offset we have is too large to fit into the instruction, we need |
| 1166 | // to form it with a series of ADDri's. Do this by taking 8-bit chunks |
| 1167 | // out of 'Offset'. |
| 1168 | unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI); |
| 1169 | if (ScratchReg == 0) |
| 1170 | // No register is "free". Scavenge a register. |
| 1171 | ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj); |
| 1172 | int PIdx = MI.findFirstPredOperandIdx(); |
| 1173 | ARMCC::CondCodes Pred = (PIdx == -1) |
| 1174 | ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); |
| 1175 | unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); |
| 1176 | emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg, |
| 1177 | isSub ? -Offset : Offset, Pred, PredReg, TII, dl); |
| 1178 | MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); |
| 1179 | } |
| 1180 | |
| 1181 | /// Move iterator pass the next bunch of callee save load / store ops for |
| 1182 | /// the particular spill area (1: integer area 1, 2: integer area 2, |
| 1183 | /// 3: fp area, 0: don't care). |
| 1184 | static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, |
| 1185 | MachineBasicBlock::iterator &MBBI, |
| 1186 | int Opc, unsigned Area, |
| 1187 | const ARMSubtarget &STI) { |
| 1188 | while (MBBI != MBB.end() && |
| 1189 | MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) { |
| 1190 | if (Area != 0) { |
| 1191 | bool Done = false; |
| 1192 | unsigned Category = 0; |
| 1193 | switch (MBBI->getOperand(0).getReg()) { |
| 1194 | case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: |
| 1195 | case ARM::LR: |
| 1196 | Category = 1; |
| 1197 | break; |
| 1198 | case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: |
| 1199 | Category = STI.isTargetDarwin() ? 2 : 1; |
| 1200 | break; |
| 1201 | case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: |
| 1202 | case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: |
| 1203 | Category = 3; |
| 1204 | break; |
| 1205 | default: |
| 1206 | Done = true; |
| 1207 | break; |
| 1208 | } |
| 1209 | if (Done || Category != Area) |
| 1210 | break; |
| 1211 | } |
| 1212 | |
| 1213 | ++MBBI; |
| 1214 | } |
| 1215 | } |
| 1216 | |
| 1217 | void ARMBaseRegisterInfo:: |
| 1218 | emitPrologue(MachineFunction &MF) const { |
| 1219 | MachineBasicBlock &MBB = MF.front(); |
| 1220 | MachineBasicBlock::iterator MBBI = MBB.begin(); |
| 1221 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1222 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 1223 | unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); |
| 1224 | unsigned NumBytes = MFI->getStackSize(); |
| 1225 | const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); |
| 1226 | DebugLoc dl = (MBBI != MBB.end() ? |
| 1227 | MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); |
| 1228 | |
| 1229 | // Determine the sizes of each callee-save spill areas and record which frame |
| 1230 | // belongs to which callee-save spill areas. |
| 1231 | unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; |
| 1232 | int FramePtrSpillFI = 0; |
| 1233 | |
| 1234 | if (VARegSaveSize) |
| 1235 | emitSPUpdate(MBB, MBBI, TII, dl, -VARegSaveSize); |
| 1236 | |
| 1237 | if (!AFI->hasStackFrame()) { |
| 1238 | if (NumBytes != 0) |
| 1239 | emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes); |
| 1240 | return; |
| 1241 | } |
| 1242 | |
| 1243 | for (unsigned i = 0, e = CSI.size(); i != e; ++i) { |
| 1244 | unsigned Reg = CSI[i].getReg(); |
| 1245 | int FI = CSI[i].getFrameIdx(); |
| 1246 | switch (Reg) { |
| 1247 | case ARM::R4: |
| 1248 | case ARM::R5: |
| 1249 | case ARM::R6: |
| 1250 | case ARM::R7: |
| 1251 | case ARM::LR: |
| 1252 | if (Reg == FramePtr) |
| 1253 | FramePtrSpillFI = FI; |
| 1254 | AFI->addGPRCalleeSavedArea1Frame(FI); |
| 1255 | GPRCS1Size += 4; |
| 1256 | break; |
| 1257 | case ARM::R8: |
| 1258 | case ARM::R9: |
| 1259 | case ARM::R10: |
| 1260 | case ARM::R11: |
| 1261 | if (Reg == FramePtr) |
| 1262 | FramePtrSpillFI = FI; |
| 1263 | if (STI.isTargetDarwin()) { |
| 1264 | AFI->addGPRCalleeSavedArea2Frame(FI); |
| 1265 | GPRCS2Size += 4; |
| 1266 | } else { |
| 1267 | AFI->addGPRCalleeSavedArea1Frame(FI); |
| 1268 | GPRCS1Size += 4; |
| 1269 | } |
| 1270 | break; |
| 1271 | default: |
| 1272 | AFI->addDPRCalleeSavedAreaFrame(FI); |
| 1273 | DPRCSSize += 8; |
| 1274 | } |
| 1275 | } |
| 1276 | |
| 1277 | // Build the new SUBri to adjust SP for integer callee-save spill area 1. |
| 1278 | emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size); |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1279 | movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STR), 1, STI); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1280 | |
| 1281 | // Darwin ABI requires FP to point to the stack slot that contains the |
| 1282 | // previous FP. |
| 1283 | if (STI.isTargetDarwin() || hasFP(MF)) { |
| 1284 | MachineInstrBuilder MIB = |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1285 | BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::ADDri)), FramePtr) |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1286 | .addFrameIndex(FramePtrSpillFI).addImm(0); |
| 1287 | AddDefaultCC(AddDefaultPred(MIB)); |
| 1288 | } |
| 1289 | |
| 1290 | // Build the new SUBri to adjust SP for integer callee-save spill area 2. |
| 1291 | emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size); |
| 1292 | |
| 1293 | // Build the new SUBri to adjust SP for FP callee-save spill area. |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1294 | movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::STR), 2, STI); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1295 | emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize); |
| 1296 | |
| 1297 | // Determine starting offsets of spill areas. |
| 1298 | unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); |
| 1299 | unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; |
| 1300 | unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; |
| 1301 | AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); |
| 1302 | AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); |
| 1303 | AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); |
| 1304 | AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); |
| 1305 | |
| 1306 | NumBytes = DPRCSOffset; |
| 1307 | if (NumBytes) { |
| 1308 | // Insert it after all the callee-save spills. |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1309 | movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FSTD), 3, STI); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1310 | emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes); |
| 1311 | } |
| 1312 | |
| 1313 | if (STI.isTargetELF() && hasFP(MF)) { |
| 1314 | MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - |
| 1315 | AFI->getFramePtrSpillOffset()); |
| 1316 | } |
| 1317 | |
| 1318 | AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); |
| 1319 | AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); |
| 1320 | AFI->setDPRCalleeSavedAreaSize(DPRCSSize); |
| 1321 | } |
| 1322 | |
| 1323 | static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { |
| 1324 | for (unsigned i = 0; CSRegs[i]; ++i) |
| 1325 | if (Reg == CSRegs[i]) |
| 1326 | return true; |
| 1327 | return false; |
| 1328 | } |
| 1329 | |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1330 | static bool isCSRestore(MachineInstr *MI, |
| 1331 | const ARMBaseInstrInfo &TII, |
| 1332 | const unsigned *CSRegs) { |
| 1333 | return ((MI->getOpcode() == (int)TII.getOpcode(ARMII::FLDD) || |
| 1334 | MI->getOpcode() == (int)TII.getOpcode(ARMII::LDR)) && |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1335 | MI->getOperand(1).isFI() && |
| 1336 | isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)); |
| 1337 | } |
| 1338 | |
| 1339 | void ARMBaseRegisterInfo:: |
| 1340 | emitEpilogue(MachineFunction &MF, |
| 1341 | MachineBasicBlock &MBB) const { |
| 1342 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1343 | assert(MBBI->getOpcode() == (int)getOpcode(ARMII::BX_RET) && |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1344 | "Can only insert epilog into returning blocks"); |
| 1345 | DebugLoc dl = MBBI->getDebugLoc(); |
| 1346 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 1347 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 1348 | unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); |
| 1349 | int NumBytes = (int)MFI->getStackSize(); |
| 1350 | |
| 1351 | if (!AFI->hasStackFrame()) { |
| 1352 | if (NumBytes != 0) |
| 1353 | emitSPUpdate(MBB, MBBI, TII, dl, NumBytes); |
| 1354 | } else { |
| 1355 | // Unwind MBBI to point to first LDR / FLDD. |
| 1356 | const unsigned *CSRegs = getCalleeSavedRegs(); |
| 1357 | if (MBBI != MBB.begin()) { |
| 1358 | do |
| 1359 | --MBBI; |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1360 | while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); |
| 1361 | if (!isCSRestore(MBBI, TII, CSRegs)) |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1362 | ++MBBI; |
| 1363 | } |
| 1364 | |
| 1365 | // Move SP to start of FP callee save spill area. |
| 1366 | NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + |
| 1367 | AFI->getGPRCalleeSavedArea2Size() + |
| 1368 | AFI->getDPRCalleeSavedAreaSize()); |
| 1369 | |
| 1370 | // Darwin ABI requires FP to point to the stack slot that contains the |
| 1371 | // previous FP. |
| 1372 | if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) { |
| 1373 | NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; |
| 1374 | // Reset SP based on frame pointer only if the stack frame extends beyond |
| 1375 | // frame pointer stack slot or target is ELF and the function has FP. |
| 1376 | if (AFI->getGPRCalleeSavedArea2Size() || |
| 1377 | AFI->getDPRCalleeSavedAreaSize() || |
| 1378 | AFI->getDPRCalleeSavedAreaOffset()|| |
| 1379 | hasFP(MF)) { |
| 1380 | if (NumBytes) |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1381 | BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::SUBri)), ARM::SP).addReg(FramePtr) |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1382 | .addImm(NumBytes) |
| 1383 | .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); |
| 1384 | else |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1385 | BuildMI(MBB, MBBI, dl, TII.get(getOpcode(ARMII::MOVr)), ARM::SP).addReg(FramePtr) |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1386 | .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); |
| 1387 | } |
| 1388 | } else if (NumBytes) { |
| 1389 | emitSPUpdate(MBB, MBBI, TII, dl, NumBytes); |
| 1390 | } |
| 1391 | |
| 1392 | // Move SP to start of integer callee save spill area 2. |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1393 | movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::FLDD), 3, STI); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1394 | emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize()); |
| 1395 | |
| 1396 | // Move SP to start of integer callee save spill area 1. |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1397 | movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDR), 2, STI); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1398 | emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size()); |
| 1399 | |
| 1400 | // Move SP to SP upon entry to the function. |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 1401 | movePastCSLoadStoreOps(MBB, MBBI, getOpcode(ARMII::LDR), 1, STI); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1402 | emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size()); |
| 1403 | } |
| 1404 | |
| 1405 | if (VARegSaveSize) |
| 1406 | emitSPUpdate(MBB, MBBI, TII, dl, VARegSaveSize); |
| 1407 | |
| 1408 | } |
| 1409 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 1410 | #include "ARMGenRegisterInfo.inc" |