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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / dd950096b96a1535976b2d0db3bd90153c0be82a / . / lib / Target / CellSPU / SPUCallingConv.td
blob: 5213e424523361a78527d80396088ee17d10e044 [file] [log] [blame]
Scott Michel266bc8f2007-12-04 22:23:35 +0000[diff] [blame]1//===- SPUCallingConv.td - Calling Conventions for CellSPU ------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Scott Michel266bc8f2007-12-04 22:23:35 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This describes the calling conventions for the STI Cell SPU architecture.
11//
12//===----------------------------------------------------------------------===//
13
14/// CCIfSubtarget - Match if the current subtarget has a feature F.
15class CCIfSubtarget<string F, CCAction A>
16 : CCIf<!strconcat("State.getTarget().getSubtarget<PPCSubtarget>().", F), A>;
17
18//===----------------------------------------------------------------------===//
19// Return Value Calling Convention
20//===----------------------------------------------------------------------===//
21
22// Return-value convention for Cell SPU: Everything can be passed back via $3:
23def RetCC_SPU : CallingConv<[
Scott Micheldd950092009-01-06 03:36:14 +0000[diff] [blame^]24 CCIfType<[i8], CCAssignToReg<[R3]>>,
25 CCIfType<[i16], CCAssignToReg<[R3]>>,
26 CCIfType<[i32], CCAssignToReg<[R3]>>,
27 CCIfType<[i64], CCAssignToReg<[R3]>>,
28 CCIfType<[i128], CCAssignToReg<[R3]>>,
Scott Michel266bc8f2007-12-04 22:23:35 +0000[diff] [blame]29 CCIfType<[f32, f64], CCAssignToReg<[R3]>>,
30 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToReg<[R3]>>
31]>;
32
33
34//===----------------------------------------------------------------------===//
35// CellSPU Argument Calling Conventions
Scott Michelb30e8f62008-12-02 19:53:53 +0000[diff] [blame]36// (note: this isn't used, but presumably should be at some point when other
37// targets do.)
Scott Michel266bc8f2007-12-04 22:23:35 +0000[diff] [blame]38//===----------------------------------------------------------------------===//
39/*
40def CC_SPU : CallingConv<[
Scott Michelb30e8f62008-12-02 19:53:53 +0000[diff] [blame]41 CCIfType<[i8], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
42 R12, R13, R14, R15, R16, R17, R18, R19, R20,
43 R21, R22, R23, R24, R25, R26, R27, R28, R29,
44 R30, R31, R32, R33, R34, R35, R36, R37, R38,
45 R39, R40, R41, R42, R43, R44, R45, R46, R47,
46 R48, R49, R50, R51, R52, R53, R54, R55, R56,
47 R57, R58, R59, R60, R61, R62, R63, R64, R65,
48 R66, R67, R68, R69, R70, R71, R72, R73, R74,
49 R75, R76, R77, R78, R79]>>,
50 CCIfType<[i16], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
51 R12, R13, R14, R15, R16, R17, R18, R19, R20,
52 R21, R22, R23, R24, R25, R26, R27, R28, R29,
53 R30, R31, R32, R33, R34, R35, R36, R37, R38,
54 R39, R40, R41, R42, R43, R44, R45, R46, R47,
55 R48, R49, R50, R51, R52, R53, R54, R55, R56,
56 R57, R58, R59, R60, R61, R62, R63, R64, R65,
57 R66, R67, R68, R69, R70, R71, R72, R73, R74,
58 R75, R76, R77, R78, R79]>>,
59 CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
60 R12, R13, R14, R15, R16, R17, R18, R19, R20,
61 R21, R22, R23, R24, R25, R26, R27, R28, R29,
62 R30, R31, R32, R33, R34, R35, R36, R37, R38,
63 R39, R40, R41, R42, R43, R44, R45, R46, R47,
64 R48, R49, R50, R51, R52, R53, R54, R55, R56,
65 R57, R58, R59, R60, R61, R62, R63, R64, R65,
66 R66, R67, R68, R69, R70, R71, R72, R73, R74,
67 R75, R76, R77, R78, R79]>>,
68 CCIfType<[f32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
69 R12, R13, R14, R15, R16, R17, R18, R19, R20,
70 R21, R22, R23, R24, R25, R26, R27, R28, R29,
71 R30, R31, R32, R33, R34, R35, R36, R37, R38,
72 R39, R40, R41, R42, R43, R44, R45, R46, R47,
73 R48, R49, R50, R51, R52, R53, R54, R55, R56,
74 R57, R58, R59, R60, R61, R62, R63, R64, R65,
75 R66, R67, R68, R69, R70, R71, R72, R73, R74,
76 R75, R76, R77, R78, R79]>>,
77 CCIfType<[i64], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
78 R12, R13, R14, R15, R16, R17, R18, R19, R20,
79 R21, R22, R23, R24, R25, R26, R27, R28, R29,
80 R30, R31, R32, R33, R34, R35, R36, R37, R38,
81 R39, R40, R41, R42, R43, R44, R45, R46, R47,
82 R48, R49, R50, R51, R52, R53, R54, R55, R56,
83 R57, R58, R59, R60, R61, R62, R63, R64, R65,
84 R66, R67, R68, R69, R70, R71, R72, R73, R74,
85 R75, R76, R77, R78, R79]>>,
86 CCIfType<[f64], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
87 R12, R13, R14, R15, R16, R17, R18, R19, R20,
88 R21, R22, R23, R24, R25, R26, R27, R28, R29,
89 R30, R31, R32, R33, R34, R35, R36, R37, R38,
90 R39, R40, R41, R42, R43, R44, R45, R46, R47,
91 R48, R49, R50, R51, R52, R53, R54, R55, R56,
92 R57, R58, R59, R60, R61, R62, R63, R64, R65,
93 R66, R67, R68, R69, R70, R71, R72, R73, R74,
94 R75, R76, R77, R78, R79]>>,
95 CCIfType<[v16i8, v8i16, v4i32, v4f32, v2i64, v2f64],
96 CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10, R11,
97 R12, R13, R14, R15, R16, R17, R18, R19, R20,
98 R21, R22, R23, R24, R25, R26, R27, R28, R29,
99 R30, R31, R32, R33, R34, R35, R36, R37, R38,
100 R39, R40, R41, R42, R43, R44, R45, R46, R47,
101 R48, R49, R50, R51, R52, R53, R54, R55, R56,
102 R57, R58, R59, R60, R61, R62, R63, R64, R65,
103 R66, R67, R68, R69, R70, R71, R72, R73, R74,
104 R75, R76, R77, R78, R79]>>,
Scott Michel266bc8f2007-12-04 22:23:35 +0000[diff] [blame]105
Scott Michel266bc8f2007-12-04 22:23:35 +0000[diff] [blame]106 // Integer/FP values get stored in stack slots that are 8 bytes in size and
107 // 8-byte aligned if there are no more registers to hold them.
108 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
109
110 // Vectors get 16-byte stack slots that are 16-byte aligned.
111 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
Scott Michelb30e8f62008-12-02 19:53:53 +0000[diff] [blame]112 CCAssignToStack<16, 16>>
Scott Michel266bc8f2007-12-04 22:23:35 +0000[diff] [blame]113]>;
Scott Michelb30e8f62008-12-02 19:53:53 +0000[diff] [blame]114*/