| Chad Rosier | e07cd5e | 2011-11-02 18:08:25 +0000 | [diff] [blame^] | 1 | ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM |
| 2 | ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB |
| 3 | |
| 4 | define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind { |
| 5 | entry: |
| 6 | ; ARM: icmp_i16_unsigned |
| 7 | ; ARM: uxth r0, r0 |
| 8 | ; ARM: uxth r1, r1 |
| 9 | ; ARM: cmp r0, r1 |
| 10 | ; THUMB: icmp_i16_unsigned |
| 11 | ; THUMB: uxth r0, r0 |
| 12 | ; THUMB: uxth r1, r1 |
| 13 | ; THUMB: cmp r0, r1 |
| 14 | %cmp = icmp ult i16 %a, %b |
| 15 | %conv2 = zext i1 %cmp to i32 |
| 16 | ret i32 %conv2 |
| 17 | } |
| 18 | |
| 19 | define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind { |
| 20 | entry: |
| 21 | ; ARM: icmp_i8_signed |
| 22 | ; ARM: sxtb r0, r0 |
| 23 | ; ARM: sxtb r1, r1 |
| 24 | ; ARM: cmp r0, r1 |
| 25 | ; THUMB: icmp_i8_signed |
| 26 | ; THUMB: sxtb r0, r0 |
| 27 | ; THUMB: sxtb r1, r1 |
| 28 | ; THUMB: cmp r0, r1 |
| 29 | %cmp = icmp sgt i8 %a, %b |
| 30 | %conv2 = zext i1 %cmp to i32 |
| 31 | ret i32 %conv2 |
| 32 | } |
| 33 | |
| 34 | define i32 @icmp_i1_unsigned(i1 %a, i1 %b) nounwind { |
| 35 | entry: |
| 36 | ; ARM: icmp_i1_unsigned |
| 37 | ; ARM: and r0, r0, #1 |
| 38 | ; ARM: and r1, r1, #1 |
| 39 | ; ARM: cmp r0, r1 |
| 40 | ; THUMB: icmp_i1_unsigned |
| 41 | ; THUMB: and r0, r0, #1 |
| 42 | ; THUMB: and r1, r1, #1 |
| 43 | ; THUMB: cmp r0, r1 |
| 44 | %cmp = icmp ult i1 %a, %b |
| 45 | %conv2 = zext i1 %cmp to i32 |
| 46 | ret i32 %conv2 |
| 47 | } |