| Duncan Sands | e7de3b2 | 2012-07-05 09:32:46 +0000 | [diff] [blame^] | 1 | ; RUN: llc -march=x86 -mcpu=nehalem < %s | FileCheck %s |
| 2 | |
| 3 | define <4 x i32> @test_ueq(<4 x float> %in) { |
| 4 | entry: |
| 5 | ; CHECK: pcmpeqd %xmm0, %xmm0 |
| 6 | ; CHECK-NEXT: ret |
| 7 | %0 = fcmp ueq <4 x float> %in, %in |
| 8 | %1 = sext <4 x i1> %0 to <4 x i32> |
| 9 | ret <4 x i32> %1 |
| 10 | } |
| 11 | |
| 12 | define <4 x i32> @test_uge(<4 x float> %in) { |
| 13 | entry: |
| 14 | ; CHECK: pcmpeqd %xmm0, %xmm0 |
| 15 | ; CHECK-NEXT: ret |
| 16 | %0 = fcmp uge <4 x float> %in, %in |
| 17 | %1 = sext <4 x i1> %0 to <4 x i32> |
| 18 | ret <4 x i32> %1 |
| 19 | } |
| 20 | |
| 21 | define <4 x i32> @test_ule(<4 x float> %in) { |
| 22 | entry: |
| 23 | ; CHECK: pcmpeqd %xmm0, %xmm0 |
| 24 | ; CHECK-NEXT: ret |
| 25 | %0 = fcmp ule <4 x float> %in, %in |
| 26 | %1 = sext <4 x i1> %0 to <4 x i32> |
| 27 | ret <4 x i32> %1 |
| 28 | } |
| 29 | |
| 30 | define <4 x i32> @test_one(<4 x float> %in) { |
| 31 | entry: |
| 32 | ; CHECK: xorps %xmm0, %xmm0 |
| 33 | ; CHECK-NEXT: ret |
| 34 | %0 = fcmp one <4 x float> %in, %in |
| 35 | %1 = sext <4 x i1> %0 to <4 x i32> |
| 36 | ret <4 x i32> %1 |
| 37 | } |
| 38 | |
| 39 | define <4 x i32> @test_ogt(<4 x float> %in) { |
| 40 | entry: |
| 41 | ; CHECK: xorps %xmm0, %xmm0 |
| 42 | ; CHECK-NEXT: ret |
| 43 | %0 = fcmp ogt <4 x float> %in, %in |
| 44 | %1 = sext <4 x i1> %0 to <4 x i32> |
| 45 | ret <4 x i32> %1 |
| 46 | } |
| 47 | |
| 48 | define <4 x i32> @test_olt(<4 x float> %in) { |
| 49 | entry: |
| 50 | ; CHECK: xorps %xmm0, %xmm0 |
| 51 | ; CHECK-NEXT: ret |
| 52 | %0 = fcmp olt <4 x float> %in, %in |
| 53 | %1 = sext <4 x i1> %0 to <4 x i32> |
| 54 | ret <4 x i32> %1 |
| 55 | } |