Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / edc83d6ec19f32ce2a3ea11109674d5370815d8c / . / lib / Target / Alpha / AlphaInstrInfo.h
blob: f04c4881f254e2e8ffa8913a1349fc2d06a95265 [file] [log] [blame]
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1//===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner081ce942007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Alpha implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ALPHAINSTRUCTIONINFO_H
15#define ALPHAINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "AlphaRegisterInfo.h"
19
20namespace llvm {
21
Chris Lattnerd2fd6db2008-01-01 01:03:04 +0000[diff] [blame]22class AlphaInstrInfo : public TargetInstrInfoImpl {
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]23 const AlphaRegisterInfo RI;
24public:
25 AlphaInstrInfo();
26
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
30 ///
Dan Gohmanb41dfba2008-05-14 01:58:56 +0000[diff] [blame]31 virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]32
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
35 ///
36 virtual bool isMoveInstr(const MachineInstr &MI,
37 unsigned &SrcReg, unsigned &DstReg) const;
38
Dan Gohman90feee22008-11-18 19:49:32 +0000[diff] [blame]39 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
40 int &FrameIndex) const;
41 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
42 int &FrameIndex) const;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]43
44 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
45 MachineBasicBlock *FBB,
Owen Andersond131b5b2008-08-14 22:49:33 +0000[diff] [blame]46 const SmallVectorImpl<MachineOperand> &Cond) const;
Owen Anderson9fa72d92008-08-26 18:03:31 +0000[diff] [blame]47 virtual bool copyRegToReg(MachineBasicBlock &MBB,
Owen Anderson8f2c8932007-12-31 06:32:00 +0000[diff] [blame]48 MachineBasicBlock::iterator MI,
49 unsigned DestReg, unsigned SrcReg,
50 const TargetRegisterClass *DestRC,
51 const TargetRegisterClass *SrcRC) const;
Owen Anderson81875432008-01-01 21:11:32 +0000[diff] [blame]52 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MBBI,
54 unsigned SrcReg, bool isKill, int FrameIndex,
55 const TargetRegisterClass *RC) const;
56
57 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
58 SmallVectorImpl<MachineOperand> &Addr,
59 const TargetRegisterClass *RC,
60 SmallVectorImpl<MachineInstr*> &NewMIs) const;
61
62 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
63 MachineBasicBlock::iterator MBBI,
64 unsigned DestReg, int FrameIndex,
65 const TargetRegisterClass *RC) const;
66
67 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
68 SmallVectorImpl<MachineOperand> &Addr,
69 const TargetRegisterClass *RC,
70 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Owen Anderson9a184ef2008-01-07 01:35:02 +0000[diff] [blame]71
Dan Gohmanedc83d62008-12-03 18:43:12 +0000[diff] [blame^]72 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
73 MachineInstr* MI,
74 const SmallVectorImpl<unsigned> &Ops,
75 int FrameIndex) const;
Owen Anderson9a184ef2008-01-07 01:35:02 +0000[diff] [blame]76
Dan Gohmanedc83d62008-12-03 18:43:12 +0000[diff] [blame^]77 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
78 MachineInstr* MI,
79 const SmallVectorImpl<unsigned> &Ops,
80 MachineInstr* LoadMI) const {
Owen Anderson9a184ef2008-01-07 01:35:02 +0000[diff] [blame]81 return 0;
82 }
83
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]84 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
85 MachineBasicBlock *&FBB,
Owen Andersond131b5b2008-08-14 22:49:33 +0000[diff] [blame]86 SmallVectorImpl<MachineOperand> &Cond) const;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]87 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
88 void insertNoop(MachineBasicBlock &MBB,
89 MachineBasicBlock::iterator MI) const;
Dan Gohman46b948e2008-10-16 01:49:15 +0000[diff] [blame]90 bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
Owen Andersond131b5b2008-08-14 22:49:33 +0000[diff] [blame]91 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]92};
93
94}
95
96#endif