Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / f17a25c88b892d30c2b41ba7ecdfbdfb2b4be9cc / . / lib / Target / ARM / ARMInstrThumb.td
blob: 27231daf133064f7ddad6595ce113a95c1c9f5a0 [file] [log] [blame]
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame^]1//===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under the
6// University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Thumb instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Thumb specific DAG Nodes.
16//
17
18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
20
21// TI - Thumb instruction.
22
23// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
24class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
25 list<Predicate> Predicates = [IsThumb];
26}
27
28class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
29 list<Predicate> Predicates = [IsThumb, HasV5T];
30}
31
32class ThumbI<dag ops, AddrMode am, SizeFlagVal sz,
33 string asm, string cstr, list<dag> pattern>
34 // FIXME: Set all opcodes to 0 for now.
35 : InstARM<0, am, sz, IndexModeNone, cstr> {
36 let OperandList = ops;
37 let AsmString = asm;
38 let Pattern = pattern;
39 list<Predicate> Predicates = [IsThumb];
40}
41
42class TI<dag ops, string asm, list<dag> pattern>
43 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "", pattern>;
44class TI1<dag ops, string asm, list<dag> pattern>
45 : ThumbI<ops, AddrModeT1, Size2Bytes, asm, "", pattern>;
46class TI2<dag ops, string asm, list<dag> pattern>
47 : ThumbI<ops, AddrModeT2, Size2Bytes, asm, "", pattern>;
48class TI4<dag ops, string asm, list<dag> pattern>
49 : ThumbI<ops, AddrModeT4, Size2Bytes, asm, "", pattern>;
50class TIs<dag ops, string asm, list<dag> pattern>
51 : ThumbI<ops, AddrModeTs, Size2Bytes, asm, "", pattern>;
52
53// Two-address instructions
54class TIt<dag ops, string asm, list<dag> pattern>
55 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
56
57// BL, BLX(1) are translated by assembler into two instructions
58class TIx2<dag ops, string asm, list<dag> pattern>
59 : ThumbI<ops, AddrModeNone, Size4Bytes, asm, "", pattern>;
60
61// BR_JT instructions
62class TJTI<dag ops, string asm, list<dag> pattern>
63 : ThumbI<ops, AddrModeNone, SizeSpecial, asm, "", pattern>;
64
65def imm_neg_XFORM : SDNodeXForm<imm, [{
66 return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
67}]>;
68def imm_comp_XFORM : SDNodeXForm<imm, [{
69 return CurDAG->getTargetConstant(~((uint32_t)N->getValue()), MVT::i32);
70}]>;
71
72
73/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
74def imm0_7 : PatLeaf<(i32 imm), [{
75 return (uint32_t)N->getValue() < 8;
76}]>;
77def imm0_7_neg : PatLeaf<(i32 imm), [{
78 return (uint32_t)-N->getValue() < 8;
79}], imm_neg_XFORM>;
80
81def imm0_255 : PatLeaf<(i32 imm), [{
82 return (uint32_t)N->getValue() < 256;
83}]>;
84def imm0_255_comp : PatLeaf<(i32 imm), [{
85 return ~((uint32_t)N->getValue()) < 256;
86}]>;
87
88def imm8_255 : PatLeaf<(i32 imm), [{
89 return (uint32_t)N->getValue() >= 8 && (uint32_t)N->getValue() < 256;
90}]>;
91def imm8_255_neg : PatLeaf<(i32 imm), [{
92 unsigned Val = -N->getValue();
93 return Val >= 8 && Val < 256;
94}], imm_neg_XFORM>;
95
96// Break imm's up into two pieces: an immediate + a left shift.
97// This uses thumb_immshifted to match and thumb_immshifted_val and
98// thumb_immshifted_shamt to get the val/shift pieces.
99def thumb_immshifted : PatLeaf<(imm), [{
100 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getValue());
101}]>;
102
103def thumb_immshifted_val : SDNodeXForm<imm, [{
104 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getValue());
105 return CurDAG->getTargetConstant(V, MVT::i32);
106}]>;
107
108def thumb_immshifted_shamt : SDNodeXForm<imm, [{
109 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getValue());
110 return CurDAG->getTargetConstant(V, MVT::i32);
111}]>;
112
113// Define Thumb specific addressing modes.
114
115// t_addrmode_rr := reg + reg
116//
117def t_addrmode_rr : Operand<i32>,
118 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
119 let PrintMethod = "printThumbAddrModeRROperand";
120 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
121}
122
123// t_addrmode_s4 := reg + reg
124// reg + imm5 * 4
125//
126def t_addrmode_s4 : Operand<i32>,
127 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
128 let PrintMethod = "printThumbAddrModeS4Operand";
129 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
130}
131
132// t_addrmode_s2 := reg + reg
133// reg + imm5 * 2
134//
135def t_addrmode_s2 : Operand<i32>,
136 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
137 let PrintMethod = "printThumbAddrModeS2Operand";
138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
139}
140
141// t_addrmode_s1 := reg + reg
142// reg + imm5
143//
144def t_addrmode_s1 : Operand<i32>,
145 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
146 let PrintMethod = "printThumbAddrModeS1Operand";
147 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
148}
149
150// t_addrmode_sp := sp + imm8 * 4
151//
152def t_addrmode_sp : Operand<i32>,
153 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
154 let PrintMethod = "printThumbAddrModeSPOperand";
155 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
156}
157
158//===----------------------------------------------------------------------===//
159// Miscellaneous Instructions.
160//
161
162def tADJCALLSTACKUP :
163PseudoInst<(ops i32imm:$amt),
164 "@ tADJCALLSTACKUP $amt",
165 [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>;
166
167def tADJCALLSTACKDOWN :
168PseudoInst<(ops i32imm:$amt),
169 "@ tADJCALLSTACKDOWN $amt",
170 [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>;
171
172let isNotDuplicable = 1 in
173def tPICADD : TIt<(ops GPR:$dst, GPR:$lhs, pclabel:$cp),
174 "$cp:\n\tadd $dst, pc",
175 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
176
177//===----------------------------------------------------------------------===//
178// Control Flow Instructions.
179//
180
181let isReturn = 1, isTerminator = 1 in {
182 def tBX_RET : TI<(ops), "bx lr", [(ARMretflag)]>;
183 // Alternative return instruction used by vararg functions.
184 def tBX_RET_vararg : TI<(ops GPR:$dst), "bx $dst", []>;
185}
186
187// FIXME: remove when we have a way to marking a MI with these properties.
188let isLoad = 1, isReturn = 1, isTerminator = 1 in
189def tPOP_RET : TI<(ops reglist:$dst1, variable_ops),
190 "pop $dst1", []>;
191
192let isCall = 1, noResults = 1,
193 Defs = [R0, R1, R2, R3, LR,
194 D0, D1, D2, D3, D4, D5, D6, D7] in {
195 def tBL : TIx2<(ops i32imm:$func, variable_ops),
196 "bl ${func:call}",
197 [(ARMtcall tglobaladdr:$func)]>;
198 // ARMv5T and above
199 def tBLXi : TIx2<(ops i32imm:$func, variable_ops),
200 "blx ${func:call}",
201 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
202 def tBLXr : TI<(ops GPR:$dst, variable_ops),
203 "blx $dst",
204 [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
205 // ARMv4T
206 def tBX : TIx2<(ops GPR:$dst, variable_ops),
207 "cpy lr, pc\n\tbx $dst",
208 [(ARMcall_nolink GPR:$dst)]>;
209}
210
211let isBranch = 1, isTerminator = 1, noResults = 1 in {
212 let isBarrier = 1 in {
213 let isPredicable = 1 in
214 def tB : TI<(ops brtarget:$dst), "b $dst", [(br bb:$dst)]>;
215
216 // Far jump
217 def tBfar : TIx2<(ops brtarget:$dst), "bl $dst\t@ far jump", []>;
218
219 def tBR_JTr : TJTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
220 "cpy pc, $dst \n\t.align\t2\n$jt",
221 [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
222 }
223}
224
225// FIXME: should be able to write a pattern for ARMBrcond, but can't use
226// a two-value operand where a dag node expects two operands. :(
227let isBranch = 1, isTerminator = 1, noResults = 1 in
228 def tBcc : TI<(ops brtarget:$dst, pred:$cc), "b$cc $dst",
229 [/*(ARMbrcond bb:$dst, imm:$cc)*/]>;
230
231//===----------------------------------------------------------------------===//
232// Load Store Instructions.
233//
234
235let isLoad = 1 in {
236def tLDR : TI4<(ops GPR:$dst, t_addrmode_s4:$addr),
237 "ldr $dst, $addr",
238 [(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
239
240def tLDRB : TI1<(ops GPR:$dst, t_addrmode_s1:$addr),
241 "ldrb $dst, $addr",
242 [(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
243
244def tLDRH : TI2<(ops GPR:$dst, t_addrmode_s2:$addr),
245 "ldrh $dst, $addr",
246 [(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
247
248def tLDRSB : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
249 "ldrsb $dst, $addr",
250 [(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
251
252def tLDRSH : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
253 "ldrsh $dst, $addr",
254 [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
255
256def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
257 "ldr $dst, $addr",
258 [(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
259
260// Special instruction for restore. It cannot clobber condition register
261// when it's expanded by eliminateCallFramePseudoInstr().
262def tRestore : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
263 "ldr $dst, $addr", []>;
264
265// Load tconstpool
266def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
267 "ldr $dst, $addr",
268 [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
269
270// Special LDR for loads from non-pc-relative constpools.
271let isReMaterializable = 1 in
272def tLDRcp : TIs<(ops GPR:$dst, i32imm:$addr),
273 "ldr $dst, $addr", []>;
274} // isLoad
275
276let isStore = 1 in {
277def tSTR : TI4<(ops GPR:$src, t_addrmode_s4:$addr),
278 "str $src, $addr",
279 [(store GPR:$src, t_addrmode_s4:$addr)]>;
280
281def tSTRB : TI1<(ops GPR:$src, t_addrmode_s1:$addr),
282 "strb $src, $addr",
283 [(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
284
285def tSTRH : TI2<(ops GPR:$src, t_addrmode_s2:$addr),
286 "strh $src, $addr",
287 [(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
288
289def tSTRspi : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
290 "str $src, $addr",
291 [(store GPR:$src, t_addrmode_sp:$addr)]>;
292
293// Special instruction for spill. It cannot clobber condition register
294// when it's expanded by eliminateCallFramePseudoInstr().
295def tSpill : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
296 "str $src, $addr", []>;
297}
298
299//===----------------------------------------------------------------------===//
300// Load / store multiple Instructions.
301//
302
303// TODO: A7-44: LDMIA - load multiple
304
305let isLoad = 1 in
306def tPOP : TI<(ops reglist:$dst1, variable_ops),
307 "pop $dst1", []>;
308
309let isStore = 1 in
310def tPUSH : TI<(ops reglist:$src1, variable_ops),
311 "push $src1", []>;
312
313//===----------------------------------------------------------------------===//
314// Arithmetic Instructions.
315//
316
317// Add with carry
318def tADC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
319 "adc $dst, $rhs",
320 [(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>;
321
322def tADDS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
323 "add $dst, $lhs, $rhs",
324 [(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>;
325
326
327def tADDi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
328 "add $dst, $lhs, $rhs",
329 [(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
330
331def tADDi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
332 "add $dst, $rhs",
333 [(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
334
335def tADDrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
336 "add $dst, $lhs, $rhs",
337 [(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
338
339def tADDhirr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
340 "add $dst, $rhs", []>;
341
342def tADDrPCi : TI<(ops GPR:$dst, i32imm:$rhs),
343 "add $dst, pc, $rhs * 4", []>;
344def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs),
345 "add $dst, $sp, $rhs * 4", []>;
346def tADDspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
347 "add $dst, $rhs * 4", []>;
348
349def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
350 "and $dst, $rhs",
351 [(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
352
353def tASRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
354 "asr $dst, $lhs, $rhs",
355 [(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
356
357def tASRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
358 "asr $dst, $rhs",
359 [(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
360
361def tBIC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
362 "bic $dst, $rhs",
363 [(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
364
365
366def tCMN : TI<(ops GPR:$lhs, GPR:$rhs),
367 "cmn $lhs, $rhs",
368 [(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
369
370def tCMPi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
371 "cmp $lhs, $rhs",
372 [(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
373
374def tCMPr : TI<(ops GPR:$lhs, GPR:$rhs),
375 "cmp $lhs, $rhs",
376 [(ARMcmp GPR:$lhs, GPR:$rhs)]>;
377
378def tTST : TI<(ops GPR:$lhs, GPR:$rhs),
379 "tst $lhs, $rhs",
380 [(ARMcmpNZ (and GPR:$lhs, GPR:$rhs), 0)]>;
381
382def tCMNNZ : TI<(ops GPR:$lhs, GPR:$rhs),
383 "cmn $lhs, $rhs",
384 [(ARMcmpNZ GPR:$lhs, (ineg GPR:$rhs))]>;
385
386def tCMPNZi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
387 "cmp $lhs, $rhs",
388 [(ARMcmpNZ GPR:$lhs, imm0_255:$rhs)]>;
389
390def tCMPNZr : TI<(ops GPR:$lhs, GPR:$rhs),
391 "cmp $lhs, $rhs",
392 [(ARMcmpNZ GPR:$lhs, GPR:$rhs)]>;
393
394// TODO: A7-37: CMP(3) - cmp hi regs
395
396def tEOR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
397 "eor $dst, $rhs",
398 [(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
399
400def tLSLri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
401 "lsl $dst, $lhs, $rhs",
402 [(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
403
404def tLSLrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
405 "lsl $dst, $rhs",
406 [(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
407
408def tLSRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
409 "lsr $dst, $lhs, $rhs",
410 [(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
411
412def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
413 "lsr $dst, $rhs",
414 [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
415
416// FIXME: This is not rematerializable because mov changes the condition code.
417def tMOVi8 : TI<(ops GPR:$dst, i32imm:$src),
418 "mov $dst, $src",
419 [(set GPR:$dst, imm0_255:$src)]>;
420
421// TODO: A7-73: MOV(2) - mov setting flag.
422
423
424// Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
425// which is MOV(3). This also supports high registers.
426def tMOVr : TI<(ops GPR:$dst, GPR:$src),
427 "cpy $dst, $src", []>;
428
429def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
430 "mul $dst, $rhs",
431 [(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
432
433def tMVN : TI<(ops GPR:$dst, GPR:$src),
434 "mvn $dst, $src",
435 [(set GPR:$dst, (not GPR:$src))]>;
436
437def tNEG : TI<(ops GPR:$dst, GPR:$src),
438 "neg $dst, $src",
439 [(set GPR:$dst, (ineg GPR:$src))]>;
440
441def tORR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
442 "orr $dst, $rhs",
443 [(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
444
445
446def tREV : TI<(ops GPR:$dst, GPR:$src),
447 "rev $dst, $src",
448 [(set GPR:$dst, (bswap GPR:$src))]>,
449 Requires<[IsThumb, HasV6]>;
450
451def tREV16 : TI<(ops GPR:$dst, GPR:$src),
452 "rev16 $dst, $src",
453 [(set GPR:$dst,
454 (or (and (srl GPR:$src, 8), 0xFF),
455 (or (and (shl GPR:$src, 8), 0xFF00),
456 (or (and (srl GPR:$src, 8), 0xFF0000),
457 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
458 Requires<[IsThumb, HasV6]>;
459
460def tREVSH : TI<(ops GPR:$dst, GPR:$src),
461 "revsh $dst, $src",
462 [(set GPR:$dst,
463 (sext_inreg
464 (or (srl (and GPR:$src, 0xFFFF), 8),
465 (shl GPR:$src, 8)), i16))]>,
466 Requires<[IsThumb, HasV6]>;
467
468def tROR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
469 "ror $dst, $rhs",
470 [(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
471
472
473// Subtract with carry
474def tSBC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
475 "sbc $dst, $rhs",
476 [(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
477
478def tSUBS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
479 "sub $dst, $lhs, $rhs",
480 [(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>;
481
482
483// TODO: A7-96: STMIA - store multiple.
484
485def tSUBi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
486 "sub $dst, $lhs, $rhs",
487 [(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
488
489def tSUBi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
490 "sub $dst, $rhs",
491 [(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
492
493def tSUBrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
494 "sub $dst, $lhs, $rhs",
495 [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
496
497def tSUBspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
498 "sub $dst, $rhs * 4", []>;
499
500def tSXTB : TI<(ops GPR:$dst, GPR:$src),
501 "sxtb $dst, $src",
502 [(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
503 Requires<[IsThumb, HasV6]>;
504def tSXTH : TI<(ops GPR:$dst, GPR:$src),
505 "sxth $dst, $src",
506 [(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
507 Requires<[IsThumb, HasV6]>;
508
509
510def tUXTB : TI<(ops GPR:$dst, GPR:$src),
511 "uxtb $dst, $src",
512 [(set GPR:$dst, (and GPR:$src, 0xFF))]>,
513 Requires<[IsThumb, HasV6]>;
514def tUXTH : TI<(ops GPR:$dst, GPR:$src),
515 "uxth $dst, $src",
516 [(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
517 Requires<[IsThumb, HasV6]>;
518
519
520// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
521// Expanded by the scheduler into a branch sequence.
522let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
523 def tMOVCCr :
524 PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, pred:$cc),
525 "@ tMOVCCr $cc",
526 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))*/]>;
527
528// tLEApcrel - Load a pc-relative address into a register without offending the
529// assembler.
530def tLEApcrel : TIx2<(ops GPR:$dst, i32imm:$label),
531 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
532 "${:private}PCRELL${:uid}+4))\n"),
533 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
534 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
535 []>;
536
537def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id),
538 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
539 "${:private}PCRELL${:uid}+4))\n"),
540 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
541 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
542 []>;
543
544//===----------------------------------------------------------------------===//
545// TLS Instructions
546//
547
548// __aeabi_read_tp preserves the registers r1-r3.
549let isCall = 1,
550 Defs = [R0, LR] in {
551 def tTPsoft : TIx2<(ops),
552 "bl __aeabi_read_tp",
553 [(set R0, ARMthread_pointer)]>;
554}
555
556//===----------------------------------------------------------------------===//
557// Non-Instruction Patterns
558//
559
560// ConstantPool, GlobalAddress
561def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
562def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
563
564// JumpTable
565def : ThumbPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
566 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
567
568// Direct calls
569def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
570def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
571
572// Indirect calls to ARM routines
573def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
574
575// zextload i1 -> zextload i8
576def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
577 (tLDRB t_addrmode_s1:$addr)>;
578
579// extload -> zextload
580def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
581def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
582def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
583
584// truncstore i1 -> truncstore i8
585def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst),
586 (tSTRB GPR:$src, t_addrmode_s1:$dst)>;
587
588// Large immediate handling.
589
590// Two piece imms.
591def : ThumbPat<(i32 thumb_immshifted:$src),
592 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
593 (thumb_immshifted_shamt imm:$src))>;
594
595def : ThumbPat<(i32 imm0_255_comp:$src),
596 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;