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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / f17a25c88b892d30c2b41ba7ecdfbdfb2b4be9cc / . / lib / Target / X86 / X86InstrSSE.td
blob: 5fc7a65a084ca5387ac4f527fb1016436d4ff058 [file] [log] [blame]
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame^]1//====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by Evan Cheng and is distributed under the University
6// of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 SSE instruction set, defining the instructions,
11// and properties of the instructions which are needed for code generation,
12// machine code emission, and analysis.
13//
14//===----------------------------------------------------------------------===//
15
16
17//===----------------------------------------------------------------------===//
18// SSE specific DAG Nodes.
19//===----------------------------------------------------------------------===//
20
21def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23
24def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad, [SDNPHasChain]>;
25def X86loadu : SDNode<"X86ISD::LOAD_UA", SDTLoad, [SDNPHasChain]>;
26def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
38 [SDNPHasChain, SDNPOutFlag]>;
39def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
40 [SDNPHasChain, SDNPOutFlag]>;
41def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
42def X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
43def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
44
45//===----------------------------------------------------------------------===//
46// SSE 'Special' Instructions
47//===----------------------------------------------------------------------===//
48
49def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
50 "#IMPLICIT_DEF $dst",
51 [(set VR128:$dst, (v4f32 (undef)))]>,
52 Requires<[HasSSE1]>;
53def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
54 "#IMPLICIT_DEF $dst",
55 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
56def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
57 "#IMPLICIT_DEF $dst",
58 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
59
60//===----------------------------------------------------------------------===//
61// SSE Complex Patterns
62//===----------------------------------------------------------------------===//
63
64// These are 'extloads' from a scalar to the low element of a vector, zeroing
65// the top elements. These are used for the SSE 'ss' and 'sd' instruction
66// forms.
67def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
68 [SDNPHasChain]>;
69def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
70 [SDNPHasChain]>;
71
72def ssmem : Operand<v4f32> {
73 let PrintMethod = "printf32mem";
74 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
75}
76def sdmem : Operand<v2f64> {
77 let PrintMethod = "printf64mem";
78 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
79}
80
81//===----------------------------------------------------------------------===//
82// SSE pattern fragments
83//===----------------------------------------------------------------------===//
84
85def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
86def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
87
88def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
89def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
90def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
91def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
92
93def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
94def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
95def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
96def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
97def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
98def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
99
100def fp32imm0 : PatLeaf<(f32 fpimm), [{
101 return N->isExactlyValue(+0.0);
102}]>;
103
104def PSxLDQ_imm : SDNodeXForm<imm, [{
105 // Transformation function: imm >> 3
106 return getI32Imm(N->getValue() >> 3);
107}]>;
108
109// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
110// SHUFP* etc. imm.
111def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
112 return getI8Imm(X86::getShuffleSHUFImmediate(N));
113}]>;
114
115// SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
116// PSHUFHW imm.
117def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
118 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
119}]>;
120
121// SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
122// PSHUFLW imm.
123def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
124 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
125}]>;
126
127def SSE_splat_mask : PatLeaf<(build_vector), [{
128 return X86::isSplatMask(N);
129}], SHUFFLE_get_shuf_imm>;
130
131def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
132 return X86::isSplatLoMask(N);
133}]>;
134
135def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
136 return X86::isMOVHLPSMask(N);
137}]>;
138
139def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
140 return X86::isMOVHLPS_v_undef_Mask(N);
141}]>;
142
143def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
144 return X86::isMOVHPMask(N);
145}]>;
146
147def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
148 return X86::isMOVLPMask(N);
149}]>;
150
151def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
152 return X86::isMOVLMask(N);
153}]>;
154
155def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
156 return X86::isMOVSHDUPMask(N);
157}]>;
158
159def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
160 return X86::isMOVSLDUPMask(N);
161}]>;
162
163def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
164 return X86::isUNPCKLMask(N);
165}]>;
166
167def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
168 return X86::isUNPCKHMask(N);
169}]>;
170
171def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
172 return X86::isUNPCKL_v_undef_Mask(N);
173}]>;
174
175def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
176 return X86::isUNPCKH_v_undef_Mask(N);
177}]>;
178
179def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
180 return X86::isPSHUFDMask(N);
181}], SHUFFLE_get_shuf_imm>;
182
183def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
184 return X86::isPSHUFHWMask(N);
185}], SHUFFLE_get_pshufhw_imm>;
186
187def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
188 return X86::isPSHUFLWMask(N);
189}], SHUFFLE_get_pshuflw_imm>;
190
191def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
192 return X86::isPSHUFDMask(N);
193}], SHUFFLE_get_shuf_imm>;
194
195def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
196 return X86::isSHUFPMask(N);
197}], SHUFFLE_get_shuf_imm>;
198
199def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
200 return X86::isSHUFPMask(N);
201}], SHUFFLE_get_shuf_imm>;
202
203//===----------------------------------------------------------------------===//
204// SSE scalar FP Instructions
205//===----------------------------------------------------------------------===//
206
207// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
208// scheduler into a branch sequence.
209let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
210 def CMOV_FR32 : I<0, Pseudo,
211 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
212 "#CMOV_FR32 PSEUDO!",
213 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
214 def CMOV_FR64 : I<0, Pseudo,
215 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
216 "#CMOV_FR64 PSEUDO!",
217 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
218 def CMOV_V4F32 : I<0, Pseudo,
219 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
220 "#CMOV_V4F32 PSEUDO!",
221 [(set VR128:$dst,
222 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
223 def CMOV_V2F64 : I<0, Pseudo,
224 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
225 "#CMOV_V2F64 PSEUDO!",
226 [(set VR128:$dst,
227 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
228 def CMOV_V2I64 : I<0, Pseudo,
229 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
230 "#CMOV_V2I64 PSEUDO!",
231 [(set VR128:$dst,
232 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
233}
234
235//===----------------------------------------------------------------------===//
236// SSE1 Instructions
237//===----------------------------------------------------------------------===//
238
239// SSE1 Instruction Templates:
240//
241// SSI - SSE1 instructions with XS prefix.
242// PSI - SSE1 instructions with TB prefix.
243// PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
244
245class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
246 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
247class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
248 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
249class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
250 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
251
252// Move Instructions
253def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
254 "movss {$src, $dst|$dst, $src}", []>;
255def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
256 "movss {$src, $dst|$dst, $src}",
257 [(set FR32:$dst, (loadf32 addr:$src))]>;
258def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
259 "movss {$src, $dst|$dst, $src}",
260 [(store FR32:$src, addr:$dst)]>;
261
262// Conversion instructions
263def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (ops GR32:$dst, FR32:$src),
264 "cvttss2si {$src, $dst|$dst, $src}",
265 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
266def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
267 "cvttss2si {$src, $dst|$dst, $src}",
268 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
269def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR32:$src),
270 "cvtsi2ss {$src, $dst|$dst, $src}",
271 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
272def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
273 "cvtsi2ss {$src, $dst|$dst, $src}",
274 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
275
276// Match intrinsics which expect XMM operand(s).
277def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
278 "cvtss2si {$src, $dst|$dst, $src}",
279 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
280def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
281 "cvtss2si {$src, $dst|$dst, $src}",
282 [(set GR32:$dst, (int_x86_sse_cvtss2si
283 (load addr:$src)))]>;
284
285// Aliases for intrinsics
286def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
287 "cvttss2si {$src, $dst|$dst, $src}",
288 [(set GR32:$dst,
289 (int_x86_sse_cvttss2si VR128:$src))]>;
290def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
291 "cvttss2si {$src, $dst|$dst, $src}",
292 [(set GR32:$dst,
293 (int_x86_sse_cvttss2si(load addr:$src)))]>;
294
295let isTwoAddress = 1 in {
296 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
297 (ops VR128:$dst, VR128:$src1, GR32:$src2),
298 "cvtsi2ss {$src2, $dst|$dst, $src2}",
299 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
300 GR32:$src2))]>;
301 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
302 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
303 "cvtsi2ss {$src2, $dst|$dst, $src2}",
304 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
305 (loadi32 addr:$src2)))]>;
306}
307
308// Comparison instructions
309let isTwoAddress = 1 in {
310 def CMPSSrr : SSI<0xC2, MRMSrcReg,
311 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
312 "cmp${cc}ss {$src, $dst|$dst, $src}",
313 []>;
314 def CMPSSrm : SSI<0xC2, MRMSrcMem,
315 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
316 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
317}
318
319def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
320 "ucomiss {$src2, $src1|$src1, $src2}",
321 [(X86cmp FR32:$src1, FR32:$src2)]>;
322def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
323 "ucomiss {$src2, $src1|$src1, $src2}",
324 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
325
326// Aliases to match intrinsics which expect XMM operand(s).
327let isTwoAddress = 1 in {
328 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
329 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
330 "cmp${cc}ss {$src, $dst|$dst, $src}",
331 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
332 VR128:$src, imm:$cc))]>;
333 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
334 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
335 "cmp${cc}ss {$src, $dst|$dst, $src}",
336 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
337 (load addr:$src), imm:$cc))]>;
338}
339
340def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
341 "ucomiss {$src2, $src1|$src1, $src2}",
342 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
343def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
344 "ucomiss {$src2, $src1|$src1, $src2}",
345 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2))]>;
346
347def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
348 "comiss {$src2, $src1|$src1, $src2}",
349 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
350def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
351 "comiss {$src2, $src1|$src1, $src2}",
352 [(X86comi (v4f32 VR128:$src1), (load addr:$src2))]>;
353
354// Aliases of packed SSE1 instructions for scalar use. These all have names that
355// start with 'Fs'.
356
357// Alias instructions that map fld0 to pxor for sse.
358def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
359 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
360 Requires<[HasSSE1]>, TB, OpSize;
361
362// Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
363// disregarded.
364def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
365 "movaps {$src, $dst|$dst, $src}", []>;
366
367// Alias instruction to load FR32 from f128mem using movaps. Upper bits are
368// disregarded.
369def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
370 "movaps {$src, $dst|$dst, $src}",
371 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
372
373// Alias bitwise logical operations using SSE logical ops on packed FP values.
374let isTwoAddress = 1 in {
375let isCommutable = 1 in {
376 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
377 "andps {$src2, $dst|$dst, $src2}",
378 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
379 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
380 "orps {$src2, $dst|$dst, $src2}",
381 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
382 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
383 "xorps {$src2, $dst|$dst, $src2}",
384 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
385}
386
387def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
388 "andps {$src2, $dst|$dst, $src2}",
389 [(set FR32:$dst, (X86fand FR32:$src1,
390 (X86loadpf32 addr:$src2)))]>;
391def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
392 "orps {$src2, $dst|$dst, $src2}",
393 [(set FR32:$dst, (X86for FR32:$src1,
394 (X86loadpf32 addr:$src2)))]>;
395def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
396 "xorps {$src2, $dst|$dst, $src2}",
397 [(set FR32:$dst, (X86fxor FR32:$src1,
398 (X86loadpf32 addr:$src2)))]>;
399
400def FsANDNPSrr : PSI<0x55, MRMSrcReg,
401 (ops FR32:$dst, FR32:$src1, FR32:$src2),
402 "andnps {$src2, $dst|$dst, $src2}", []>;
403def FsANDNPSrm : PSI<0x55, MRMSrcMem,
404 (ops FR32:$dst, FR32:$src1, f128mem:$src2),
405 "andnps {$src2, $dst|$dst, $src2}", []>;
406}
407
408/// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
409///
410/// In addition, we also have a special variant of the scalar form here to
411/// represent the associated intrinsic operation. This form is unlike the
412/// plain scalar form, in that it takes an entire vector (instead of a scalar)
413/// and leaves the top elements undefined.
414///
415/// These three forms can each be reg+reg or reg+mem, so there are a total of
416/// six "instructions".
417///
418let isTwoAddress = 1 in {
419multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
420 SDNode OpNode, Intrinsic F32Int,
421 bit Commutable = 0> {
422 // Scalar operation, reg+reg.
423 def SSrr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
424 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
425 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
426 let isCommutable = Commutable;
427 }
428
429 // Scalar operation, reg+mem.
430 def SSrm : SSI<opc, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
431 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
432 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
433
434 // Vector operation, reg+reg.
435 def PSrr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
436 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
437 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
438 let isCommutable = Commutable;
439 }
440
441 // Vector operation, reg+mem.
442 def PSrm : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
443 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
444 [(set VR128:$dst, (OpNode VR128:$src1, (loadv4f32 addr:$src2)))]>;
445
446 // Intrinsic operation, reg+reg.
447 def SSrr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
448 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
449 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
450 let isCommutable = Commutable;
451 }
452
453 // Intrinsic operation, reg+mem.
454 def SSrm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, ssmem:$src2),
455 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
456 [(set VR128:$dst, (F32Int VR128:$src1,
457 sse_load_f32:$src2))]>;
458}
459}
460
461// Arithmetic instructions
462defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
463defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
464defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
465defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
466
467/// sse1_fp_binop_rm - Other SSE1 binops
468///
469/// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
470/// instructions for a full-vector intrinsic form. Operations that map
471/// onto C operators don't use this form since they just use the plain
472/// vector form instead of having a separate vector intrinsic form.
473///
474/// This provides a total of eight "instructions".
475///
476let isTwoAddress = 1 in {
477multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
478 SDNode OpNode,
479 Intrinsic F32Int,
480 Intrinsic V4F32Int,
481 bit Commutable = 0> {
482
483 // Scalar operation, reg+reg.
484 def SSrr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
485 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
486 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
487 let isCommutable = Commutable;
488 }
489
490 // Scalar operation, reg+mem.
491 def SSrm : SSI<opc, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
492 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
493 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
494
495 // Vector operation, reg+reg.
496 def PSrr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
497 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
498 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
499 let isCommutable = Commutable;
500 }
501
502 // Vector operation, reg+mem.
503 def PSrm : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
504 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
505 [(set VR128:$dst, (OpNode VR128:$src1, (loadv4f32 addr:$src2)))]>;
506
507 // Intrinsic operation, reg+reg.
508 def SSrr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
509 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
510 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
511 let isCommutable = Commutable;
512 }
513
514 // Intrinsic operation, reg+mem.
515 def SSrm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, ssmem:$src2),
516 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
517 [(set VR128:$dst, (F32Int VR128:$src1,
518 sse_load_f32:$src2))]>;
519
520 // Vector intrinsic operation, reg+reg.
521 def PSrr_Int : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
522 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
523 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
524 let isCommutable = Commutable;
525 }
526
527 // Vector intrinsic operation, reg+mem.
528 def PSrm_Int : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
529 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
530 [(set VR128:$dst, (V4F32Int VR128:$src1, (load addr:$src2)))]>;
531}
532}
533
534defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
535 int_x86_sse_max_ss, int_x86_sse_max_ps>;
536defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
537 int_x86_sse_min_ss, int_x86_sse_min_ps>;
538
539//===----------------------------------------------------------------------===//
540// SSE packed FP Instructions
541
542// Move Instructions
543def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
544 "movaps {$src, $dst|$dst, $src}", []>;
545def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
546 "movaps {$src, $dst|$dst, $src}",
547 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
548
549def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
550 "movaps {$src, $dst|$dst, $src}",
551 [(store (v4f32 VR128:$src), addr:$dst)]>;
552
553def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
554 "movups {$src, $dst|$dst, $src}", []>;
555def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
556 "movups {$src, $dst|$dst, $src}",
557 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
558def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
559 "movups {$src, $dst|$dst, $src}",
560 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
561
562let isTwoAddress = 1 in {
563 let AddedComplexity = 20 in {
564 def MOVLPSrm : PSI<0x12, MRMSrcMem,
565 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
566 "movlps {$src2, $dst|$dst, $src2}",
567 [(set VR128:$dst,
568 (v4f32 (vector_shuffle VR128:$src1,
569 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
570 MOVLP_shuffle_mask)))]>;
571 def MOVHPSrm : PSI<0x16, MRMSrcMem,
572 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
573 "movhps {$src2, $dst|$dst, $src2}",
574 [(set VR128:$dst,
575 (v4f32 (vector_shuffle VR128:$src1,
576 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
577 MOVHP_shuffle_mask)))]>;
578 } // AddedComplexity
579} // isTwoAddress
580
581def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
582 "movlps {$src, $dst|$dst, $src}",
583 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
584 (iPTR 0))), addr:$dst)]>;
585
586// v2f64 extract element 1 is always custom lowered to unpack high to low
587// and extract element 0 so the non-store version isn't too horrible.
588def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
589 "movhps {$src, $dst|$dst, $src}",
590 [(store (f64 (vector_extract
591 (v2f64 (vector_shuffle
592 (bc_v2f64 (v4f32 VR128:$src)), (undef),
593 UNPCKH_shuffle_mask)), (iPTR 0))),
594 addr:$dst)]>;
595
596let isTwoAddress = 1 in {
597let AddedComplexity = 15 in {
598def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
599 "movlhps {$src2, $dst|$dst, $src2}",
600 [(set VR128:$dst,
601 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
602 MOVHP_shuffle_mask)))]>;
603
604def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
605 "movhlps {$src2, $dst|$dst, $src2}",
606 [(set VR128:$dst,
607 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
608 MOVHLPS_shuffle_mask)))]>;
609} // AddedComplexity
610} // isTwoAddress
611
612
613
614// Arithmetic
615
616/// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
617///
618/// In addition, we also have a special variant of the scalar form here to
619/// represent the associated intrinsic operation. This form is unlike the
620/// plain scalar form, in that it takes an entire vector (instead of a
621/// scalar) and leaves the top elements undefined.
622///
623/// And, we have a special variant form for a full-vector intrinsic form.
624///
625/// These four forms can each have a reg or a mem operand, so there are a
626/// total of eight "instructions".
627///
628multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
629 SDNode OpNode,
630 Intrinsic F32Int,
631 Intrinsic V4F32Int,
632 bit Commutable = 0> {
633 // Scalar operation, reg.
634 def SSr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src),
635 !strconcat(OpcodeStr, "ss {$src, $dst|$dst, $src}"),
636 [(set FR32:$dst, (OpNode FR32:$src))]> {
637 let isCommutable = Commutable;
638 }
639
640 // Scalar operation, mem.
641 def SSm : SSI<opc, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
642 !strconcat(OpcodeStr, "ss {$src, $dst|$dst, $src}"),
643 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
644
645 // Vector operation, reg.
646 def PSr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src),
647 !strconcat(OpcodeStr, "ps {$src, $dst|$dst, $src}"),
648 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
649 let isCommutable = Commutable;
650 }
651
652 // Vector operation, mem.
653 def PSm : PSI<opc, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
654 !strconcat(OpcodeStr, "ps {$src, $dst|$dst, $src}"),
655 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))]>;
656
657 // Intrinsic operation, reg.
658 def SSr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src),
659 !strconcat(OpcodeStr, "ss {$src, $dst|$dst, $src}"),
660 [(set VR128:$dst, (F32Int VR128:$src))]> {
661 let isCommutable = Commutable;
662 }
663
664 // Intrinsic operation, mem.
665 def SSm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, ssmem:$src),
666 !strconcat(OpcodeStr, "ss {$src, $dst|$dst, $src}"),
667 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
668
669 // Vector intrinsic operation, reg
670 def PSr_Int : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src),
671 !strconcat(OpcodeStr, "ps {$src, $dst|$dst, $src}"),
672 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
673 let isCommutable = Commutable;
674 }
675
676 // Vector intrinsic operation, mem
677 def PSm_Int : PSI<opc, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
678 !strconcat(OpcodeStr, "ps {$src, $dst|$dst, $src}"),
679 [(set VR128:$dst, (V4F32Int (load addr:$src)))]>;
680}
681
682// Square root.
683defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
684 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
685
686// Reciprocal approximations. Note that these typically require refinement
687// in order to obtain suitable precision.
688defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
689 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
690defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
691 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
692
693// Logical
694let isTwoAddress = 1 in {
695 let isCommutable = 1 in {
696 def ANDPSrr : PSI<0x54, MRMSrcReg,
697 (ops VR128:$dst, VR128:$src1, VR128:$src2),
698 "andps {$src2, $dst|$dst, $src2}",
699 [(set VR128:$dst, (v2i64
700 (and VR128:$src1, VR128:$src2)))]>;
701 def ORPSrr : PSI<0x56, MRMSrcReg,
702 (ops VR128:$dst, VR128:$src1, VR128:$src2),
703 "orps {$src2, $dst|$dst, $src2}",
704 [(set VR128:$dst, (v2i64
705 (or VR128:$src1, VR128:$src2)))]>;
706 def XORPSrr : PSI<0x57, MRMSrcReg,
707 (ops VR128:$dst, VR128:$src1, VR128:$src2),
708 "xorps {$src2, $dst|$dst, $src2}",
709 [(set VR128:$dst, (v2i64
710 (xor VR128:$src1, VR128:$src2)))]>;
711 }
712
713 def ANDPSrm : PSI<0x54, MRMSrcMem,
714 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
715 "andps {$src2, $dst|$dst, $src2}",
716 [(set VR128:$dst, (and VR128:$src1,
717 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
718 def ORPSrm : PSI<0x56, MRMSrcMem,
719 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
720 "orps {$src2, $dst|$dst, $src2}",
721 [(set VR128:$dst, (or VR128:$src1,
722 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
723 def XORPSrm : PSI<0x57, MRMSrcMem,
724 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
725 "xorps {$src2, $dst|$dst, $src2}",
726 [(set VR128:$dst, (xor VR128:$src1,
727 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
728 def ANDNPSrr : PSI<0x55, MRMSrcReg,
729 (ops VR128:$dst, VR128:$src1, VR128:$src2),
730 "andnps {$src2, $dst|$dst, $src2}",
731 [(set VR128:$dst,
732 (v2i64 (and (xor VR128:$src1,
733 (bc_v2i64 (v4i32 immAllOnesV))),
734 VR128:$src2)))]>;
735 def ANDNPSrm : PSI<0x55, MRMSrcMem,
736 (ops VR128:$dst, VR128:$src1,f128mem:$src2),
737 "andnps {$src2, $dst|$dst, $src2}",
738 [(set VR128:$dst,
739 (v2i64 (and (xor VR128:$src1,
740 (bc_v2i64 (v4i32 immAllOnesV))),
741 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
742}
743
744let isTwoAddress = 1 in {
745 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
746 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
747 "cmp${cc}ps {$src, $dst|$dst, $src}",
748 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
749 VR128:$src, imm:$cc))]>;
750 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
751 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
752 "cmp${cc}ps {$src, $dst|$dst, $src}",
753 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
754 (load addr:$src), imm:$cc))]>;
755}
756
757// Shuffle and unpack instructions
758let isTwoAddress = 1 in {
759 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
760 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
761 (ops VR128:$dst, VR128:$src1,
762 VR128:$src2, i32i8imm:$src3),
763 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
764 [(set VR128:$dst,
765 (v4f32 (vector_shuffle
766 VR128:$src1, VR128:$src2,
767 SHUFP_shuffle_mask:$src3)))]>;
768 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
769 (ops VR128:$dst, VR128:$src1,
770 f128mem:$src2, i32i8imm:$src3),
771 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
772 [(set VR128:$dst,
773 (v4f32 (vector_shuffle
774 VR128:$src1, (load addr:$src2),
775 SHUFP_shuffle_mask:$src3)))]>;
776
777 let AddedComplexity = 10 in {
778 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
779 (ops VR128:$dst, VR128:$src1, VR128:$src2),
780 "unpckhps {$src2, $dst|$dst, $src2}",
781 [(set VR128:$dst,
782 (v4f32 (vector_shuffle
783 VR128:$src1, VR128:$src2,
784 UNPCKH_shuffle_mask)))]>;
785 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
786 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
787 "unpckhps {$src2, $dst|$dst, $src2}",
788 [(set VR128:$dst,
789 (v4f32 (vector_shuffle
790 VR128:$src1, (load addr:$src2),
791 UNPCKH_shuffle_mask)))]>;
792
793 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
794 (ops VR128:$dst, VR128:$src1, VR128:$src2),
795 "unpcklps {$src2, $dst|$dst, $src2}",
796 [(set VR128:$dst,
797 (v4f32 (vector_shuffle
798 VR128:$src1, VR128:$src2,
799 UNPCKL_shuffle_mask)))]>;
800 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
801 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
802 "unpcklps {$src2, $dst|$dst, $src2}",
803 [(set VR128:$dst,
804 (v4f32 (vector_shuffle
805 VR128:$src1, (load addr:$src2),
806 UNPCKL_shuffle_mask)))]>;
807 } // AddedComplexity
808} // isTwoAddress
809
810// Mask creation
811def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
812 "movmskps {$src, $dst|$dst, $src}",
813 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
814def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
815 "movmskpd {$src, $dst|$dst, $src}",
816 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
817
818// Prefetching loads.
819// TODO: no intrinsics for these?
820def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src), "prefetcht0 $src", []>;
821def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src), "prefetcht1 $src", []>;
822def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src), "prefetcht2 $src", []>;
823def PREFETCHNTA : PSI<0x18, MRM0m, (ops i8mem:$src), "prefetchnta $src", []>;
824
825// Non-temporal stores
826def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
827 "movntps {$src, $dst|$dst, $src}",
828 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
829
830// Load, store, and memory fence
831def SFENCE : PSI<0xAE, MRM7m, (ops), "sfence", [(int_x86_sse_sfence)]>;
832
833// MXCSR register
834def LDMXCSR : PSI<0xAE, MRM2m, (ops i32mem:$src),
835 "ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>;
836def STMXCSR : PSI<0xAE, MRM3m, (ops i32mem:$dst),
837 "stmxcsr $dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
838
839// Alias instructions that map zero vector to pxor / xorp* for sse.
840// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
841let isReMaterializable = 1 in
842def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
843 "xorps $dst, $dst",
844 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
845
846// FR32 to 128-bit vector conversion.
847def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
848 "movss {$src, $dst|$dst, $src}",
849 [(set VR128:$dst,
850 (v4f32 (scalar_to_vector FR32:$src)))]>;
851def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
852 "movss {$src, $dst|$dst, $src}",
853 [(set VR128:$dst,
854 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
855
856// FIXME: may not be able to eliminate this movss with coalescing the src and
857// dest register classes are different. We really want to write this pattern
858// like this:
859// def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
860// (f32 FR32:$src)>;
861def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
862 "movss {$src, $dst|$dst, $src}",
863 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
864 (iPTR 0)))]>;
865def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
866 "movss {$src, $dst|$dst, $src}",
867 [(store (f32 (vector_extract (v4f32 VR128:$src),
868 (iPTR 0))), addr:$dst)]>;
869
870
871// Move to lower bits of a VR128, leaving upper bits alone.
872// Three operand (but two address) aliases.
873let isTwoAddress = 1 in {
874 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
875 (ops VR128:$dst, VR128:$src1, FR32:$src2),
876 "movss {$src2, $dst|$dst, $src2}", []>;
877
878 let AddedComplexity = 15 in
879 def MOVLPSrr : SSI<0x10, MRMSrcReg,
880 (ops VR128:$dst, VR128:$src1, VR128:$src2),
881 "movss {$src2, $dst|$dst, $src2}",
882 [(set VR128:$dst,
883 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
884 MOVL_shuffle_mask)))]>;
885}
886
887// Move to lower bits of a VR128 and zeroing upper bits.
888// Loading from memory automatically zeroing upper bits.
889let AddedComplexity = 20 in
890def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
891 "movss {$src, $dst|$dst, $src}",
892 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV,
893 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
894 MOVL_shuffle_mask)))]>;
895
896
897//===----------------------------------------------------------------------===//
898// SSE2 Instructions
899//===----------------------------------------------------------------------===//
900
901// SSE2 Instruction Templates:
902//
903// SDI - SSE2 instructions with XD prefix.
904// PDI - SSE2 instructions with TB and OpSize prefixes.
905// PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
906
907class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
908 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
909class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
910 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
911class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
912 : Ii8<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
913
914// Move Instructions
915def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
916 "movsd {$src, $dst|$dst, $src}", []>;
917def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
918 "movsd {$src, $dst|$dst, $src}",
919 [(set FR64:$dst, (loadf64 addr:$src))]>;
920def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
921 "movsd {$src, $dst|$dst, $src}",
922 [(store FR64:$src, addr:$dst)]>;
923
924// Conversion instructions
925def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (ops GR32:$dst, FR64:$src),
926 "cvttsd2si {$src, $dst|$dst, $src}",
927 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
928def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f64mem:$src),
929 "cvttsd2si {$src, $dst|$dst, $src}",
930 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
931def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
932 "cvtsd2ss {$src, $dst|$dst, $src}",
933 [(set FR32:$dst, (fround FR64:$src))]>;
934def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
935 "cvtsd2ss {$src, $dst|$dst, $src}",
936 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
937def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR32:$src),
938 "cvtsi2sd {$src, $dst|$dst, $src}",
939 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
940def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
941 "cvtsi2sd {$src, $dst|$dst, $src}",
942 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
943
944// SSE2 instructions with XS prefix
945def CVTSS2SDrr : I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
946 "cvtss2sd {$src, $dst|$dst, $src}",
947 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
948 Requires<[HasSSE2]>;
949def CVTSS2SDrm : I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
950 "cvtss2sd {$src, $dst|$dst, $src}",
951 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
952 Requires<[HasSSE2]>;
953
954// Match intrinsics which expect XMM operand(s).
955def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
956 "cvtsd2si {$src, $dst|$dst, $src}",
957 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
958def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
959 "cvtsd2si {$src, $dst|$dst, $src}",
960 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
961 (load addr:$src)))]>;
962
963// Aliases for intrinsics
964def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
965 "cvttsd2si {$src, $dst|$dst, $src}",
966 [(set GR32:$dst,
967 (int_x86_sse2_cvttsd2si VR128:$src))]>;
968def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
969 "cvttsd2si {$src, $dst|$dst, $src}",
970 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
971 (load addr:$src)))]>;
972
973// Comparison instructions
974let isTwoAddress = 1 in {
975 def CMPSDrr : SDI<0xC2, MRMSrcReg,
976 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
977 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
978 def CMPSDrm : SDI<0xC2, MRMSrcMem,
979 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
980 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
981}
982
983def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
984 "ucomisd {$src2, $src1|$src1, $src2}",
985 [(X86cmp FR64:$src1, FR64:$src2)]>;
986def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
987 "ucomisd {$src2, $src1|$src1, $src2}",
988 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
989
990// Aliases to match intrinsics which expect XMM operand(s).
991let isTwoAddress = 1 in {
992 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
993 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
994 "cmp${cc}sd {$src, $dst|$dst, $src}",
995 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
996 VR128:$src, imm:$cc))]>;
997 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
998 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
999 "cmp${cc}sd {$src, $dst|$dst, $src}",
1000 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1001 (load addr:$src), imm:$cc))]>;
1002}
1003
1004def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
1005 "ucomisd {$src2, $src1|$src1, $src2}",
1006 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
1007def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
1008 "ucomisd {$src2, $src1|$src1, $src2}",
1009 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2))]>;
1010
1011def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
1012 "comisd {$src2, $src1|$src1, $src2}",
1013 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
1014def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
1015 "comisd {$src2, $src1|$src1, $src2}",
1016 [(X86comi (v2f64 VR128:$src1), (load addr:$src2))]>;
1017
1018// Aliases of packed SSE2 instructions for scalar use. These all have names that
1019// start with 'Fs'.
1020
1021// Alias instructions that map fld0 to pxor for sse.
1022def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
1023 "pxor $dst, $dst", [(set FR64:$dst, fpimm0)]>,
1024 Requires<[HasSSE2]>, TB, OpSize;
1025
1026// Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1027// disregarded.
1028def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
1029 "movapd {$src, $dst|$dst, $src}", []>;
1030
1031// Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1032// disregarded.
1033def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
1034 "movapd {$src, $dst|$dst, $src}",
1035 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
1036
1037// Alias bitwise logical operations using SSE logical ops on packed FP values.
1038let isTwoAddress = 1 in {
1039let isCommutable = 1 in {
1040 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
1041 "andpd {$src2, $dst|$dst, $src2}",
1042 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1043 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
1044 "orpd {$src2, $dst|$dst, $src2}",
1045 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1046 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
1047 "xorpd {$src2, $dst|$dst, $src2}",
1048 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1049}
1050
1051def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
1052 "andpd {$src2, $dst|$dst, $src2}",
1053 [(set FR64:$dst, (X86fand FR64:$src1,
1054 (X86loadpf64 addr:$src2)))]>;
1055def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
1056 "orpd {$src2, $dst|$dst, $src2}",
1057 [(set FR64:$dst, (X86for FR64:$src1,
1058 (X86loadpf64 addr:$src2)))]>;
1059def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
1060 "xorpd {$src2, $dst|$dst, $src2}",
1061 [(set FR64:$dst, (X86fxor FR64:$src1,
1062 (X86loadpf64 addr:$src2)))]>;
1063
1064def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1065 (ops FR64:$dst, FR64:$src1, FR64:$src2),
1066 "andnpd {$src2, $dst|$dst, $src2}", []>;
1067def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1068 (ops FR64:$dst, FR64:$src1, f128mem:$src2),
1069 "andnpd {$src2, $dst|$dst, $src2}", []>;
1070}
1071
1072/// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1073///
1074/// In addition, we also have a special variant of the scalar form here to
1075/// represent the associated intrinsic operation. This form is unlike the
1076/// plain scalar form, in that it takes an entire vector (instead of a scalar)
1077/// and leaves the top elements undefined.
1078///
1079/// These three forms can each be reg+reg or reg+mem, so there are a total of
1080/// six "instructions".
1081///
1082let isTwoAddress = 1 in {
1083multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1084 SDNode OpNode, Intrinsic F64Int,
1085 bit Commutable = 0> {
1086 // Scalar operation, reg+reg.
1087 def SDrr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
1088 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1089 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1090 let isCommutable = Commutable;
1091 }
1092
1093 // Scalar operation, reg+mem.
1094 def SDrm : SDI<opc, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
1095 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1096 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1097
1098 // Vector operation, reg+reg.
1099 def PDrr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1100 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
1101 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1102 let isCommutable = Commutable;
1103 }
1104
1105 // Vector operation, reg+mem.
1106 def PDrm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1107 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
1108 [(set VR128:$dst, (OpNode VR128:$src1, (loadv2f64 addr:$src2)))]>;
1109
1110 // Intrinsic operation, reg+reg.
1111 def SDrr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1112 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1113 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1114 let isCommutable = Commutable;
1115 }
1116
1117 // Intrinsic operation, reg+mem.
1118 def SDrm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, sdmem:$src2),
1119 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1120 [(set VR128:$dst, (F64Int VR128:$src1,
1121 sse_load_f64:$src2))]>;
1122}
1123}
1124
1125// Arithmetic instructions
1126defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1127defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1128defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1129defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1130
1131/// sse2_fp_binop_rm - Other SSE2 binops
1132///
1133/// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1134/// instructions for a full-vector intrinsic form. Operations that map
1135/// onto C operators don't use this form since they just use the plain
1136/// vector form instead of having a separate vector intrinsic form.
1137///
1138/// This provides a total of eight "instructions".
1139///
1140let isTwoAddress = 1 in {
1141multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1142 SDNode OpNode,
1143 Intrinsic F64Int,
1144 Intrinsic V2F64Int,
1145 bit Commutable = 0> {
1146
1147 // Scalar operation, reg+reg.
1148 def SDrr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
1149 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1150 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1151 let isCommutable = Commutable;
1152 }
1153
1154 // Scalar operation, reg+mem.
1155 def SDrm : SDI<opc, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
1156 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1157 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1158
1159 // Vector operation, reg+reg.
1160 def PDrr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1161 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
1162 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1163 let isCommutable = Commutable;
1164 }
1165
1166 // Vector operation, reg+mem.
1167 def PDrm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1168 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
1169 [(set VR128:$dst, (OpNode VR128:$src1, (loadv2f64 addr:$src2)))]>;
1170
1171 // Intrinsic operation, reg+reg.
1172 def SDrr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1173 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1174 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1175 let isCommutable = Commutable;
1176 }
1177
1178 // Intrinsic operation, reg+mem.
1179 def SDrm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, sdmem:$src2),
1180 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1181 [(set VR128:$dst, (F64Int VR128:$src1,
1182 sse_load_f64:$src2))]>;
1183
1184 // Vector intrinsic operation, reg+reg.
1185 def PDrr_Int : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1186 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
1187 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1188 let isCommutable = Commutable;
1189 }
1190
1191 // Vector intrinsic operation, reg+mem.
1192 def PDrm_Int : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
1193 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
1194 [(set VR128:$dst, (V2F64Int VR128:$src1, (load addr:$src2)))]>;
1195}
1196}
1197
1198defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1199 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1200defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1201 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1202
1203//===----------------------------------------------------------------------===//
1204// SSE packed FP Instructions
1205
1206// Move Instructions
1207def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1208 "movapd {$src, $dst|$dst, $src}", []>;
1209def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1210 "movapd {$src, $dst|$dst, $src}",
1211 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1212
1213def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1214 "movapd {$src, $dst|$dst, $src}",
1215 [(store (v2f64 VR128:$src), addr:$dst)]>;
1216
1217def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1218 "movupd {$src, $dst|$dst, $src}", []>;
1219def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1220 "movupd {$src, $dst|$dst, $src}",
1221 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1222def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1223 "movupd {$src, $dst|$dst, $src}",
1224 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1225
1226let isTwoAddress = 1 in {
1227 let AddedComplexity = 20 in {
1228 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1229 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
1230 "movlpd {$src2, $dst|$dst, $src2}",
1231 [(set VR128:$dst,
1232 (v2f64 (vector_shuffle VR128:$src1,
1233 (scalar_to_vector (loadf64 addr:$src2)),
1234 MOVLP_shuffle_mask)))]>;
1235 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1236 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
1237 "movhpd {$src2, $dst|$dst, $src2}",
1238 [(set VR128:$dst,
1239 (v2f64 (vector_shuffle VR128:$src1,
1240 (scalar_to_vector (loadf64 addr:$src2)),
1241 MOVHP_shuffle_mask)))]>;
1242 } // AddedComplexity
1243} // isTwoAddress
1244
1245def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
1246 "movlpd {$src, $dst|$dst, $src}",
1247 [(store (f64 (vector_extract (v2f64 VR128:$src),
1248 (iPTR 0))), addr:$dst)]>;
1249
1250// v2f64 extract element 1 is always custom lowered to unpack high to low
1251// and extract element 0 so the non-store version isn't too horrible.
1252def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
1253 "movhpd {$src, $dst|$dst, $src}",
1254 [(store (f64 (vector_extract
1255 (v2f64 (vector_shuffle VR128:$src, (undef),
1256 UNPCKH_shuffle_mask)), (iPTR 0))),
1257 addr:$dst)]>;
1258
1259// SSE2 instructions without OpSize prefix
1260def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1261 "cvtdq2ps {$src, $dst|$dst, $src}",
1262 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1263 TB, Requires<[HasSSE2]>;
1264def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1265 "cvtdq2ps {$src, $dst|$dst, $src}",
1266 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1267 (bitconvert (loadv2i64 addr:$src))))]>,
1268 TB, Requires<[HasSSE2]>;
1269
1270// SSE2 instructions with XS prefix
1271def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1272 "cvtdq2pd {$src, $dst|$dst, $src}",
1273 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1274 XS, Requires<[HasSSE2]>;
1275def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1276 "cvtdq2pd {$src, $dst|$dst, $src}",
1277 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1278 (bitconvert (loadv2i64 addr:$src))))]>,
1279 XS, Requires<[HasSSE2]>;
1280
1281def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1282 "cvtps2dq {$src, $dst|$dst, $src}",
1283 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1284def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1285 "cvtps2dq {$src, $dst|$dst, $src}",
1286 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1287 (load addr:$src)))]>;
1288// SSE2 packed instructions with XS prefix
1289def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1290 "cvttps2dq {$src, $dst|$dst, $src}",
1291 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1292 XS, Requires<[HasSSE2]>;
1293def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1294 "cvttps2dq {$src, $dst|$dst, $src}",
1295 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1296 (load addr:$src)))]>,
1297 XS, Requires<[HasSSE2]>;
1298
1299// SSE2 packed instructions with XD prefix
1300def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1301 "cvtpd2dq {$src, $dst|$dst, $src}",
1302 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1303 XD, Requires<[HasSSE2]>;
1304def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1305 "cvtpd2dq {$src, $dst|$dst, $src}",
1306 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1307 (load addr:$src)))]>,
1308 XD, Requires<[HasSSE2]>;
1309
1310def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1311 "cvttpd2dq {$src, $dst|$dst, $src}",
1312 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1313def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1314 "cvttpd2dq {$src, $dst|$dst, $src}",
1315 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1316 (load addr:$src)))]>;
1317
1318// SSE2 instructions without OpSize prefix
1319def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1320 "cvtps2pd {$src, $dst|$dst, $src}",
1321 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1322 TB, Requires<[HasSSE2]>;
1323def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
1324 "cvtps2pd {$src, $dst|$dst, $src}",
1325 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1326 (load addr:$src)))]>,
1327 TB, Requires<[HasSSE2]>;
1328
1329def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1330 "cvtpd2ps {$src, $dst|$dst, $src}",
1331 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1332def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
1333 "cvtpd2ps {$src, $dst|$dst, $src}",
1334 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1335 (load addr:$src)))]>;
1336
1337// Match intrinsics which expect XMM operand(s).
1338// Aliases for intrinsics
1339let isTwoAddress = 1 in {
1340def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1341 (ops VR128:$dst, VR128:$src1, GR32:$src2),
1342 "cvtsi2sd {$src2, $dst|$dst, $src2}",
1343 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1344 GR32:$src2))]>;
1345def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1346 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
1347 "cvtsi2sd {$src2, $dst|$dst, $src2}",
1348 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1349 (loadi32 addr:$src2)))]>;
1350def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1351 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1352 "cvtsd2ss {$src2, $dst|$dst, $src2}",
1353 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1354 VR128:$src2))]>;
1355def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1356 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
1357 "cvtsd2ss {$src2, $dst|$dst, $src2}",
1358 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1359 (load addr:$src2)))]>;
1360def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1361 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1362 "cvtss2sd {$src2, $dst|$dst, $src2}",
1363 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1364 VR128:$src2))]>, XS,
1365 Requires<[HasSSE2]>;
1366def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1367 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
1368 "cvtss2sd {$src2, $dst|$dst, $src2}",
1369 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1370 (load addr:$src2)))]>, XS,
1371 Requires<[HasSSE2]>;
1372}
1373
1374// Arithmetic
1375
1376/// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1377///
1378/// In addition, we also have a special variant of the scalar form here to
1379/// represent the associated intrinsic operation. This form is unlike the
1380/// plain scalar form, in that it takes an entire vector (instead of a
1381/// scalar) and leaves the top elements undefined.
1382///
1383/// And, we have a special variant form for a full-vector intrinsic form.
1384///
1385/// These four forms can each have a reg or a mem operand, so there are a
1386/// total of eight "instructions".
1387///
1388multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1389 SDNode OpNode,
1390 Intrinsic F64Int,
1391 Intrinsic V2F64Int,
1392 bit Commutable = 0> {
1393 // Scalar operation, reg.
1394 def SDr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src),
1395 !strconcat(OpcodeStr, "sd {$src, $dst|$dst, $src}"),
1396 [(set FR64:$dst, (OpNode FR64:$src))]> {
1397 let isCommutable = Commutable;
1398 }
1399
1400 // Scalar operation, mem.
1401 def SDm : SDI<opc, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
1402 !strconcat(OpcodeStr, "sd {$src, $dst|$dst, $src}"),
1403 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1404
1405 // Vector operation, reg.
1406 def PDr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1407 !strconcat(OpcodeStr, "pd {$src, $dst|$dst, $src}"),
1408 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1409 let isCommutable = Commutable;
1410 }
1411
1412 // Vector operation, mem.
1413 def PDm : PDI<opc, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1414 !strconcat(OpcodeStr, "pd {$src, $dst|$dst, $src}"),
1415 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))]>;
1416
1417 // Intrinsic operation, reg.
1418 def SDr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1419 !strconcat(OpcodeStr, "sd {$src, $dst|$dst, $src}"),
1420 [(set VR128:$dst, (F64Int VR128:$src))]> {
1421 let isCommutable = Commutable;
1422 }
1423
1424 // Intrinsic operation, mem.
1425 def SDm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, sdmem:$src),
1426 !strconcat(OpcodeStr, "sd {$src, $dst|$dst, $src}"),
1427 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1428
1429 // Vector intrinsic operation, reg
1430 def PDr_Int : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1431 !strconcat(OpcodeStr, "pd {$src, $dst|$dst, $src}"),
1432 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1433 let isCommutable = Commutable;
1434 }
1435
1436 // Vector intrinsic operation, mem
1437 def PDm_Int : PDI<opc, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1438 !strconcat(OpcodeStr, "pd {$src, $dst|$dst, $src}"),
1439 [(set VR128:$dst, (V2F64Int (load addr:$src)))]>;
1440}
1441
1442// Square root.
1443defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1444 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1445
1446// There is no f64 version of the reciprocal approximation instructions.
1447
1448// Logical
1449let isTwoAddress = 1 in {
1450 let isCommutable = 1 in {
1451 def ANDPDrr : PDI<0x54, MRMSrcReg,
1452 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1453 "andpd {$src2, $dst|$dst, $src2}",
1454 [(set VR128:$dst,
1455 (and (bc_v2i64 (v2f64 VR128:$src1)),
1456 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1457 def ORPDrr : PDI<0x56, MRMSrcReg,
1458 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1459 "orpd {$src2, $dst|$dst, $src2}",
1460 [(set VR128:$dst,
1461 (or (bc_v2i64 (v2f64 VR128:$src1)),
1462 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1463 def XORPDrr : PDI<0x57, MRMSrcReg,
1464 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1465 "xorpd {$src2, $dst|$dst, $src2}",
1466 [(set VR128:$dst,
1467 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1468 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1469 }
1470
1471 def ANDPDrm : PDI<0x54, MRMSrcMem,
1472 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1473 "andpd {$src2, $dst|$dst, $src2}",
1474 [(set VR128:$dst,
1475 (and (bc_v2i64 (v2f64 VR128:$src1)),
1476 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1477 def ORPDrm : PDI<0x56, MRMSrcMem,
1478 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1479 "orpd {$src2, $dst|$dst, $src2}",
1480 [(set VR128:$dst,
1481 (or (bc_v2i64 (v2f64 VR128:$src1)),
1482 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1483 def XORPDrm : PDI<0x57, MRMSrcMem,
1484 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1485 "xorpd {$src2, $dst|$dst, $src2}",
1486 [(set VR128:$dst,
1487 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1488 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1489 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1490 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1491 "andnpd {$src2, $dst|$dst, $src2}",
1492 [(set VR128:$dst,
1493 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1494 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1495 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1496 (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1497 "andnpd {$src2, $dst|$dst, $src2}",
1498 [(set VR128:$dst,
1499 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1500 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1501}
1502
1503let isTwoAddress = 1 in {
1504 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1505 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1506 "cmp${cc}pd {$src, $dst|$dst, $src}",
1507 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1508 VR128:$src, imm:$cc))]>;
1509 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1510 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1511 "cmp${cc}pd {$src, $dst|$dst, $src}",
1512 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1513 (load addr:$src), imm:$cc))]>;
1514}
1515
1516// Shuffle and unpack instructions
1517let isTwoAddress = 1 in {
1518 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1519 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1520 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1521 [(set VR128:$dst, (v2f64 (vector_shuffle
1522 VR128:$src1, VR128:$src2,
1523 SHUFP_shuffle_mask:$src3)))]>;
1524 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1525 (ops VR128:$dst, VR128:$src1,
1526 f128mem:$src2, i8imm:$src3),
1527 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1528 [(set VR128:$dst,
1529 (v2f64 (vector_shuffle
1530 VR128:$src1, (load addr:$src2),
1531 SHUFP_shuffle_mask:$src3)))]>;
1532
1533 let AddedComplexity = 10 in {
1534 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1535 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1536 "unpckhpd {$src2, $dst|$dst, $src2}",
1537 [(set VR128:$dst,
1538 (v2f64 (vector_shuffle
1539 VR128:$src1, VR128:$src2,
1540 UNPCKH_shuffle_mask)))]>;
1541 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1542 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1543 "unpckhpd {$src2, $dst|$dst, $src2}",
1544 [(set VR128:$dst,
1545 (v2f64 (vector_shuffle
1546 VR128:$src1, (load addr:$src2),
1547 UNPCKH_shuffle_mask)))]>;
1548
1549 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1550 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1551 "unpcklpd {$src2, $dst|$dst, $src2}",
1552 [(set VR128:$dst,
1553 (v2f64 (vector_shuffle
1554 VR128:$src1, VR128:$src2,
1555 UNPCKL_shuffle_mask)))]>;
1556 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1557 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1558 "unpcklpd {$src2, $dst|$dst, $src2}",
1559 [(set VR128:$dst,
1560 (v2f64 (vector_shuffle
1561 VR128:$src1, (load addr:$src2),
1562 UNPCKL_shuffle_mask)))]>;
1563 } // AddedComplexity
1564} // isTwoAddress
1565
1566
1567//===----------------------------------------------------------------------===//
1568// SSE integer instructions
1569
1570// Move Instructions
1571def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1572 "movdqa {$src, $dst|$dst, $src}", []>;
1573def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1574 "movdqa {$src, $dst|$dst, $src}",
1575 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1576def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1577 "movdqa {$src, $dst|$dst, $src}",
1578 [(store (v2i64 VR128:$src), addr:$dst)]>;
1579def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1580 "movdqu {$src, $dst|$dst, $src}",
1581 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1582 XS, Requires<[HasSSE2]>;
1583def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1584 "movdqu {$src, $dst|$dst, $src}",
1585 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1586 XS, Requires<[HasSSE2]>;
1587
1588
1589let isTwoAddress = 1 in {
1590
1591multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1592 bit Commutable = 0> {
1593 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1594 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1595 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1596 let isCommutable = Commutable;
1597 }
1598 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1599 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1600 [(set VR128:$dst, (IntId VR128:$src1,
1601 (bitconvert (loadv2i64 addr:$src2))))]>;
1602}
1603
1604multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1605 string OpcodeStr, Intrinsic IntId> {
1606 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1607 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1608 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1609 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1610 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1611 [(set VR128:$dst, (IntId VR128:$src1,
1612 (bitconvert (loadv2i64 addr:$src2))))]>;
1613 def ri : PDIi8<opc2, ImmForm, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1614 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1615 [(set VR128:$dst, (IntId VR128:$src1,
1616 (scalar_to_vector (i32 imm:$src2))))]>;
1617}
1618
1619
1620/// PDI_binop_rm - Simple SSE2 binary operator.
1621multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1622 ValueType OpVT, bit Commutable = 0> {
1623 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1624 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1625 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1626 let isCommutable = Commutable;
1627 }
1628 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1629 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1630 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1631 (bitconvert (loadv2i64 addr:$src2)))))]>;
1632}
1633
1634/// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1635///
1636/// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1637/// to collapse (bitconvert VT to VT) into its operand.
1638///
1639multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1640 bit Commutable = 0> {
1641 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1642 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1643 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1644 let isCommutable = Commutable;
1645 }
1646 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1647 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1648 [(set VR128:$dst, (OpNode VR128:$src1,(loadv2i64 addr:$src2)))]>;
1649}
1650
1651} // isTwoAddress
1652
1653// 128-bit Integer Arithmetic
1654
1655defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1656defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1657defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1658defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1659
1660defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1661defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1662defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1663defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1664
1665defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1666defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1667defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1668defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1669
1670defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1671defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1672defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1673defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1674
1675defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1676
1677defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1678defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1679defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1680
1681defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1682
1683defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1684defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1685
1686
1687defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1688defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1689defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1690defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1691defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1692
1693
1694defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_sse2_psll_w>;
1695defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_sse2_psll_d>;
1696defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_sse2_psll_q>;
1697
1698defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_sse2_psrl_w>;
1699defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_sse2_psrl_d>;
1700defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_sse2_psrl_q>;
1701
1702defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_sse2_psra_w>;
1703defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_sse2_psra_d>;
1704// PSRAQ doesn't exist in SSE[1-3].
1705
1706// 128-bit logical shifts.
1707let isTwoAddress = 1 in {
1708 def PSLLDQri : PDIi8<0x73, MRM7r,
1709 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1710 "pslldq {$src2, $dst|$dst, $src2}", []>;
1711 def PSRLDQri : PDIi8<0x73, MRM3r,
1712 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1713 "psrldq {$src2, $dst|$dst, $src2}", []>;
1714 // PSRADQri doesn't exist in SSE[1-3].
1715}
1716
1717let Predicates = [HasSSE2] in {
1718 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1719 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1720 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1721 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1722 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1723 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1724}
1725
1726// Logical
1727defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1728defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1729defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1730
1731let isTwoAddress = 1 in {
1732 def PANDNrr : PDI<0xDF, MRMSrcReg,
1733 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1734 "pandn {$src2, $dst|$dst, $src2}",
1735 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1736 VR128:$src2)))]>;
1737
1738 def PANDNrm : PDI<0xDF, MRMSrcMem,
1739 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1740 "pandn {$src2, $dst|$dst, $src2}",
1741 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1742 (load addr:$src2))))]>;
1743}
1744
1745// SSE2 Integer comparison
1746defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1747defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1748defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1749defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1750defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1751defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1752
1753// Pack instructions
1754defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1755defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1756defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1757
1758// Shuffle and unpack instructions
1759def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1760 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1761 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1762 [(set VR128:$dst, (v4i32 (vector_shuffle
1763 VR128:$src1, (undef),
1764 PSHUFD_shuffle_mask:$src2)))]>;
1765def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1766 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1767 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1768 [(set VR128:$dst, (v4i32 (vector_shuffle
1769 (bc_v4i32(loadv2i64 addr:$src1)),
1770 (undef),
1771 PSHUFD_shuffle_mask:$src2)))]>;
1772
1773// SSE2 with ImmT == Imm8 and XS prefix.
1774def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1775 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1776 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1777 [(set VR128:$dst, (v8i16 (vector_shuffle
1778 VR128:$src1, (undef),
1779 PSHUFHW_shuffle_mask:$src2)))]>,
1780 XS, Requires<[HasSSE2]>;
1781def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1782 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1783 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1784 [(set VR128:$dst, (v8i16 (vector_shuffle
1785 (bc_v8i16 (loadv2i64 addr:$src1)),
1786 (undef),
1787 PSHUFHW_shuffle_mask:$src2)))]>,
1788 XS, Requires<[HasSSE2]>;
1789
1790// SSE2 with ImmT == Imm8 and XD prefix.
1791def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1792 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1793 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1794 [(set VR128:$dst, (v8i16 (vector_shuffle
1795 VR128:$src1, (undef),
1796 PSHUFLW_shuffle_mask:$src2)))]>,
1797 XD, Requires<[HasSSE2]>;
1798def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1799 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1800 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1801 [(set VR128:$dst, (v8i16 (vector_shuffle
1802 (bc_v8i16 (loadv2i64 addr:$src1)),
1803 (undef),
1804 PSHUFLW_shuffle_mask:$src2)))]>,
1805 XD, Requires<[HasSSE2]>;
1806
1807
1808let isTwoAddress = 1 in {
1809 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1810 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1811 "punpcklbw {$src2, $dst|$dst, $src2}",
1812 [(set VR128:$dst,
1813 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1814 UNPCKL_shuffle_mask)))]>;
1815 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1816 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1817 "punpcklbw {$src2, $dst|$dst, $src2}",
1818 [(set VR128:$dst,
1819 (v16i8 (vector_shuffle VR128:$src1,
1820 (bc_v16i8 (loadv2i64 addr:$src2)),
1821 UNPCKL_shuffle_mask)))]>;
1822 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1823 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1824 "punpcklwd {$src2, $dst|$dst, $src2}",
1825 [(set VR128:$dst,
1826 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1827 UNPCKL_shuffle_mask)))]>;
1828 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1829 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1830 "punpcklwd {$src2, $dst|$dst, $src2}",
1831 [(set VR128:$dst,
1832 (v8i16 (vector_shuffle VR128:$src1,
1833 (bc_v8i16 (loadv2i64 addr:$src2)),
1834 UNPCKL_shuffle_mask)))]>;
1835 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1836 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1837 "punpckldq {$src2, $dst|$dst, $src2}",
1838 [(set VR128:$dst,
1839 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1840 UNPCKL_shuffle_mask)))]>;
1841 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1842 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1843 "punpckldq {$src2, $dst|$dst, $src2}",
1844 [(set VR128:$dst,
1845 (v4i32 (vector_shuffle VR128:$src1,
1846 (bc_v4i32 (loadv2i64 addr:$src2)),
1847 UNPCKL_shuffle_mask)))]>;
1848 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1849 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1850 "punpcklqdq {$src2, $dst|$dst, $src2}",
1851 [(set VR128:$dst,
1852 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1853 UNPCKL_shuffle_mask)))]>;
1854 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1855 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1856 "punpcklqdq {$src2, $dst|$dst, $src2}",
1857 [(set VR128:$dst,
1858 (v2i64 (vector_shuffle VR128:$src1,
1859 (loadv2i64 addr:$src2),
1860 UNPCKL_shuffle_mask)))]>;
1861
1862 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1863 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1864 "punpckhbw {$src2, $dst|$dst, $src2}",
1865 [(set VR128:$dst,
1866 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1867 UNPCKH_shuffle_mask)))]>;
1868 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1869 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1870 "punpckhbw {$src2, $dst|$dst, $src2}",
1871 [(set VR128:$dst,
1872 (v16i8 (vector_shuffle VR128:$src1,
1873 (bc_v16i8 (loadv2i64 addr:$src2)),
1874 UNPCKH_shuffle_mask)))]>;
1875 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1876 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1877 "punpckhwd {$src2, $dst|$dst, $src2}",
1878 [(set VR128:$dst,
1879 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1880 UNPCKH_shuffle_mask)))]>;
1881 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1882 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1883 "punpckhwd {$src2, $dst|$dst, $src2}",
1884 [(set VR128:$dst,
1885 (v8i16 (vector_shuffle VR128:$src1,
1886 (bc_v8i16 (loadv2i64 addr:$src2)),
1887 UNPCKH_shuffle_mask)))]>;
1888 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1889 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1890 "punpckhdq {$src2, $dst|$dst, $src2}",
1891 [(set VR128:$dst,
1892 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1893 UNPCKH_shuffle_mask)))]>;
1894 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1895 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1896 "punpckhdq {$src2, $dst|$dst, $src2}",
1897 [(set VR128:$dst,
1898 (v4i32 (vector_shuffle VR128:$src1,
1899 (bc_v4i32 (loadv2i64 addr:$src2)),
1900 UNPCKH_shuffle_mask)))]>;
1901 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1902 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1903 "punpckhqdq {$src2, $dst|$dst, $src2}",
1904 [(set VR128:$dst,
1905 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1906 UNPCKH_shuffle_mask)))]>;
1907 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1908 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1909 "punpckhqdq {$src2, $dst|$dst, $src2}",
1910 [(set VR128:$dst,
1911 (v2i64 (vector_shuffle VR128:$src1,
1912 (loadv2i64 addr:$src2),
1913 UNPCKH_shuffle_mask)))]>;
1914}
1915
1916// Extract / Insert
1917def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
1918 (ops GR32:$dst, VR128:$src1, i32i8imm:$src2),
1919 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1920 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
1921 (iPTR imm:$src2)))]>;
1922let isTwoAddress = 1 in {
1923 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
1924 (ops VR128:$dst, VR128:$src1,
1925 GR32:$src2, i32i8imm:$src3),
1926 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1927 [(set VR128:$dst,
1928 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1929 GR32:$src2, (iPTR imm:$src3))))]>;
1930 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
1931 (ops VR128:$dst, VR128:$src1,
1932 i16mem:$src2, i32i8imm:$src3),
1933 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1934 [(set VR128:$dst,
1935 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1936 (i32 (anyext (loadi16 addr:$src2))),
1937 (iPTR imm:$src3))))]>;
1938}
1939
1940// Mask creation
1941def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1942 "pmovmskb {$src, $dst|$dst, $src}",
1943 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
1944
1945// Conditional store
1946def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (ops VR128:$src, VR128:$mask),
1947 "maskmovdqu {$mask, $src|$src, $mask}",
1948 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
1949 Imp<[EDI],[]>;
1950
1951// Non-temporal stores
1952def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1953 "movntpd {$src, $dst|$dst, $src}",
1954 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
1955def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1956 "movntdq {$src, $dst|$dst, $src}",
1957 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
1958def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, GR32:$src),
1959 "movnti {$src, $dst|$dst, $src}",
1960 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
1961 TB, Requires<[HasSSE2]>;
1962
1963// Flush cache
1964def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
1965 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
1966 TB, Requires<[HasSSE2]>;
1967
1968// Load, store, and memory fence
1969def LFENCE : I<0xAE, MRM5m, (ops),
1970 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
1971def MFENCE : I<0xAE, MRM6m, (ops),
1972 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
1973
1974
1975// Alias instructions that map zero vector to pxor / xorp* for sse.
1976// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1977let isReMaterializable = 1 in
1978 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
1979 "pcmpeqd $dst, $dst",
1980 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
1981
1982// FR64 to 128-bit vector conversion.
1983def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
1984 "movsd {$src, $dst|$dst, $src}",
1985 [(set VR128:$dst,
1986 (v2f64 (scalar_to_vector FR64:$src)))]>;
1987def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1988 "movsd {$src, $dst|$dst, $src}",
1989 [(set VR128:$dst,
1990 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
1991
1992def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
1993 "movd {$src, $dst|$dst, $src}",
1994 [(set VR128:$dst,
1995 (v4i32 (scalar_to_vector GR32:$src)))]>;
1996def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1997 "movd {$src, $dst|$dst, $src}",
1998 [(set VR128:$dst,
1999 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2000
2001def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (ops FR32:$dst, GR32:$src),
2002 "movd {$src, $dst|$dst, $src}",
2003 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2004
2005def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
2006 "movd {$src, $dst|$dst, $src}",
2007 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2008
2009// SSE2 instructions with XS prefix
2010def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2011 "movq {$src, $dst|$dst, $src}",
2012 [(set VR128:$dst,
2013 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2014 Requires<[HasSSE2]>;
2015def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
2016 "movq {$src, $dst|$dst, $src}",
2017 [(store (i64 (vector_extract (v2i64 VR128:$src),
2018 (iPTR 0))), addr:$dst)]>;
2019
2020// FIXME: may not be able to eliminate this movss with coalescing the src and
2021// dest register classes are different. We really want to write this pattern
2022// like this:
2023// def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2024// (f32 FR32:$src)>;
2025def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
2026 "movsd {$src, $dst|$dst, $src}",
2027 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2028 (iPTR 0)))]>;
2029def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
2030 "movsd {$src, $dst|$dst, $src}",
2031 [(store (f64 (vector_extract (v2f64 VR128:$src),
2032 (iPTR 0))), addr:$dst)]>;
2033def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, VR128:$src),
2034 "movd {$src, $dst|$dst, $src}",
2035 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2036 (iPTR 0)))]>;
2037def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
2038 "movd {$src, $dst|$dst, $src}",
2039 [(store (i32 (vector_extract (v4i32 VR128:$src),
2040 (iPTR 0))), addr:$dst)]>;
2041
2042def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, FR32:$src),
2043 "movd {$src, $dst|$dst, $src}",
2044 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2045def MOVSS2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, FR32:$src),
2046 "movd {$src, $dst|$dst, $src}",
2047 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2048
2049
2050// Move to lower bits of a VR128, leaving upper bits alone.
2051// Three operand (but two address) aliases.
2052let isTwoAddress = 1 in {
2053 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2054 (ops VR128:$dst, VR128:$src1, FR64:$src2),
2055 "movsd {$src2, $dst|$dst, $src2}", []>;
2056
2057 let AddedComplexity = 15 in
2058 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2059 (ops VR128:$dst, VR128:$src1, VR128:$src2),
2060 "movsd {$src2, $dst|$dst, $src2}",
2061 [(set VR128:$dst,
2062 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2063 MOVL_shuffle_mask)))]>;
2064}
2065
2066// Store / copy lower 64-bits of a XMM register.
2067def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
2068 "movq {$src, $dst|$dst, $src}",
2069 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2070
2071// Move to lower bits of a VR128 and zeroing upper bits.
2072// Loading from memory automatically zeroing upper bits.
2073let AddedComplexity = 20 in
2074 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2075 "movsd {$src, $dst|$dst, $src}",
2076 [(set VR128:$dst,
2077 (v2f64 (vector_shuffle immAllZerosV,
2078 (v2f64 (scalar_to_vector
2079 (loadf64 addr:$src))),
2080 MOVL_shuffle_mask)))]>;
2081
2082let AddedComplexity = 15 in
2083// movd / movq to XMM register zero-extends
2084def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
2085 "movd {$src, $dst|$dst, $src}",
2086 [(set VR128:$dst,
2087 (v4i32 (vector_shuffle immAllZerosV,
2088 (v4i32 (scalar_to_vector GR32:$src)),
2089 MOVL_shuffle_mask)))]>;
2090let AddedComplexity = 20 in
2091def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2092 "movd {$src, $dst|$dst, $src}",
2093 [(set VR128:$dst,
2094 (v4i32 (vector_shuffle immAllZerosV,
2095 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
2096 MOVL_shuffle_mask)))]>;
2097
2098// Moving from XMM to XMM but still clear upper 64 bits.
2099let AddedComplexity = 15 in
2100def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2101 "movq {$src, $dst|$dst, $src}",
2102 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>,
2103 XS, Requires<[HasSSE2]>;
2104let AddedComplexity = 20 in
2105def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2106 "movq {$src, $dst|$dst, $src}",
2107 [(set VR128:$dst, (int_x86_sse2_movl_dq
2108 (bitconvert (loadv2i64 addr:$src))))]>,
2109 XS, Requires<[HasSSE2]>;
2110
2111
2112//===----------------------------------------------------------------------===//
2113// SSE3 Instructions
2114//===----------------------------------------------------------------------===//
2115
2116// SSE3 Instruction Templates:
2117//
2118// S3I - SSE3 instructions with TB and OpSize prefixes.
2119// S3SI - SSE3 instructions with XS prefix.
2120// S3DI - SSE3 instructions with XD prefix.
2121
2122class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
2123 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
2124class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
2125 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
2126class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
2127 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
2128
2129// Move Instructions
2130def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2131 "movshdup {$src, $dst|$dst, $src}",
2132 [(set VR128:$dst, (v4f32 (vector_shuffle
2133 VR128:$src, (undef),
2134 MOVSHDUP_shuffle_mask)))]>;
2135def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
2136 "movshdup {$src, $dst|$dst, $src}",
2137 [(set VR128:$dst, (v4f32 (vector_shuffle
2138 (loadv4f32 addr:$src), (undef),
2139 MOVSHDUP_shuffle_mask)))]>;
2140
2141def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2142 "movsldup {$src, $dst|$dst, $src}",
2143 [(set VR128:$dst, (v4f32 (vector_shuffle
2144 VR128:$src, (undef),
2145 MOVSLDUP_shuffle_mask)))]>;
2146def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
2147 "movsldup {$src, $dst|$dst, $src}",
2148 [(set VR128:$dst, (v4f32 (vector_shuffle
2149 (loadv4f32 addr:$src), (undef),
2150 MOVSLDUP_shuffle_mask)))]>;
2151
2152def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2153 "movddup {$src, $dst|$dst, $src}",
2154 [(set VR128:$dst, (v2f64 (vector_shuffle
2155 VR128:$src, (undef),
2156 SSE_splat_lo_mask)))]>;
2157def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2158 "movddup {$src, $dst|$dst, $src}",
2159 [(set VR128:$dst,
2160 (v2f64 (vector_shuffle
2161 (scalar_to_vector (loadf64 addr:$src)),
2162 (undef),
2163 SSE_splat_lo_mask)))]>;
2164
2165// Arithmetic
2166let isTwoAddress = 1 in {
2167 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2168 (ops VR128:$dst, VR128:$src1, VR128:$src2),
2169 "addsubps {$src2, $dst|$dst, $src2}",
2170 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2171 VR128:$src2))]>;
2172 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2173 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
2174 "addsubps {$src2, $dst|$dst, $src2}",
2175 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2176 (load addr:$src2)))]>;
2177 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2178 (ops VR128:$dst, VR128:$src1, VR128:$src2),
2179 "addsubpd {$src2, $dst|$dst, $src2}",
2180 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2181 VR128:$src2))]>;
2182 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2183 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
2184 "addsubpd {$src2, $dst|$dst, $src2}",
2185 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2186 (load addr:$src2)))]>;
2187}
2188
2189def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
2190 "lddqu {$src, $dst|$dst, $src}",
2191 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2192
2193// Horizontal ops
2194class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2195 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2196 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2197 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2198class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2199 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
2200 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2201 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
2202class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2203 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2204 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2205 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2206class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2207 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
2208 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2209 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
2210
2211let isTwoAddress = 1 in {
2212 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2213 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2214 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2215 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2216 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2217 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2218 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2219 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2220}
2221
2222// Thread synchronization
2223def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
2224 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2225def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
2226 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2227
2228// vector_shuffle v1, <undef> <1, 1, 3, 3>
2229let AddedComplexity = 15 in
2230def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2231 MOVSHDUP_shuffle_mask)),
2232 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2233let AddedComplexity = 20 in
2234def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2235 MOVSHDUP_shuffle_mask)),
2236 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2237
2238// vector_shuffle v1, <undef> <0, 0, 2, 2>
2239let AddedComplexity = 15 in
2240 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2241 MOVSLDUP_shuffle_mask)),
2242 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2243let AddedComplexity = 20 in
2244 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2245 MOVSLDUP_shuffle_mask)),
2246 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2247
2248//===----------------------------------------------------------------------===//
2249// SSSE3 Instructions
2250//===----------------------------------------------------------------------===//
2251
2252// SSE3 Instruction Templates:
2253//
2254// SS38I - SSSE3 instructions with T8 and OpSize prefixes.
2255// SS3AI - SSSE3 instructions with TA and OpSize prefixes.
2256
2257class SS38I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
2258 : I<o, F, ops, asm, pattern>, T8, OpSize, Requires<[HasSSSE3]>;
2259class SS3AI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
2260 : I<o, F, ops, asm, pattern>, TA, OpSize, Requires<[HasSSSE3]>;
2261
2262/// SS3I_binop_rm_int - Simple SSSE3 binary operatr whose type is v2i64.
2263let isTwoAddress = 1 in {
2264 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2265 bit Commutable = 0> {
2266 def rr : SS38I<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2267 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2268 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
2269 let isCommutable = Commutable;
2270 }
2271 def rm : SS38I<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
2272 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2273 [(set VR128:$dst,
2274 (IntId VR128:$src1,
2275 (bitconvert (loadv2i64 addr:$src2))))]>;
2276 }
2277}
2278
2279defm PMULHRSW128 : SS3I_binop_rm_int<0x0B, "pmulhrsw",
2280 int_x86_ssse3_pmulhrsw_128, 1>;
2281
2282//===----------------------------------------------------------------------===//
2283// Non-Instruction Patterns
2284//===----------------------------------------------------------------------===//
2285
2286// 128-bit vector undef's.
2287def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2288def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2289def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2290def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2291def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2292
2293// 128-bit vector all zero's.
2294def : Pat<(v16i8 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2295def : Pat<(v8i16 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2296def : Pat<(v4i32 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2297def : Pat<(v2i64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2298def : Pat<(v2f64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2299
2300// 128-bit vector all one's.
2301def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2302def : Pat<(v8i16 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2303def : Pat<(v4i32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2304def : Pat<(v2i64 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2305def : Pat<(v4f32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE1]>;
2306
2307// Store 128-bit integer vector values.
2308def : Pat<(store (v16i8 VR128:$src), addr:$dst),
2309 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2310def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2311 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2312def : Pat<(store (v4i32 VR128:$src), addr:$dst),
2313 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2314
2315// Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
2316// 16-bits matter.
2317def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2318 Requires<[HasSSE2]>;
2319def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2320 Requires<[HasSSE2]>;
2321
2322// bit_convert
2323let Predicates = [HasSSE2] in {
2324 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2325 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2326 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2327 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2328 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2329 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2330 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2331 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2332 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2333 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2334 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2335 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2336 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2337 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2338 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2339 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2340 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2341 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2342 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2343 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2344 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2345 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2346 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2347 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2348 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2349 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2350 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2351 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2352 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2353 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2354}
2355
2356// Move scalar to XMM zero-extended
2357// movd to XMM register zero-extends
2358let AddedComplexity = 15 in {
2359def : Pat<(v8i16 (vector_shuffle immAllZerosV,
2360 (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2361 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2362def : Pat<(v16i8 (vector_shuffle immAllZerosV,
2363 (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2364 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2365// Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2366def : Pat<(v2f64 (vector_shuffle immAllZerosV,
2367 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
2368 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2369def : Pat<(v4f32 (vector_shuffle immAllZerosV,
2370 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
2371 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2372}
2373
2374// Splat v2f64 / v2i64
2375let AddedComplexity = 10 in {
2376def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2377 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2378def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2379 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2380def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2381 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2382def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2383 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2384}
2385
2386// Splat v4f32
2387def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2388 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
2389 Requires<[HasSSE1]>;
2390
2391// Special unary SHUFPSrri case.
2392// FIXME: when we want non two-address code, then we should use PSHUFD?
2393def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
2394 SHUFP_unary_shuffle_mask:$sm),
2395 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2396 Requires<[HasSSE1]>;
2397// Unary v4f32 shuffle with PSHUF* in order to fold a load.
2398def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
2399 SHUFP_unary_shuffle_mask:$sm),
2400 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2401 Requires<[HasSSE2]>;
2402// Special binary v4i32 shuffle cases with SHUFPS.
2403def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
2404 PSHUFD_binary_shuffle_mask:$sm),
2405 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2406 Requires<[HasSSE2]>;
2407def : Pat<(vector_shuffle (v4i32 VR128:$src1),
2408 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
2409 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2410 Requires<[HasSSE2]>;
2411
2412// vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2413let AddedComplexity = 10 in {
2414def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2415 UNPCKL_v_undef_shuffle_mask)),
2416 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2417def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2418 UNPCKL_v_undef_shuffle_mask)),
2419 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2420def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2421 UNPCKL_v_undef_shuffle_mask)),
2422 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2423def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2424 UNPCKL_v_undef_shuffle_mask)),
2425 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2426}
2427
2428// vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2429let AddedComplexity = 10 in {
2430def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2431 UNPCKH_v_undef_shuffle_mask)),
2432 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2433def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2434 UNPCKH_v_undef_shuffle_mask)),
2435 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2436def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2437 UNPCKH_v_undef_shuffle_mask)),
2438 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2439def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2440 UNPCKH_v_undef_shuffle_mask)),
2441 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2442}
2443
2444let AddedComplexity = 15 in {
2445// vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2446def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2447 MOVHP_shuffle_mask)),
2448 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2449
2450// vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2451def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2452 MOVHLPS_shuffle_mask)),
2453 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2454
2455// vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2456def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2457 MOVHLPS_v_undef_shuffle_mask)),
2458 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2459def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2460 MOVHLPS_v_undef_shuffle_mask)),
2461 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2462}
2463
2464let AddedComplexity = 20 in {
2465// vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2466// vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2467def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2468 MOVLP_shuffle_mask)),
2469 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2470def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2471 MOVLP_shuffle_mask)),
2472 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2473def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2474 MOVHP_shuffle_mask)),
2475 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2476def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2477 MOVHP_shuffle_mask)),
2478 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2479
2480def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2481 MOVLP_shuffle_mask)),
2482 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2483def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2484 MOVLP_shuffle_mask)),
2485 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2486def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2487 MOVHP_shuffle_mask)),
2488 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2489def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2490 MOVLP_shuffle_mask)),
2491 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2492}
2493
2494let AddedComplexity = 15 in {
2495// Setting the lowest element in the vector.
2496def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2497 MOVL_shuffle_mask)),
2498 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2499def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2500 MOVL_shuffle_mask)),
2501 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2502
2503// vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2504def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2505 MOVLP_shuffle_mask)),
2506 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2507def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2508 MOVLP_shuffle_mask)),
2509 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2510}
2511
2512// Set lowest element and zero upper elements.
2513let AddedComplexity = 20 in
2514def : Pat<(bc_v2i64 (vector_shuffle immAllZerosV,
2515 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2516 MOVL_shuffle_mask)),
2517 (MOVZQI2PQIrm addr:$src)>, Requires<[HasSSE2]>;
2518
2519// FIXME: Temporary workaround since 2-wide shuffle is broken.
2520def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2521 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2522def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2523 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2524def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2525 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2526def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2527 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2528 Requires<[HasSSE2]>;
2529def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2530 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2531 Requires<[HasSSE2]>;
2532def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2533 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2534def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2535 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2536def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2537 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2538def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2539 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2540def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2541 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2542def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2543 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2544def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2545 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2546def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2547 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2548
2549// Some special case pandn patterns.
2550def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2551 VR128:$src2)),
2552 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2553def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2554 VR128:$src2)),
2555 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2556def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2557 VR128:$src2)),
2558 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2559
2560def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2561 (load addr:$src2))),
2562 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2563def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2564 (load addr:$src2))),
2565 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2566def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2567 (load addr:$src2))),
2568 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2569
2570// Unaligned load
2571def : Pat<(v4f32 (X86loadu addr:$src)), (MOVUPSrm addr:$src)>,
2572 Requires<[HasSSE1]>;