blob: 598591c0fcb0349da627b68f631283d71c865b05 [file] [log] [blame]
Che-Liang Chiou3f409f72010-11-17 08:08:49 +00001; RUN: llc < %s -march=ptx | FileCheck %s
2
Che-Liang Chioufd8978b2011-03-02 03:20:28 +00003define ptx_device i16 @t1_u16(i16 %x, i16 %y) {
4; CHECK: add.u16 rh0, rh1, rh2;
5; CHECK-NEXT: ret;
6 %z = add i16 %x, %y
7 ret i16 %z
8}
9
10define ptx_device i32 @t1_u32(i32 %x, i32 %y) {
11; CHECK: add.u32 r0, r1, r2;
12; CHECK-NEXT: ret;
Che-Liang Chiou3f409f72010-11-17 08:08:49 +000013 %z = add i32 %x, %y
Che-Liang Chiou3f409f72010-11-17 08:08:49 +000014 ret i32 %z
15}
16
Che-Liang Chioufd8978b2011-03-02 03:20:28 +000017define ptx_device i64 @t1_u64(i64 %x, i64 %y) {
18; CHECK: add.u64 rd0, rd1, rd2;
19; CHECK-NEXT: ret;
20 %z = add i64 %x, %y
21 ret i64 %z
Che-Liang Chiou3f409f72010-11-17 08:08:49 +000022}
Che-Liang Chiouf7172022011-02-28 06:34:09 +000023
Che-Liang Chioufd8978b2011-03-02 03:20:28 +000024define ptx_device float @t1_f32(float %x, float %y) {
Che-Liang Chiouf7172022011-02-28 06:34:09 +000025; CHECK: add.f32 f0, f1, f2
26; CHECK-NEXT: ret;
27 %z = fadd float %x, %y
28 ret float %z
29}
30
Che-Liang Chioufd8978b2011-03-02 03:20:28 +000031define ptx_device double @t1_f64(double %x, double %y) {
32; CHECK: add.f64 fd0, fd1, fd2
33; CHECK-NEXT: ret;
34 %z = fadd double %x, %y
35 ret double %z
36}
37
38define ptx_device i16 @t2_u16(i16 %x) {
39; CHECK: add.u16 rh0, rh1, 1;
40; CHECK-NEXT: ret;
41 %z = add i16 %x, 1
42 ret i16 %z
43}
44
45define ptx_device i32 @t2_u32(i32 %x) {
46; CHECK: add.u32 r0, r1, 1;
47; CHECK-NEXT: ret;
48 %z = add i32 %x, 1
49 ret i32 %z
50}
51
52define ptx_device i64 @t2_u64(i64 %x) {
53; CHECK: add.u64 rd0, rd1, 1;
54; CHECK-NEXT: ret;
55 %z = add i64 %x, 1
56 ret i64 %z
57}
58
59define ptx_device float @t2_f32(float %x) {
Che-Liang Chiouf7172022011-02-28 06:34:09 +000060; CHECK: add.f32 f0, f1, 0F3F800000;
61; CHECK-NEXT: ret;
62 %z = fadd float %x, 1.0
63 ret float %z
64}
Che-Liang Chioufd8978b2011-03-02 03:20:28 +000065
66define ptx_device double @t2_f64(double %x) {
67; CHECK: add.f64 fd0, fd1, 0D3FF0000000000000;
68; CHECK-NEXT: ret;
69 %z = fadd double %x, 1.0
70 ret double %z
71}