Bob Wilson | fe61fb1 | 2010-02-12 01:30:21 +0000 | [diff] [blame^] | 1 | //===-- OptimizePHIs.cpp - Optimize machine instruction PHIs --------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This pass optimizes machine instruction PHIs to take advantage of |
| 11 | // opportunities created during DAG legalization. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #define DEBUG_TYPE "phi-opt" |
| 16 | #include "llvm/CodeGen/Passes.h" |
| 17 | #include "llvm/CodeGen/MachineFunctionPass.h" |
| 18 | #include "llvm/CodeGen/MachineInstr.h" |
| 19 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
| 20 | #include "llvm/Target/TargetInstrInfo.h" |
| 21 | #include "llvm/Function.h" |
| 22 | #include "llvm/ADT/SmallSet.h" |
| 23 | #include "llvm/ADT/Statistic.h" |
| 24 | using namespace llvm; |
| 25 | |
| 26 | STATISTIC(NumPHICycles, "Number of PHI cycles replaced"); |
| 27 | |
| 28 | namespace { |
| 29 | class OptimizePHIs : public MachineFunctionPass { |
| 30 | MachineRegisterInfo *MRI; |
| 31 | const TargetInstrInfo *TII; |
| 32 | |
| 33 | public: |
| 34 | static char ID; // Pass identification |
| 35 | OptimizePHIs() : MachineFunctionPass(&ID) {} |
| 36 | |
| 37 | virtual bool runOnMachineFunction(MachineFunction &MF); |
| 38 | |
| 39 | virtual void getAnalysisUsage(AnalysisUsage &AU) const { |
| 40 | AU.setPreservesCFG(); |
| 41 | MachineFunctionPass::getAnalysisUsage(AU); |
| 42 | } |
| 43 | |
| 44 | private: |
| 45 | bool IsSingleValuePHICycle(const MachineInstr *MI, unsigned &SingleValReg, |
| 46 | SmallSet<unsigned, 16> &RegsInCycle); |
| 47 | bool ReplacePHICycles(MachineBasicBlock &MBB); |
| 48 | }; |
| 49 | } |
| 50 | |
| 51 | char OptimizePHIs::ID = 0; |
| 52 | static RegisterPass<OptimizePHIs> |
| 53 | X("opt-phis", "Optimize machine instruction PHIs"); |
| 54 | |
| 55 | FunctionPass *llvm::createOptimizePHIsPass() { return new OptimizePHIs(); } |
| 56 | |
| 57 | bool OptimizePHIs::runOnMachineFunction(MachineFunction &Fn) { |
| 58 | MRI = &Fn.getRegInfo(); |
| 59 | TII = Fn.getTarget().getInstrInfo(); |
| 60 | |
| 61 | // Find PHI cycles that can be replaced by a single value. InstCombine |
| 62 | // does this, but DAG legalization may introduce new opportunities, e.g., |
| 63 | // when i64 values are split up for 32-bit targets. |
| 64 | bool Changed = false; |
| 65 | for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) |
| 66 | Changed |= ReplacePHICycles(*I); |
| 67 | |
| 68 | return Changed; |
| 69 | } |
| 70 | |
| 71 | /// IsSingleValuePHICycle - Check if MI is a PHI where all the source operands |
| 72 | /// are copies of SingleValReg, possibly via copies through other PHIs. If |
| 73 | /// SingleValReg is zero on entry, it is set to the register with the single |
| 74 | /// non-copy value. RegsInCycle is a set used to keep track of the PHIs that |
| 75 | /// have been scanned. |
| 76 | bool OptimizePHIs::IsSingleValuePHICycle(const MachineInstr *MI, |
| 77 | unsigned &SingleValReg, |
| 78 | SmallSet<unsigned, 16> &RegsInCycle) { |
| 79 | assert(MI->isPHI() && "IsSingleValuePHICycle expects a PHI instruction"); |
| 80 | unsigned DstReg = MI->getOperand(0).getReg(); |
| 81 | |
| 82 | // See if we already saw this register. |
| 83 | if (!RegsInCycle.insert(DstReg)) |
| 84 | return true; |
| 85 | |
| 86 | // Don't scan crazily complex things. |
| 87 | if (RegsInCycle.size() == 16) |
| 88 | return false; |
| 89 | |
| 90 | // Scan the PHI operands. |
| 91 | for (unsigned i = 1; i != MI->getNumOperands(); i += 2) { |
| 92 | unsigned SrcReg = MI->getOperand(i).getReg(); |
| 93 | if (SrcReg == DstReg) |
| 94 | continue; |
| 95 | const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); |
| 96 | |
| 97 | // Skip over register-to-register moves. |
| 98 | unsigned MvSrcReg, MvDstReg, SrcSubIdx, DstSubIdx; |
| 99 | if (SrcMI && |
| 100 | TII->isMoveInstr(*SrcMI, MvSrcReg, MvDstReg, SrcSubIdx, DstSubIdx) && |
| 101 | SrcSubIdx == 0 && DstSubIdx == 0 && |
| 102 | TargetRegisterInfo::isVirtualRegister(MvSrcReg)) |
| 103 | SrcMI = MRI->getVRegDef(MvSrcReg); |
| 104 | if (!SrcMI) |
| 105 | return false; |
| 106 | |
| 107 | if (SrcMI->isPHI()) { |
| 108 | if (!IsSingleValuePHICycle(SrcMI, SingleValReg, RegsInCycle)) |
| 109 | return false; |
| 110 | } else { |
| 111 | // Fail if there is more than one non-phi/non-move register. |
| 112 | if (SingleValReg != 0) |
| 113 | return false; |
| 114 | SingleValReg = SrcReg; |
| 115 | } |
| 116 | } |
| 117 | return true; |
| 118 | } |
| 119 | |
| 120 | /// ReplacePHICycles - Find PHI cycles that can be replaced by a single |
| 121 | /// value and remove them. |
| 122 | bool OptimizePHIs::ReplacePHICycles(MachineBasicBlock &MBB) { |
| 123 | bool Changed = false; |
| 124 | for (MachineBasicBlock::iterator |
| 125 | MII = MBB.begin(), E = MBB.end(); MII != E; ) { |
| 126 | MachineInstr *MI = &*MII++; |
| 127 | if (!MI->isPHI()) |
| 128 | break; |
| 129 | |
| 130 | unsigned SingleValReg = 0; |
| 131 | SmallSet<unsigned, 16> RegsInCycle; |
| 132 | if (IsSingleValuePHICycle(MI, SingleValReg, RegsInCycle) && |
| 133 | SingleValReg != 0) { |
| 134 | MRI->replaceRegWith(MI->getOperand(0).getReg(), SingleValReg); |
| 135 | MI->eraseFromParent(); |
| 136 | ++NumPHICycles; |
| 137 | Changed = true; |
| 138 | } |
| 139 | } |
| 140 | return Changed; |
| 141 | } |