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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 17011050225aebadfdaaf645db692ba825c0c2c4
  1. 23d59c2 typo in declaration from earlier today by Andrew Trick · 13 years ago
  2. 50ade65 Simplify the known retain count tracking; use a boolean state instead by Dan Gohman · 13 years ago
  3. eeeb775 Build custom predecessor and successor lists for each basic block. by Dan Gohman · 13 years ago
  4. 14ce6fa ARM: improved assembler diagnostics for missing CPU features. by Jim Grosbach · 13 years ago
  5. 86b7e2a Fix a naughty header include that breaks "installed" builds. by Andrew Trick · 13 years ago
  6. 80c1ea6 ConstantFoldSelectInstruction swapped the operands of the select. by Nadav Rotem · 13 years ago
  7. 2003e03 Fix the testcase. We do expect two vblendw on XMMs. by Nadav Rotem · 13 years ago
  8. 34a13bb Add a testcase for 155440 by Nadav Rotem · 13 years ago
  9. ddb1420 MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and refuse to break edge to EH landing pad. rdar://11300144 by Evan Cheng · 13 years ago
  10. 1d9e68d Add support for llvm.arm.neon.vmull* intrinsics to InstCombine. This fixes by Lang Hames · 13 years ago
  11. 7362ac7 Fix a crash on valid (if UB) bitcode that is produced for some global by Chandler Carruth · 13 years ago
  12. 95a7e80 ARM: Nuke remnant bogus code. by Jim Grosbach · 13 years ago
  13. 6ce1c88 Related to PR1255. Let's begin. I'll commit classes that corresponds to our latest PR1255 discussion posts in llvm-commits. by Stepan Dyatkovskiy · 13 years ago
  14. 7bc9698 AVX: Add additional vbroadcast replacement sequences for integers. by Nadav Rotem · 13 years ago
  15. 63bbe14 cmake: new file by Andrew Trick · 13 years ago
  16. c3ad885 misched: DAG builder must special case earlyclobber by Andrew Trick · 13 years ago
  17. 000b250 misched: try (not too hard) to place debug values where they belong by Andrew Trick · 13 years ago
  18. eb45ebb misched: ignore debug values during scheduling by Andrew Trick · 13 years ago
  19. 006e1ab misched: DAG builder support for tracking register pressure within the current scheduling region. by Andrew Trick · 13 years ago
  20. 4dfeef1 RegisterPressure: A utility for computing register pressure within a by Andrew Trick · 13 years ago
  21. 24e767d Add missing test cases for ARM VLD3 (single 3-element structure to all lanes) by Kevin Enderby · 13 years ago
  22. 2c66edf Add missing test cases for ARM VLD4 (single 4-element structure to all lanes) by Kevin Enderby · 13 years ago
  23. 87ffdbc AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8 by Nadav Rotem · 13 years ago
  24. f4478f9 Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector by Richard Barton · 13 years ago
  25. d1a7913 AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructions by Nadav Rotem · 13 years ago
  26. adb082c Look for the 'Is Simulated' module flag. This indicates that the program is compiled to run on a simulator. by Bill Wendling · 13 years ago
  27. 75920ad FileCheck-ize tests. by Bill Wendling · 13 years ago
  28. c6490d1 FileCheck-ize these tests. by Bill Wendling · 13 years ago
  29. d5cc8b8 FileCheck-ize these tests. Harden some of them. by Bill Wendling · 13 years ago
  30. 3ef43cf Remove dangling spaces. Fix some other formatting. by Craig Topper · 13 years ago
  31. 7fd5e16 Simplify code a bit and make it compile better. Remove unused parameters. by Craig Topper · 13 years ago
  32. aff5968 Add a missing cpu subtype. by Evan Cheng · 13 years ago
  33. c92ba4e Tidy up. 80 columns, whitespace, et. al. by Jim Grosbach · 13 years ago
  34. a354077 Optimize the vector UINT_TO_FP, SINT_TO_FP and FP_TO_SINT operations where the integer type is i8 (commonly used in graphics). by Nadav Rotem · 13 years ago
  35. 6a8c7bf This patch fixes a problem which arose when using the Post-RA scheduler by Preston Gurd · 13 years ago
  36. 1d52184 ARM: VSLI two-operand assmebly aliases are tblgen'erated. by Jim Grosbach · 13 years ago
  37. e1d866e ARM: tblgen'erate VSRA/VRSRA/VSRI assembly two-operand aliases. by Jim Grosbach · 13 years ago
  38. c34954d ARM: Add testcases for two-operand variants of VSRA/VRSRA/VSRI. by Jim Grosbach · 13 years ago
  39. 10a3933 Add ARM mode tests for the NEON vector shift-accumulate tests. by Jim Grosbach · 13 years ago
  40. 2b85250 Tidy up. Reformat for ease of reading. by Jim Grosbach · 13 years ago
  41. 13b7352 ARM: vqdmulh two-operand aliases are tblgen'erated now. by Jim Grosbach · 13 years ago
  42. 8dab504 [Support/Unix] Unconditionally include time.h. by Michael J. Spencer · 13 years ago
  43. 216432d Allow forward declarations to take a context. This helps the debugger by Eric Christopher · 13 years ago
  44. e3fd2a3 Temporarily revert r155364 until the upstream review can complete, per by Chandler Carruth · 13 years ago
  45. d410eab Revert r155365, r155366, and r155367. All three of these have regression by Chandler Carruth · 13 years ago
  46. 15e56ad Hexagon V5 (floating point) support. by Sirish Pande · 13 years ago
  47. 1bfd248 Support for Hexagon architectural feature, new value jump. by Sirish Pande · 13 years ago
  48. 0dac391 Support for Hexagon VLIW Packetizer. by Sirish Pande · 13 years ago
  49. 9f6852d Hexagon Packetizer's target independent fix. by Sirish Pande · 13 years ago
  50. 72847f3 Reapply r155136 after fixing PR12599. by Jakob Stoklund Olesen · 13 years ago
  51. 9dc06bd Conflict with st_dev/st_ino identifiers under Debian GNU/Hurd by Sylvestre Ledru · 13 years ago
  52. 55cabae Fix issue 67 by checking that the interface functions weren't redefined in the compiled source file. by Alexander Potapenko · 13 years ago
  53. 2d5fdf8 [tsan] use llvm/ADT/Statistic.h for tsan stats by Kostya Serebryany · 13 years ago
  54. 708e44f Use MVT instead of EVT through all of LowerVECTOR_SHUFFLEtoBlend and not just the switch. Saves a little bit of binary size. by Craig Topper · 13 years ago
  55. 9d35240 Make getZeroVector and getOnesVector more alike as far as how they detect 128-bit versus 256-bit vectors. Be explicit about both sizes and use llvm_unreachable. Similar changes to getLegalSplat. by Craig Topper · 13 years ago
  56. 69947b9 Tidy up by removing some 'else' after 'return' by Craig Topper · 13 years ago
  57. 1842ba0 Tidy up spacing in LowerVECTOR_SHUFFLEtoBlend. Remove code that checks if shuffle operand has a different type than the the shuffle result since it can never happen. by Craig Topper · 13 years ago
  58. 731dfd0 Add a couple llvm_unreachables. by Craig Topper · 13 years ago
  59. 0fbf364 Remove some tab characers. by Craig Topper · 13 years ago
  60. e8eb116 Remove some 'else' after 'return'. No functional change. by Craig Topper · 13 years ago
  61. a9963c6 Don't die with an assertion if the Result bitwidth is already correct. This by Chris Lattner · 13 years ago
  62. 85d043d Cleanup whitespace. by Bill Wendling · 13 years ago
  63. 098c595 Limit the number of times we recurse through this algorithm. All of the by Bill Wendling · 13 years ago
  64. b14940a Make Extract128BitVector and Insert128BitVector take an unsigned instead of an ConstantNode SDValue. getConstant was almost always called just before only to have the functions take it apart and build a new ConstantSDNode. by Craig Topper · 13 years ago
  65. 767b4f6 Convert getNode(UNDEF) to getUNDEF. by Craig Topper · 13 years ago
  66. df966f6 Make calls to getVectorShuffle more consistent. Use shuffle VT for calls to getUNDEF instead of requerying. Use &Mask[0] instead of Mask.data(). by Craig Topper · 13 years ago
  67. d63fa65 Tidy up. 80 columns and argument alignment. by Craig Topper · 13 years ago
  68. 4c7972d Simplify code by converting multiple places that were manually concatenating 128-bit vectors to use either CONCAT_VECTORS or a helper function. CONCAT_VECTORS will itself be lowered to the same pattern as before. The helper function is needed for concats of BUILD_VECTORs since getNode(CONCAT_VECTORS) will just return a large BUILD_VECTOR and we may be trying to lower large BUILD_VECTORS when this occurs. by Craig Topper · 13 years ago
  69. dd90478 cleaned line endings in the newly added test file by Elena Demikhovsky · 13 years ago
  70. bfae1fd ARM: Initialize the HasRAS bit. by Benjamin Kramer · 13 years ago
  71. a3e3481 Tidy up this test more: by Chandler Carruth · 13 years ago
  72. 71f8bc3 FileCheck-ize a test, and tidy it up a touch. by Chandler Carruth · 13 years ago
  73. 1da5867 ZERO_EXTEND/SIGN_EXTEND/TRUNCATE optimization for AVX2 by Elena Demikhovsky · 13 years ago
  74. eb23f9e Remove some potential warnings about variables used uninitialized. by Bill Wendling · 13 years ago
  75. d46575f Add a flag to the struct type finder to collect only those types which have by Bill Wendling · 13 years ago
  76. 2dbd784 No need for "else if" after a return. Autosense "0o123" as octal in by Chris Lattner · 13 years ago
  77. 5573876 stop hiding SmallVector's append that takes a count + element. by Chris Lattner · 13 years ago
  78. db34616 Teach getVectorTypeBreakdown about promotion of vectors in addition to widening of vectors. by Nadav Rotem · 13 years ago
  79. 9e401f2 Make some fixed arrays const. Use array_lengthof in a couple places instead of a hardcoded number. by Craig Topper · 13 years ago
  80. d0cf565 Tidy up. 80 columns and some other spacing issues. by Craig Topper · 13 years ago
  81. 0b5ad0b Remove unused PointerLikeTypeTraits for IndexListEntry. by Benjamin Kramer · 13 years ago
  82. 8959393 llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC. by NAKAMURA Takumi · 13 years ago
  83. d2f16a2 HexagonISelLowering.cpp: Reorder #includes. by NAKAMURA Takumi · 13 years ago
  84. 4a80d64 CMake: Enable LLVM_COMPILER_JOBS on all MS IDEs. We don't support older environments than VS9. by NAKAMURA Takumi · 13 years ago
  85. 5bfe3bf CMake: Prune redundant LLVM_COMPILER_JOBS from llvm/CMakeLists.txt. HandleLLVMOptions.cmake has it. by NAKAMURA Takumi · 13 years ago
  86. e0af267 move Signals to .rodata by Nuno Lopes · 13 years ago
  87. d1ad82f HexagonInstPrinter.cpp: Suppress -Wunused-variable warnings with -Asserts. by NAKAMURA Takumi · 13 years ago
  88. 2ddb845 YAMLParser: silence warning about tautological comparison on unsigned-char platforms. by Benjamin Kramer · 13 years ago
  89. f0ae38e Remove 'XXXRegisterClass' from tablegen output. Targets should use '&XXXRegClass' instead. by Craig Topper · 13 years ago
  90. 8e3c17a ARM: tblgen'erate more NEON two-operand aliases. by Jim Grosbach · 13 years ago
  91. 0b35c35 Fix PR12599. by Jakob Stoklund Olesen · 13 years ago
  92. d83c9ea ARM: tblgen'erate more NEON two-operand aliases. by Jim Grosbach · 13 years ago
  93. c827834 Revert r155241, which is causing some breakage. by Bill Wendling · 13 years ago
  94. 8c48e4f Make ISelPosition a local variable. by Jakob Stoklund Olesen · 13 years ago
  95. bc7d448 Register DAGUpdateListeners with SelectionDAG. by Jakob Stoklund Olesen · 13 years ago
  96. c61382b Extraneous semicolon. by Eric Christopher · 13 years ago
  97. 64c7af8 If we discover all of the named structs in a module, then don't bother to by Bill Wendling · 13 years ago
  98. 3429c75 Print <def,read-undef> to avoid confusion. by Jakob Stoklund Olesen · 13 years ago
  99. d06c2de Added TargetRegisterInfo::getRegPressureSetName. by Andrew Trick · 13 years ago
  100. 7c0903a TableGen'd RegPressure: Added getPressureSetName. by Andrew Trick · 13 years ago