Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 364a72a8e5810561613491bef0de6f301ee4925c / lib / Target / ARM / ARMISelLowering.cpp
  1. 364a72a Add entry in getTargetNodeName() for ARMISD::VBICIMM. by Bob Wilson · 15 years ago
  2. 626613d Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations. by Bob Wilson · 15 years ago
  3. bf17cfa Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. by Wesley Peck · 15 years ago
  4. 1f190c8 These instructions are thumb2 only. by Evan Cheng · 15 years ago
  5. 9684a7c Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first). by Tanya Lattner · 15 years ago
  6. d0c3817 Move hasFP() and few related hooks to TargetFrameInfo. by Anton Korobeynikov · 15 years ago
  7. d5448bb Split up ARM LowerShift function. by Bob Wilson · 15 years ago
  8. bf5be26 Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build vector with 2 elts by Nate Begeman · 15 years ago
  9. 54f9256 Do not use MEMBARRIER_MCR for any Thumb code. by Bob Wilson · 15 years ago
  10. 3a2429a Change the ARMConstantPoolValue modifier string to an enumeration. This will by Jim Grosbach · 15 years ago
  11. c24cb35 Add support for ARM's specialized vector-compare-against-zero instructions. by Owen Anderson · 15 years ago
  12. 36fa3ea Disallow the certain NEON modified-immediate forms when generating vorr or vbic. by Owen Anderson · 15 years ago
  13. 080c092 Add codegen and encoding support for the immediate form of vbic. by Owen Anderson · 15 years ago
  14. 416941d Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. by Evan Cheng · 15 years ago
  15. 60f4870 Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. by Owen Anderson · 15 years ago
  16. d966817 Add support for code generation of the one register with immediate form of vorr. by Owen Anderson · 15 years ago
  17. 3468c2e Check for extractelement with a variable operand for the element number. by Bob Wilson · 15 years ago
  18. cdfad36 Simplify uses of MVT and EVT. An MVT can be compared directly by Duncan Sands · 15 years ago
  19. dfed19f Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. by Evan Cheng · 15 years ago
  20. bc7deb0 Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. by Evan Cheng · 15 years ago
  21. 24645a1 NEON does not support truncating vector stores. Radar 8598391. by Bob Wilson · 15 years ago
  22. f74a429 Overhaul memory barriers in the ARM backend. Radar 8601999. by Bob Wilson · 15 years ago
  23. d7e473c - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency. by Evan Cheng · 15 years ago
  24. 44ab89e Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support. by John Thompson · 15 years ago
  25. 1fa9d30 Fix compiler warnings about signed/unsigned comparisons. by Bob Wilson · 15 years ago
  26. f20700c SelectionDAG shuffle nodes do not allow operands with different numbers of by Bob Wilson · 15 years ago
  27. 5c2d428 Enable ARM fastcc. by Evan Cheng · 15 years ago
  28. 76f920d Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by -arm-fastcc for now. by Evan Cheng · 15 years ago
  29. e4d3159 Fix crash introduced in 116852. 8573915. by Dale Johannesen · 15 years ago
  30. e4ad387 Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any by Jim Grosbach · 15 years ago
  31. 575cd14 Enable using vdup for vector constants which are splat of by Dale Johannesen · 15 years ago
  32. fd52906 Don't mark argument value stores as immutable, as otherwise the post-RA by Jim Grosbach · 15 years ago
  33. 1dd5a2f Remove unused ARMISD::AND selection DAG node. by Bob Wilson · 15 years ago
  34. 4f922f2 User proper libcall names & condcodes while compiling for ARM EABI. by Anton Korobeynikov · 15 years ago
  35. 02aba73 Add a command line option "-arm-strict-align" to disallow unaligned memory by Bob Wilson · 15 years ago
  36. fff606d Enable code placement optimization pass for ARM. by Evan Cheng · 15 years ago
  37. 637d89f Add support for ELF PLT references for ARM MC asm printing. Adding a by Jim Grosbach · 15 years ago
  38. b68987e Change VDUPLANE DAG combiner to just return the result instead of calling by Bob Wilson · 15 years ago
  39. 0b8ccb8 Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one by Bob Wilson · 15 years ago
  40. 8614167 Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes by Owen Anderson · 15 years ago
  41. fc448ff convert a couple more places to use the new getStore() by Chris Lattner · 15 years ago
  42. 65ffec4 Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load by Bob Wilson · 15 years ago
  43. d1c24ed convert the targets off the non-MachinePointerInfo of getLoad. by Chris Lattner · 15 years ago
  44. e72f202 reimplement memcpy/memmove/memset lowering to use MachinePointerInfo by Chris Lattner · 15 years ago
  45. 75f0288 Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64 by Bob Wilson · 15 years ago
  46. 6f2ccef Split out some of the calling convention bits so that they can be by Eric Christopher · 15 years ago
  47. 3ef1c87 Teach if-converter to be more careful with predicating instructions that would by Evan Cheng · 15 years ago
  48. 4725ca7 remove trailing whitespace by Jim Grosbach · 15 years ago
  49. eb0c3d3 Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the by Bob Wilson · 15 years ago
  50. d0b69cf Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply, by Bob Wilson · 15 years ago
  51. 0b4aa7d Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, but by Bill Wendling · 15 years ago
  52. 3cc3283 ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed by Daniel Dunbar · 15 years ago
  53. b31a11b Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and by Bob Wilson · 15 years ago
  54. 2003bcf Expand ZERO_EXTEND operations for NEON vector types. Testcase from Nick Lewycky. by Bob Wilson · 15 years ago
  55. 7aaf5bf Allow more cases of undef shuffle indices and add tests for them. by Bob Wilson · 15 years ago
  56. ca5e47d Ignore undef shuffle indices when checking for a VTRN shuffle. Radar 8290937. by Bob Wilson · 15 years ago
  57. 703af3a Temporarily disable tail calls on ARM to work around some linker problems. by Bob Wilson · 15 years ago
  58. fcba5e6 cortex m4 has floating point support, but only single precision. by Jim Grosbach · 15 years ago
  59. de2b151 Consider this code snippet: by Bill Wendling · 15 years ago
  60. 11db068 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the by Evan Cheng · 15 years ago
  61. 5818032 Delete some unused instructions. by Evan Cheng · 15 years ago
  62. ac09680 Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object. by Evan Cheng · 15 years ago
  63. 4bd828f Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP by Daniel Dunbar · 15 years ago
  64. c9aed19 Fix ARM hasFP() semantics. It should return true whenever FP register is by Evan Cheng · 15 years ago
  65. a54db0c Remove switch for disabling ARM tail calls. They by Dale Johannesen · 15 years ago
  66. 67b453b Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABA by Bob Wilson · 15 years ago
  67. d1fb583 Add support for getting & setting the FPSCR application register on ARM when VFP is enabled. by Nate Begeman · 15 years ago
  68. 3d5792a Refactor ARM-specific DAG combining in preparation for adding some more by Bob Wilson · 15 years ago
  69. f630c71 Implement vector constants which are splat of by Dale Johannesen · 15 years ago
  70. cec36f4 Hook in GlobalMerge pass by Anton Korobeynikov · 15 years ago
  71. c2723a5 Use the appropriate register class for an i32 when adding ARM::LR to the by Jim Grosbach · 15 years ago
  72. 3144687 - Allow target to specify when is register pressure "too high". In most cases, by Evan Cheng · 15 years ago
  73. 30d35b8 Mark an assert-only variable as used. by Chandler Carruth · 15 years ago
  74. 4a863e2 More register pressure aware scheduling work. by Evan Cheng · 15 years ago
  75. ab69588 Baby steps towards ARM fast-isel. by Eric Christopher · 15 years ago
  76. bc56501 Fix calling convention on ARM if vfp2+ is enabled. by Rafael Espindola · 15 years ago
  77. 4f6b467 Teach bottom up pre-ra scheduler to track register pressure. Work in progress. by Evan Cheng · 15 years ago
  78. 26ede68 Removed un-used code. by Jim Grosbach · 15 years ago
  79. d70f57b ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers. by Evan Cheng · 15 years ago
  80. e1102ca Since ARM emits inline jump tables as part of the ConstantIsland pass, by Jim Grosbach · 15 years ago
  81. 350afb1 revert so I can get the right PR# in the log message. by Jim Grosbach · 15 years ago
  82. 0bb9895 Since ARM emits inline jump tables as part of the ConstantIsland pass, by Jim Grosbach · 15 years ago
  83. 5423856 Add combiner patterns to more effectively utilize the BFI (bitfield insert) by Jim Grosbach · 15 years ago
  84. dd7d28a add BFI to getTargetNodeName() by Jim Grosbach · 15 years ago
  85. 15a2f2e Fix logic think-o by Jim Grosbach · 15 years ago
  86. 469bbdb Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction by Jim Grosbach · 15 years ago
  87. 60108e9 Split -enable-finite-only-fp-math to two options: by Evan Cheng · 15 years ago
  88. 7e3f0d2 Add support for NEON VMVN immediate instructions. by Bob Wilson · 15 years ago
  89. 9e82bf1 Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes. by Bob Wilson · 15 years ago
  90. cba270d Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent by Bob Wilson · 15 years ago
  91. 218977b Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. by Evan Cheng · 15 years ago
  92. 6dce00c Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to by Bob Wilson · 15 years ago
  93. c7a797b Remove some code that doesn't appear to do anything. All the ARM call by Bob Wilson · 15 years ago
  94. cbeeae2 Fix va_arg for doubles. With this patch VAARG nodes always contain the by Rafael Espindola · 15 years ago
  95. 5d115a0 Check for FiniteOnlyFPMath as well. by Evan Cheng · 15 years ago
  96. 4ff7ab6 r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0. by Evan Cheng · 15 years ago
  97. 515fe3a Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met: by Evan Cheng · 15 years ago
  98. 7835f1f Changes to ARM tail calls, mostly cosmetic. by Dale Johannesen · 15 years ago
  99. c940365 Split the SDValue out of OutputArg so that SelectionDAG-independent by Dan Gohman · 15 years ago
  100. e97f968 Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where by Jim Grosbach · 15 years ago