- 3aef703 Update LLVM for merge to r171905. by Stephen Hines · 12 years ago
- 059800f Merge remote-tracking branch 'upstream/master' into merge-llvm by Stephen Hines · 12 years ago
- 759e3fa Remove edis - the enhanced disassembler. Fixes PR14654. by Roman Divacky · 12 years ago
- d04a8d4 Use the new script to sort the includes of every file under lib. by Chandler Carruth · 12 years ago
- 1c83093 Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInst by Kevin Enderby · 12 years ago
- 445ba85 Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target by Kevin Enderby · 12 years ago
- 88d1266 Fix a bug where a 32-bit address with the high bit does not get symbolicated by Kevin Enderby · 12 years ago
- 93c7c44 Fix the handling of edge cases in ARM shifted operands. by Tim Northover · 12 years ago
- 1c4ad5e Merge branch 'upstream' into merge-2012_09_10 by Stephen Hines · 12 years ago
- 24b9f25 Diagnose invalid alignments on duplicating VLDn instructions. by Tim Northover · 12 years ago
- eae1d34 Check for invalid alignment values when decoding VLDn/VSTn (single ln) instructions. by Tim Northover · 12 years ago
- 1144af3 Fix integer undefined behavior due to signed left shift overflow in LLVM. by Richard Smith · 12 years ago
- 3167515 Merge branch 'upstream' into merge_2 by Stephen Hines · 12 years ago
- 960fb74 Remove unnecessary include of ARMGenInstrInfo.inc. by Craig Topper · 12 years ago
- fc1a161 Switch the fixed-length disassembler to be table-driven. by Jim Grosbach · 12 years ago
- 7744acd Merge with LLVM upstream r160668 (Jul 24th 2012) by Shih-wei Liao · 12 years ago
- fd652df Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue. by Jiangning Liu · 12 years ago
- c1b7ca5 Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. by Jiangning Liu · 12 years ago
- c8e41c5 Fix a typo (the the => the) by Sylvestre Ledru · 12 years ago
- fae96f1 Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time! by Richard Barton · 12 years ago
- 270e362 Revert r159938 (and r159945) to appease the buildbots. by Chad Rosier · 12 years ago
- 83cfff6 Oops - correct broken disassembly for VMOV by Richard Barton · 12 years ago
- 2e7e34b Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) by Richard Barton · 12 years ago
- c8f2fcc Correct decoder for T1 conditional B encoding by Richard Barton · 12 years ago
- dd051a0 ARMDisassembler.cpp: Fix utf8 char in comments. by NAKAMURA Takumi · 12 years ago
- 3610a15 Tweak to the fix in r156212, as with the change in removing the shift the by Kevin Enderby · 12 years ago
- ce734d5 Fix a bug in the ARM disassembler for wide branch conditional instructions by Kevin Enderby · 12 years ago
- 2d524b0 Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits by Kevin Enderby · 12 years ago
- b422d0b Fixed disassembler for vstm/vldm ARM VFP instructions. by Silviu Baranga · 12 years ago
- bb32f1d ARM: Tweak tADDrSP definition for consistent operand order. by Jim Grosbach · 12 years ago
- 4d2f077 Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst. by Richard Barton · 12 years ago
- cf5a146 Merge with LLVM upstream r155090. by Shih-wei Liao · 12 years ago
- f4478f9 Refactor Thumb ITState handling in ARM Disassembler to more efficiently use its vector by Richard Barton · 12 years ago
- 35ee7d2 Added support for disassembling unpredictable swp/swpb ARM instructions. by Silviu Baranga · 12 years ago
- fa1ebc6 Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. by Silviu Baranga · 12 years ago
- c5a2a33 Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) by Kevin Enderby · 12 years ago
- 2a7d3a9 Fix a few more places in the ARM disassembler so that branches get by Kevin Enderby · 12 years ago
- b318cc1 Fixed a case of ARM disassembly getting an assert on a bad encoding by Kevin Enderby · 12 years ago
- a69da35 Fix ARM disassembly of VLD instructions with writebacks. And add test a case by Kevin Enderby · 12 years ago
- 75e3b7f ARMDisassembler: drop bogus dependency on ARMCodeGen by Dylan Noblesmith · 12 years ago
- c89c744 Remove unnecessary llvm:: qualifications by Craig Topper · 12 years ago
- c59a799 Merge branch 'upstream' into sliao_d by Shih-wei Liao · 12 years ago
- 6fe310e Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. by Silviu Baranga · 12 years ago
- b7c2ed6 Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM by Silviu Baranga · 12 years ago
- f0586f0 Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test by Kevin Enderby · 12 years ago
- 5c062ad The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. by Silviu Baranga · 12 years ago
- b78ca42 Use uint16_t to store registers and opcode in static tables in the target specific backends. by Craig Topper · 12 years ago
- ff3164a Tidy up. Remove dead code that slipped into previous commit. by Jim Grosbach · 12 years ago
- 4d0983a ARM more NEON VLD/VST composite physical register refactoring. by Jim Grosbach · 12 years ago
- c0fc450 ARM refactor more NEON VLD/VST instructions to use composite physregs by Jim Grosbach · 12 years ago
- 158c8a4 Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. by Kevin Enderby · 12 years ago
- c02a5c5 Merge branch 'upstream' into merge-20120305 by Stephen Hines · 12 years ago
- c3384c9 ARM Refactor VLD/VST spaced pair instructions. by Jim Grosbach · 12 years ago
- 28f08c9 ARM refactor away a bunch of VLD/VST pseudo instructions. by Jim Grosbach · 12 years ago
- adef06a Make MemoryObject accessor members const again by Derek Schuff · 12 years ago
- 0943303 Fix the symbolic operand added for the C disassmbler API for the ARM bl by Kevin Enderby · 12 years ago
- b80d571 Updated the llvm-mc disassembler C API to support for the X86 target. by Kevin Enderby · 12 years ago
- 31d157a Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. by Jia Liu · 12 years ago
- 88b6fc0 Make the EDis tables const. by Benjamin Kramer · 12 years ago
- bc21981 Convert assert(0) to llvm_unreachable by Craig Topper · 12 years ago
- 2ea9387 Enable streaming of bitcode by Derek Schuff · 12 years ago
- 4d6ccb5 More dead code removal (using -Wunreachable-code) by David Blaikie · 13 years ago
- a1e6e24 Merge with LLVM upstream r146714 (Dec 16th 2011) by Logan Chien · 13 years ago
- 60d99a5 ARM NEON VTBL/VTBX assembly parsing and encoding. by Jim Grosbach · 13 years ago
- bb3a2e4 ARM NEON refactor VST2 w/ writeback instructions. by Jim Grosbach · 13 years ago
- e90ac9b ARM NEON VST2 assembly parsing and encoding. by Jim Grosbach · 13 years ago
- 4ab406d LLVMBuild: Remove trailing newline, which irked me. by Daniel Dunbar · 13 years ago
- a4e3c7f ARM assembly parsing and encoding for VLD2 with writeback. by Jim Grosbach · 13 years ago
- 7b8e121 Remove unused variable by Matt Beaumont-Gay · 13 years ago
- 096334e ARM parsing for VLD1 all lanes, with writeback. by Jim Grosbach · 13 years ago
- 4c7edb3 ARM assembly parsing and encoding for four-register VST1. by Jim Grosbach · 13 years ago
- d5ca201 ARM assembly parsing and encoding for three-register VST1. by Jim Grosbach · 13 years ago
- d782bae build/CMake: Finish removal of add_llvm_library_dependencies. by Daniel Dunbar · 13 years ago
- 1429059 Merge with LLVM upstream r145126 (Nov 25th 2011) by Logan Chien · 13 years ago
- 22925d9 Fix a misplaced paren bug. by Owen Anderson · 13 years ago
- b589be9 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. by Owen Anderson · 13 years ago
- f9c1b92 Merge with LLVM upstream r144606 (Nov 15th 2011) by Logan Chien · 13 years ago
- 00ade8b build: Add initial cut at LLVMBuild.txt files. by Daniel Dunbar · 13 years ago
- bd513ea The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552. by Owen Anderson · 13 years ago
- 87f24f5 Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case. by Owen Anderson · 13 years ago
- 1a2a45b Fix disassembly of some VST1 instructions. by Owen Anderson · 13 years ago
- c46f912 ARM VST1 w/ writeback assembly parsing and encoding. by Jim Grosbach · 13 years ago
- 65ebfa6 More not-crashing NEON disassembly updates for the vld refactoring. by Owen Anderson · 13 years ago
- 101a983 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. by Owen Anderson · 13 years ago
- f2652f5 Add some NEON stores to the VLD decoding hook that were accidentally omitted previously. by Owen Anderson · 13 years ago
- fd92758 ARM assembly parsing and encoding for VLD1 with writeback. by Jim Grosbach · 13 years ago
- 974c3ce ARM assembly parsing and encoding for VLD1 w/ writeback. by Jim Grosbach · 13 years ago
- a028cb5 ARM refactor am6offset usage for VLD1. by Jim Grosbach · 13 years ago
- 1d4b94f Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. by Owen Anderson · 13 years ago
- 1c7cab0 Move various generated tables into read-only memory, fixing up const correctness along the way. by Benjamin Kramer · 13 years ago
- 7d59e94 Assembly parsing for 4-register sequential variant of VLD2. by Jim Grosbach · 13 years ago
- abe29f3 Assembly parsing for 2-register sequential variant of VLD2. by Jim Grosbach · 13 years ago
- 795974e Assembly parsing for 4-register variant of VLD1. by Jim Grosbach · 13 years ago
- 9f769c6 Assembly parsing for 3-register variant of VLD1. by Jim Grosbach · 13 years ago
- 4d2df7a ARM VLD parsing and encoding. by Jim Grosbach · 13 years ago
- 28e7809 Tidy up. Trailing whitespace. by Jim Grosbach · 13 years ago
- b8ebca8 build: Attempt to rectify inconsistencies between CMake and LLVMBuild versions of explicit dependencies. by Daniel Dunbar · 13 years ago
- 742c4ba Re-apply 144430, this time with the associated isel and disassmbler bits. by Jim Grosbach · 13 years ago
- eea66f6 Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler. by Benjamin Kramer · 13 years ago
- a3a2dfd build: Add initial cut at LLVMBuild.txt files. by Daniel Dunbar · 13 years ago