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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 575cd148cedec66af0adc266c5d7ecdbe1641d7e / lib / Target / ARM / ARMISelLowering.cpp
  1. 575cd14 Enable using vdup for vector constants which are splat of by Dale Johannesen · 15 years ago
  2. fd52906 Don't mark argument value stores as immutable, as otherwise the post-RA by Jim Grosbach · 15 years ago
  3. 1dd5a2f Remove unused ARMISD::AND selection DAG node. by Bob Wilson · 15 years ago
  4. 4f922f2 User proper libcall names & condcodes while compiling for ARM EABI. by Anton Korobeynikov · 15 years ago
  5. 02aba73 Add a command line option "-arm-strict-align" to disallow unaligned memory by Bob Wilson · 15 years ago
  6. fff606d Enable code placement optimization pass for ARM. by Evan Cheng · 15 years ago
  7. 637d89f Add support for ELF PLT references for ARM MC asm printing. Adding a by Jim Grosbach · 15 years ago
  8. b68987e Change VDUPLANE DAG combiner to just return the result instead of calling by Bob Wilson · 15 years ago
  9. 0b8ccb8 Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing one by Bob Wilson · 15 years ago
  10. 8614167 Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes by Owen Anderson · 15 years ago
  11. fc448ff convert a couple more places to use the new getStore() by Chris Lattner · 15 years ago
  12. 65ffec4 Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load by Bob Wilson · 15 years ago
  13. d1c24ed convert the targets off the non-MachinePointerInfo of getLoad. by Chris Lattner · 15 years ago
  14. e72f202 reimplement memcpy/memmove/memset lowering to use MachinePointerInfo by Chris Lattner · 15 years ago
  15. 75f0288 Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64 by Bob Wilson · 15 years ago
  16. 6f2ccef Split out some of the calling convention bits so that they can be by Eric Christopher · 15 years ago
  17. 3ef1c87 Teach if-converter to be more careful with predicating instructions that would by Evan Cheng · 15 years ago
  18. 4725ca7 remove trailing whitespace by Jim Grosbach · 15 years ago
  19. eb0c3d3 Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the by Bob Wilson · 15 years ago
  20. d0b69cf Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply, by Bob Wilson · 15 years ago
  21. 0b4aa7d Create an ARMISD::AND node. This node is exactly like the "ARM::AND" node, but by Bill Wendling · 15 years ago
  22. 3cc3283 ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed by Daniel Dunbar · 15 years ago
  23. b31a11b Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and by Bob Wilson · 15 years ago
  24. 2003bcf Expand ZERO_EXTEND operations for NEON vector types. Testcase from Nick Lewycky. by Bob Wilson · 15 years ago
  25. 7aaf5bf Allow more cases of undef shuffle indices and add tests for them. by Bob Wilson · 15 years ago
  26. ca5e47d Ignore undef shuffle indices when checking for a VTRN shuffle. Radar 8290937. by Bob Wilson · 15 years ago
  27. 703af3a Temporarily disable tail calls on ARM to work around some linker problems. by Bob Wilson · 15 years ago
  28. fcba5e6 cortex m4 has floating point support, but only single precision. by Jim Grosbach · 15 years ago
  29. de2b151 Consider this code snippet: by Bill Wendling · 15 years ago
  30. 11db068 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the by Evan Cheng · 15 years ago
  31. 5818032 Delete some unused instructions. by Evan Cheng · 15 years ago
  32. ac09680 Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object. by Evan Cheng · 15 years ago
  33. 4bd828f Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP by Daniel Dunbar · 15 years ago
  34. c9aed19 Fix ARM hasFP() semantics. It should return true whenever FP register is by Evan Cheng · 15 years ago
  35. a54db0c Remove switch for disabling ARM tail calls. They by Dale Johannesen · 15 years ago
  36. 67b453b Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABA by Bob Wilson · 15 years ago
  37. d1fb583 Add support for getting & setting the FPSCR application register on ARM when VFP is enabled. by Nate Begeman · 15 years ago
  38. 3d5792a Refactor ARM-specific DAG combining in preparation for adding some more by Bob Wilson · 15 years ago
  39. f630c71 Implement vector constants which are splat of by Dale Johannesen · 15 years ago
  40. cec36f4 Hook in GlobalMerge pass by Anton Korobeynikov · 15 years ago
  41. c2723a5 Use the appropriate register class for an i32 when adding ARM::LR to the by Jim Grosbach · 15 years ago
  42. 3144687 - Allow target to specify when is register pressure "too high". In most cases, by Evan Cheng · 15 years ago
  43. 30d35b8 Mark an assert-only variable as used. by Chandler Carruth · 15 years ago
  44. 4a863e2 More register pressure aware scheduling work. by Evan Cheng · 15 years ago
  45. ab69588 Baby steps towards ARM fast-isel. by Eric Christopher · 15 years ago
  46. bc56501 Fix calling convention on ARM if vfp2+ is enabled. by Rafael Espindola · 15 years ago
  47. 4f6b467 Teach bottom up pre-ra scheduler to track register pressure. Work in progress. by Evan Cheng · 15 years ago
  48. 26ede68 Removed un-used code. by Jim Grosbach · 15 years ago
  49. d70f57b ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers. by Evan Cheng · 15 years ago
  50. e1102ca Since ARM emits inline jump tables as part of the ConstantIsland pass, by Jim Grosbach · 15 years ago
  51. 350afb1 revert so I can get the right PR# in the log message. by Jim Grosbach · 15 years ago
  52. 0bb9895 Since ARM emits inline jump tables as part of the ConstantIsland pass, by Jim Grosbach · 15 years ago
  53. 5423856 Add combiner patterns to more effectively utilize the BFI (bitfield insert) by Jim Grosbach · 15 years ago
  54. dd7d28a add BFI to getTargetNodeName() by Jim Grosbach · 15 years ago
  55. 15a2f2e Fix logic think-o by Jim Grosbach · 15 years ago
  56. 469bbdb Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction by Jim Grosbach · 15 years ago
  57. 60108e9 Split -enable-finite-only-fp-math to two options: by Evan Cheng · 15 years ago
  58. 7e3f0d2 Add support for NEON VMVN immediate instructions. by Bob Wilson · 15 years ago
  59. 9e82bf1 Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes. by Bob Wilson · 15 years ago
  60. cba270d Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent by Bob Wilson · 15 years ago
  61. 218977b Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. by Evan Cheng · 15 years ago
  62. 6dce00c Move NEON "modified immediate" encode/decode into ARMAddressingModes.h to by Bob Wilson · 15 years ago
  63. c7a797b Remove some code that doesn't appear to do anything. All the ARM call by Bob Wilson · 15 years ago
  64. cbeeae2 Fix va_arg for doubles. With this patch VAARG nodes always contain the by Rafael Espindola · 15 years ago
  65. 5d115a0 Check for FiniteOnlyFPMath as well. by Evan Cheng · 15 years ago
  66. 4ff7ab6 r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0. by Evan Cheng · 15 years ago
  67. 515fe3a Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met: by Evan Cheng · 15 years ago
  68. 7835f1f Changes to ARM tail calls, mostly cosmetic. by Dale Johannesen · 15 years ago
  69. c940365 Split the SDValue out of OutputArg so that SelectionDAG-independent by Dan Gohman · 15 years ago
  70. e97f968 Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where by Jim Grosbach · 15 years ago
  71. c66e150b By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather by Jim Grosbach · 15 years ago
  72. 0d881da Propagate debug loc. by Devang Patel · 15 years ago
  73. 14152b4 Reapply r107655 with fixes; insert the pseudo instruction into by Dan Gohman · 15 years ago
  74. 258c58c Revert r107655. by Dan Gohman · 15 years ago
  75. b81c771 Fix a bunch of custom-inserter functions to handle the case where by Dan Gohman · 15 years ago
  76. ed2ae13 Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false. by Evan Cheng · 15 years ago
  77. b5b5057 ARM function alignments were off by a power of two. svn 83242 changed by Bob Wilson · 15 years ago
  78. 90c64f4 Remove initialized but otherwise unused variables. by Duncan Sands · 15 years ago
  79. a2c6f45 Followup to r106770: actually generate SXTB and SXTH for sign-extensions. by Eli Friedman · 15 years ago
  80. f679939 It's now possible to run code placement pass for ARM. by Evan Cheng · 15 years ago
  81. 1315143 Change if-conversion block size limit checks to add some flexibility. by Evan Cheng · 15 years ago
  82. 1784d16 The hasMemory argument is irrelevant to how the argument by Dale Johannesen · 15 years ago
  83. 86fe66d Reduce indentation. by Bob Wilson · 15 years ago
  84. e39fdbe Do not do tail calls to external symbols. If the by Dale Johannesen · 15 years ago
  85. 5def57a When using libcall expansions for the atomic intrinsics, the explicit by Jim Grosbach · 15 years ago
  86. 56a1a69 sign_extend_inreg needs to be expanded for pre-v6 Thumb as well as ARM. by Bob Wilson · 15 years ago
  87. dc076da Fix error message to match function name. by Bob Wilson · 15 years ago
  88. 0110ac6 Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them. by Evan Cheng · 15 years ago
  89. ef6eb9c back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set) by Jim Grosbach · 15 years ago
  90. 68741be Enable Expand handling of atomics for subtargets that can't do them inline. by Jim Grosbach · 15 years ago
  91. c66cdf7 Enable tail calls on ARM by default, with some basic tests. by Dale Johannesen · 15 years ago
  92. df50d7e Last round of changes for ARM tail calls. Not turning them on yet. by Dale Johannesen · 15 years ago
  93. 0d8ba33 Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86 by Jakob Stoklund Olesen · 15 years ago
  94. 7072cf6 Thumb1 and any pre-v6 ARM target should use the libcall expansion of by Jim Grosbach · 15 years ago
  95. c73993b simplify code a bit and add a more explanatory assert for cases that by Jim Grosbach · 15 years ago
  96. 7616b64 format and 80-column cleanup by Jim Grosbach · 15 years ago
  97. 07f6e80 Remove the hidden "neon-reg-sequence" option. The reg sequences are working by Bob Wilson · 15 years ago
  98. 46df4eb Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. by Evan Cheng · 15 years ago
  99. 6470a11 Next round of tail call changes. Register used in a tail by Dale Johannesen · 15 years ago
  100. 827b210 Add basic support for NEON modified immediates besides VMOV. by Bob Wilson · 15 years ago