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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 6e590e3f61b101554f97d6ab257c802c9ec49862
  1. 75c0d8e [Support] Drop verbose _ATTRIBUTE from LLVM_ATTRIBUTE_{READONLY,READNONE} macro by Daniel Dunbar · 13 years ago
  2. 89d8139 TableGen/CodeEmitterGen.cpp: Fix an expression of generating bitmask. by NAKAMURA Takumi · 13 years ago
  3. 63054f9 test/MC/X86/lit.local.cfg: Fix up to detect 'X86' in targets. by NAKAMURA Takumi · 13 years ago
  4. 6f1d799 Eliminate switch cases that can never match, for example removes all by Duncan Sands · 13 years ago
  5. 7415659 Add support for r600 (AMD GPUs HD2XXX - HD6XXX) target triplet. by Anton Korobeynikov · 13 years ago
  6. 00cbccc Factor out the analysis of addition and subtraction in ComputeMaskedBits. Reuse by Nick Lewycky · 13 years ago
  7. 5ae0427 [llvm.py] Initial skeleton for Python LLVM bindings by Gregory Szorc · 13 years ago
  8. 1fabd9f misched: handle scheduling region boundaries nicely. by Andrew Trick · 13 years ago
  9. 72051bf Use uint16_t to store opcodes in static tables in X86 backend. by Craig Topper · 13 years ago
  10. e38ec24 Fix undefined behavior in the Mips backend. by Ahmed Charles · 13 years ago
  11. 68675c6 misched interface: rename Begin/End to RegionBegin/RegionEnd since they are not private. by Andrew Trick · 13 years ago
  12. d24da97 misched comments by Andrew Trick · 13 years ago
  13. 7799eb4 revert 152356: verify misched changes using -misched=shuffle. by Andrew Trick · 13 years ago
  14. 0058740 Fix a silly restriction on the fast-path for hash_combine_range. This by Chandler Carruth · 13 years ago
  15. e8187e0 Undo a previous restriction on the inline cost calculation which Nick by Chandler Carruth · 13 years ago
  16. abd6674 Fix a regression from r147481. by Chad Rosier · 13 years ago
  17. d04ec0c misched: allow the default scheduler to be one chosen by the target. by Andrew Trick · 13 years ago
  18. f91a330 Added TargetPassConfig::enablePass by Andrew Trick · 13 years ago
  19. 9ad62b3 Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin(). by Evan Cheng · 13 years ago
  20. cdaedf9 Silence unused function warning when graphviz is not available. by Benjamin Kramer · 13 years ago
  21. 72af527 Remove the no longer existent psp triple from a test. by Benjamin Kramer · 13 years ago
  22. 4445215 Have llvm-mc --version print the list of registered targets like llc does. by Duncan Sands · 13 years ago
  23. ed5edea Revert commit 152300 (ddunbar) since it still seems to be breaking by Duncan Sands · 13 years ago
  24. fac2598 Use uint16_t to store instruction implicit uses and defs. Reduces static data. by Craig Topper · 13 years ago
  25. 9eddc1c [ADT] Change the trivial FoldingSetNodeID::Add* methods to be inline, reapplied by Daniel Dunbar · 13 years ago
  26. c10fa6c Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012: by Stepan Dyatkovskiy · 13 years ago
  27. 88d2fa4 Re-commit r152202 hopefully fixing the MSVC linker error. by Craig Topper · 13 years ago
  28. 8c0152f Revert r152288, "[ADT] Change the trivial FoldingSetNodeID::Add* methods to be by Daniel Dunbar · 13 years ago
  29. d4b0a06 Test case for r152280, r152285 and r152290. by Akira Hatanaka · 13 years ago
  30. ee8c3b0 Invoke setTargetDAGCombine for SELECT. by Akira Hatanaka · 13 years ago
  31. 3f778c2 [ADT] Change the trivial FoldingSetNodeID::Add* methods to be inline. by Daniel Dunbar · 13 years ago
  32. e2bdf7f Swap the operands of a select node if the false (the second) operand is 0. by Akira Hatanaka · 13 years ago
  33. 6f130bf Rotate two of the functions used to count bonuses for the inline cost by Chandler Carruth · 13 years ago
  34. 5fdf500 Set minimum function alignment to 3 if target is Mips64. by Akira Hatanaka · 13 years ago
  35. 7065b7b This patch eliminates redundant instructions that produce 0. by Akira Hatanaka · 13 years ago
  36. c174eaf misched interface: Expose the MachineScheduler pass. by Andrew Trick · 13 years ago
  37. fd03ccd ARM don't use MCRelaxAll, as it's not safe on ARM. by Jim Grosbach · 13 years ago
  38. 61dfa77 Improved support in RuntimeDyldMachO for generating by Sean Callanan · 13 years ago
  39. 7afcda0 Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface. by Andrew Trick · 13 years ago
  40. ed395c8 misched prep: Expose the ScheduleDAGInstrs interface so targets may by Andrew Trick · 13 years ago
  41. ed8a0ec misched prep: Remove LLVM_LIBRARY_VISIBILITY from ScheduleDAGInstrs. by Andrew Trick · 13 years ago
  42. d790cad misched prep: Comment the ScheduleDAGInstrs interface. by Andrew Trick · 13 years ago
  43. 035ec40 misched prep: Cleanup ScheduleDAGInstrs interface. by Andrew Trick · 13 years ago
  44. 21c5355 misched prep: remove extra "protected" by Andrew Trick · 13 years ago
  45. cf46b5a misched prep: rename InsertPos to End. by Andrew Trick · 13 years ago
  46. 953be89 misched preparation: rename core scheduler methods for consistency. by Andrew Trick · 13 years ago
  47. f03e62a Copy the right amount of elements. by Benjamin Kramer · 13 years ago
  48. 24e0e7c SmallPtrSet: Copy all the elements when swapping, not just numelements. by Benjamin Kramer · 13 years ago
  49. 44c98b7 [fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point by Chad Rosier · 13 years ago
  50. 6507d84 Use llvm-mc instead of llc. Patch by Jack Carter. by Rafael Espindola · 13 years ago
  51. 8c3d258 configure: Don't require a perl interpreter to be present, LLVM's buildsystem doesn't depend on perl anymore. by Benjamin Kramer · 13 years ago
  52. 3c77794 Revert r152202 as it's causing internal buildbot failures. by Chad Rosier · 13 years ago
  53. a2da788 Fix infinite loop in nested multiclasses. by Jakob Stoklund Olesen · 13 years ago
  54. cbfc117 Try a completely different approach to this type trait to appease older by Chandler Carruth · 13 years ago
  55. ff12877 Attempt #2 at appeasing GCC 4.3. This compiler really doesn't like these traits. by Chandler Carruth · 13 years ago
  56. b53a1d6 Try to clarify this comment some. by Chandler Carruth · 13 years ago
  57. a1eb50f Switch the is_integral_or_enum trait machinery to use an explicit by Chandler Carruth · 13 years ago
  58. 4e5b0f9 What's better than fixing and simplifying broken hash functions? by Chandler Carruth · 13 years ago
  59. fc22625 Remove another outbreak of customized (and completely broken) hashing. by Chandler Carruth · 13 years ago
  60. d4d8b2a Add support to the hashing infrastructure for automatically hashing both by Chandler Carruth · 13 years ago
  61. 5b2749a Where the BranchFolding pass removes a branch then adds another better branch, by Bill Wendling · 13 years ago
  62. 8c1161a Fix cmake by Andrew Trick · 13 years ago
  63. 6fd7dd6 comment by Andrew Trick · 13 years ago
  64. 47c1445 misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles. by Andrew Trick · 13 years ago
  65. 7b58ae7 ScheduleDAGInstrs comments by Andrew Trick · 13 years ago
  66. 84b454d misched preparation: modularize schedule emission. by Andrew Trick · 13 years ago
  67. 73ba69b misched preparation: modularize schedule printing. by Andrew Trick · 13 years ago
  68. 4c72720 misched preparation: modularize schedule verification. by Andrew Trick · 13 years ago
  69. dbdca36 whitespace by Andrew Trick · 13 years ago
  70. d3c9d94 Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect all 16-bit string table offsets. Also make sure the string to offset table string is not larger than 65536 characters since larger string literals aren't portable. by Craig Topper · 13 years ago
  71. bb9dbb7 Missing change in r152106 for TinyPtrVector. by Eli Friedman · 13 years ago
  72. eea81f3 Switch this code to use hash_combine_range rather than incremental calls by Chandler Carruth · 13 years ago
  73. f8cde73 Cache the sized-ness of struct types, once we reach the steady state of by Chandler Carruth · 13 years ago
  74. 344224b Remove an accidental cut/paste of a comment into the middle of by Chandler Carruth · 13 years ago
  75. 891495e No functionality change. Type::isSized() can be expensive, so avoid calling it by Nick Lewycky · 13 years ago
  76. 05d88f4 ARM pre-v6 assembly parsing for umull/smull. by Jim Grosbach · 13 years ago
  77. 0104dd3 ARM pre-v6 alias for 'nop' to 'mov r0, r0' by Jim Grosbach · 13 years ago
  78. ff3164a Tidy up. Remove dead code that slipped into previous commit. by Jim Grosbach · 13 years ago
  79. 255cd51 Added -view-background to avoid waiting for each GraphViz invocation. by Andrew Trick · 13 years ago
  80. 0df7f88 Added -view-misched=dags options. by Andrew Trick · 13 years ago
  81. 56b94c5 Cleanup in preparation for misched: Move DAG visualization logic. by Andrew Trick · 13 years ago
  82. 8ceaa66 Added MachineBasicBlock::getFullName() to standardize/factor codegen diagnostics. by Andrew Trick · 13 years ago
  83. acddd49 whitespace by Andrew Trick · 13 years ago
  84. 084e179 Cleanup: DAG building is specific to either SD or MI scheduling. Not part of the target interface. by Andrew Trick · 13 years ago
  85. e75537a misched comments by Andrew Trick · 13 years ago
  86. 6cfb14f misched: Use the StartBlock/FinishBlock hooks by Andrew Trick · 13 years ago
  87. 8938895 Add the DW_AT_APPLE_runtime_class attribute to forward declarations by Eric Christopher · 13 years ago
  88. 03be362 Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation). by Evan Cheng · 13 years ago
  89. 4d0983a ARM more NEON VLD/VST composite physical register refactoring. by Jim Grosbach · 13 years ago
  90. c511c28 Hoist common code out of if statement. by Jakob Stoklund Olesen · 13 years ago
  91. c0fc450 ARM refactor more NEON VLD/VST instructions to use composite physregs by Jim Grosbach · 13 years ago
  92. 40530ad Fix support for encodings up to 64-bits in length. TableGen was silently truncating them to 32-bits prior to this. by Owen Anderson · 13 years ago
  93. 2945a32 SmallPtrSet: Provide a more efficient implementation of swap than the default triple-copy std::swap. by Benjamin Kramer · 13 years ago
  94. 54427e5 Fix the operand ordering on aliases for shld and shrd. PR12173, part 2. by Eli Friedman · 13 years ago
  95. f0a6813 Add new load commands for MachO. by Ted Kremenek · 13 years ago
  96. 9566905 build/Darwin: Make it easy to cause all tools to get codesigned (with make CODESIGN_TOOLS=1). by Daniel Dunbar · 13 years ago
  97. bde1b2a Tidy up. Kill some dead code. by Jim Grosbach · 13 years ago
  98. 14f87e0 Allow the same types in DPair as in QPR. by Jakob Stoklund Olesen · 13 years ago
  99. 158c8a4 Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. by Kevin Enderby · 13 years ago
  100. e46137f Convert PowerPC to register mask operands. by Roman Divacky · 13 years ago