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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 79f06f3cbcf2cb0394d33382186c31f2967cb400 / lib / Target
  1. 79f06f3 Add build rules for MIPS. by Logan Chien · 13 years ago
  2. 1429059 Merge with LLVM upstream r145126 (Nov 25th 2011) by Logan Chien · 13 years ago
  3. 705f243 Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64. by Craig Topper · 13 years ago
  4. f475a55 Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse the 128-bit versions and let the vector type distinguish. by Craig Topper · 13 years ago
  5. 9d399b1 X86: alias cqo to cqto. by Benjamin Kramer · 13 years ago
  6. 421455f This patch makes the following changes necessary for MIPS' direct code emission. by Akira Hatanaka · 13 years ago
  7. 84bfc2f This patch addresses gp relative fixups/relocations for jump tables. by Akira Hatanaka · 13 years ago
  8. f238f50 X86: Use btq for bit tests if the immediate can't be encoded in 32 bits. by Benjamin Kramer · 13 years ago
  9. 52a35a8 I added several lines in X86 code generator that allow to choose by Elena Demikhovsky · 13 years ago
  10. 7f5e43f Fix PR11422. by Jakob Stoklund Olesen · 13 years ago
  11. 768c65f add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern by Hal Finkel · 13 years ago
  12. 796c193 More fixes to the X86InstComments for shuffle instructions. In particular add AVX flavors of many instructions and fix the destination operand for some of the existing AVX entries. by Craig Topper · 13 years ago
  13. f7de577 Fix shuffle decoding logic to handle UNPCKLPS/UNPCKLPD on 256-bit vectors correctly. Add support for decoding UNPCKHPS/UNPCKHPD for AVX 128-bit and 256-bit forms. by Craig Topper · 13 years ago
  14. c0d8285 Add methods for querying minimum SSE version along with AVX. Simplifies all the places that had to check a version of SSE and AVX. by Craig Topper · 13 years ago
  15. 6fa583d Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled. by Craig Topper · 13 years ago
  16. 6347e86 Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if AVX2 is enabled. by Craig Topper · 13 years ago
  17. a124f94 Make LowerSIGN_EXTEND_INREG split 256-bit vectors when AVX1 is enabled and use AVX2 shifts when AVX2 is enabled. by Craig Topper · 13 years ago
  18. 0d86d46 Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine. by Craig Topper · 13 years ago
  19. 745a86b Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled. by Craig Topper · 13 years ago
  20. ba798c5 Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns. by Craig Topper · 13 years ago
  21. 98fc729 Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns. by Craig Topper · 13 years ago
  22. 54f952a Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors. by Craig Topper · 13 years ago
  23. 3113384 Collapse X86 PSIGNB/PSIGNW/PSIGND node types. by Craig Topper · 13 years ago
  24. 1666cb6 Extend VPBLENDVB and VPSIGN lowering to work for AVX2. by Craig Topper · 13 years ago
  25. 60d9a92 Remove unused parameters from the AVX maskmov classes. by Craig Topper · 13 years ago
  26. cbbe33f Add AVX2 vpbroadcast support by Nadav Rotem · 13 years ago
  27. 424fe0e Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work/dead code. by Chad Rosier · 13 years ago
  28. 944d82b Add TODO comment. by Chad Rosier · 13 years ago
  29. d90a191 Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments. by Craig Topper · 13 years ago
  30. 2fb82ce Dead code. by Chad Rosier · 13 years ago
  31. ec43d1f Remove seemingly unnecessary duplicate VROUND definitions. by Craig Topper · 13 years ago
  32. 9d434db Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom by Eli Friedman · 13 years ago
  33. 3bdb3c9 Don't unconditionally set the kill flag. rdar://10456186 by Chad Rosier · 13 years ago
  34. d224c78 Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing. by Eli Friedman · 13 years ago
  35. 2abba84 Generalize the fixup info for ARM mode. by Jim Grosbach · 13 years ago
  36. 620db89 Lower 64-bit constant pool node. by Akira Hatanaka · 13 years ago
  37. 9b944a8 Lower 64-bit block address. by Akira Hatanaka · 13 years ago
  38. b84acd2 Fix encoding of NOP used for padding in ARM mode .align. by Jim Grosbach · 13 years ago
  39. 74c7634 Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool by Akira Hatanaka · 13 years ago
  40. 4fd40b3 64-bit jump register instruction. by Akira Hatanaka · 13 years ago
  41. 2b89498 Another missing X86ISD::MOVLPD pattern. rdar://10450317 by Evan Cheng · 13 years ago
  42. 40a86ee ARM assembly parsing for shifted register operands for MOV instruction. by Jim Grosbach · 13 years ago
  43. efed3d1 Clean up debug printing of ARM shifted operands. by Jim Grosbach · 13 years ago
  44. b598b04 ARM assmebly two operand forms for LSR, ASR, LSL, ROR register. by Jim Grosbach · 13 years ago
  45. 48b368b ARM assembly parsing for RRX mnemonic. by Jim Grosbach · 13 years ago
  46. cd75e44 Added missing comment about new custom lowering of DEC64 by Pete Cooper · 13 years ago
  47. 508a1f4 Check to make sure we can select the instruction before trying to put the by Chad Rosier · 13 years ago
  48. 23f2207 ARM mode aliases for bitwise instructions w/ register operands. by Jim Grosbach · 13 years ago
  49. d0405aa Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup. by Bob Wilson · 13 years ago
  50. 5c283e9 lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled. by NAKAMURA Takumi · 13 years ago
  51. b95fc31 Sink codegen optimization level into MCCodeGenInfo along side relocation model by Evan Cheng · 13 years ago
  52. 12755b0 Fix the execution domain on a bunch of SSE/AVX instructions. by Craig Topper · 13 years ago
  53. eaab6ef Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602> by Bob Wilson · 13 years ago
  54. 2713d04 Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636. by Craig Topper · 13 years ago
  55. f56c60b Add FIXME comment. by Chad Rosier · 13 years ago
  56. 3805d85 Enable -widen-vmovs by default. by Jakob Stoklund Olesen · 13 years ago
  57. e43862b ARM assembly parsing for register range syntax for VLD/VST register lists. by Jim Grosbach · 13 years ago
  58. 5b2fb20 ARM assembly parsing for data type suffices on NEON VMOV aliases. by Jim Grosbach · 13 years ago
  59. f8c10e5 AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vbroadcast code. by Nadav Rotem · 13 years ago
  60. 9f302c4 ARM assembly parsing two operand forms for shift instructions. by Jim Grosbach · 13 years ago
  61. 88d012a ARM VFP assembly parsing for VADD and VSUB two-operand forms. by Jim Grosbach · 13 years ago
  62. 6cb4b08 ARM accept an immediate offset in memory operands w/o the '#'. by Jim Grosbach · 13 years ago
  63. 2d49689 Added custom lowering for load->dec->store sequence in x86 when the EFLAGS registers is used by Pete Cooper · 13 years ago
  64. 5c984e4 ARM enclosing curly braces optional on one-register VLD/VST instruction lists. by Jim Grosbach · 13 years ago
  65. eaf2056 ARM size suffix on VFP single-precision 'vmov' is optional. by Jim Grosbach · 13 years ago
  66. 25e0a87 Fix typo. by Jim Grosbach · 13 years ago
  67. 19885de ARM alternate size suffices for VTRN instructions. by Jim Grosbach · 13 years ago
  68. 22925d9 Fix a misplaced paren bug. by Owen Anderson · 13 years ago
  69. a68e90c ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. by Jim Grosbach · 13 years ago
  70. bfb0a17 ARM assembly parsing for two-operand form of 'mul' instruction. by Jim Grosbach · 13 years ago
  71. d2586da ARM assembly parsing for two-operand form of 'mul' instruction. by Jim Grosbach · 13 years ago
  72. 7f1ec95 Thumb2 two-operand 'mul' instruction wide encoding parsing. by Jim Grosbach · 13 years ago
  73. b589be9 Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. by Owen Anderson · 13 years ago
  74. 1de0bd1 Thumb2 assembly parsing for mul.w in IT block fix. by Jim Grosbach · 13 years ago
  75. 1b71950 Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bit by Akira Hatanaka · 13 years ago
  76. ac20aad Set nomacro before emitting the sequence of instructions that set global pointer by Akira Hatanaka · 13 years ago
  77. 1604085 Simplify function PassByValArg64. by Akira Hatanaka · 13 years ago
  78. 870b3b2 Delete files. by Akira Hatanaka · 13 years ago
  79. 73c38f0 Remove MipsMCSymbolRefExpr. by Akira Hatanaka · 13 years ago
  80. c5a6a68 ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions. by Jim Grosbach · 13 years ago
  81. 36abbec Apply changes to migrate to llvm upstream r144606. by Logan Chien · 13 years ago
  82. bf8356b Fix typo in comment. by Jay Foad · 13 years ago
  83. 978e0df Make use of MachinePointerInfo::getFixedStack. This removes all mention by Jay Foad · 13 years ago
  84. d9190c0 Remove some unnecessary includes of PseudoSourceValue.h. by Jay Foad · 13 years ago
  85. f9c1b92 Merge with LLVM upstream r144606 (Nov 15th 2011) by Logan Chien · 13 years ago
  86. 44ec9fd Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 256-bit integer instructions when AVX2 isn't enabled. by Craig Topper · 13 years ago
  87. 4c077a1 Properly qualify AVX2 specific parts of execution dependency table. Also enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370. by Craig Topper · 13 years ago
  88. eaa192a Add vmov.f32 to materialize f32 immediate splats which cannot be handled by by Evan Cheng · 13 years ago
  89. bfc9429 ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions. by Jim Grosbach · 13 years ago
  90. c2ecf3e Break false dependencies before partial register updates. by Jakob Stoklund Olesen · 13 years ago
  91. dd47e0b ARM parsing datatype suffix variants for non-writeback VST1 instructions. by Jim Grosbach · 13 years ago
  92. e052b9a ARM parsing datatype suffix variants for non-writeback VLD1 instructions. by Jim Grosbach · 13 years ago
  93. 04db7f7 Add explanatory comment. by Jim Grosbach · 13 years ago
  94. 0530d0d Split out the plain '.{8|16|32|64}' suffix handling. by Jim Grosbach · 13 years ago
  95. ef44876 ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions. by Jim Grosbach · 13 years ago
  96. 2c42b8c Supporting inline memmove isn't going to be worthwhile. The only way to avoid by Chad Rosier · 13 years ago
  97. ffc658b ARM VLDR/VSTR instructions don't need a size suffix. by Jim Grosbach · 13 years ago
  98. 909cb4f Add support for inlining small memcpys. rdar://10412592 by Chad Rosier · 13 years ago
  99. e489af8 Fix a performance regression from r144565. Positive offsets were being lowered by Chad Rosier · 13 years ago
  100. 02e3d92 ARM assembly parsing type suffix options for VLDR/VSTR. by Jim Grosbach · 13 years ago