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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 79f06f3cbcf2cb0394d33382186c31f2967cb400 / lib / Target
  1. 76c8f08 Add a missing pattern for X86ISD::MOVLPD. rdar://10436044 by Evan Cheng · 13 years ago
  2. 57b2997 Add support for Thumb load/stores with negative offsets. rdar://10412592 by Chad Rosier · 13 years ago
  3. 6296ee3 Unbreak Release builds. by Benjamin Kramer · 13 years ago
  4. a77214a Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom lowered by Pete Cooper · 13 years ago
  5. 788dc0f 32-to-64-bit extended load. by Akira Hatanaka · 13 years ago
  6. 4961709 AnalyzeCallOperands function for N32/64. by Akira Hatanaka · 13 years ago
  7. bad53f4 Modify LowerFormalArguments to correctly handle vaarg arguments for Mips64. by Akira Hatanaka · 13 years ago
  8. a3f7e22 PTX: Let LLVM use loads/stores for all mem* intrinsics, instead of relying on custom implementations. by Justin Holewinski · 13 years ago
  9. 47a4ab8 Remove variable that keeps the size of area used to save byval or variable by Akira Hatanaka · 13 years ago
  10. 430052b Tidy up. 80 column. by Jim Grosbach · 13 years ago
  11. d8fb2f4 If we have to reset the calculation of the compact encoding, then also reset the by Bill Wendling · 13 years ago
  12. 39c7472 Add support for using MVN to materialize negative constants. rdar://10412592 by Chad Rosier · 13 years ago
  13. 45daa4d LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler. by Daniel Dunbar · 13 years ago
  14. fa2768f Thumb2 ldm/stm updating w/ one register in the list are LDR/STR. by Jim Grosbach · 13 years ago
  15. 036bfcb ARM let processInstruction() tranforms chain. by Jim Grosbach · 13 years ago
  16. 2cb212c Thumb2 parsing for push/pop w/ hi registers in the reglist. by Jim Grosbach · 13 years ago
  17. a475051 Thumb1 diagnostics for reglist on PUSH/POP fix. by Jim Grosbach · 13 years ago
  18. 57cada0 Thumb MUL assembly parsing for 3-operand form. by Jim Grosbach · 13 years ago
  19. 25a5df8 build/MBlazeDisassembler: Some compilers may generate an MBlaze disassembler by Daniel Dunbar · 13 years ago
  20. d382fcf When in ARM mode, LDRH/STRH require special handling of negative offsets. by Chad Rosier · 13 years ago
  21. ffe92f3 ARM .thumb_func directive for quoted symbol names. by Jim Grosbach · 13 years ago
  22. 668da49 ARM assembly parsing for LSR/LSL/ROR(immediate). by Jim Grosbach · 13 years ago
  23. 00a95c0 ARM assembly parsing for ASR(immediate). by Jim Grosbach · 13 years ago
  24. 71c301f build: Rename CBackend and CppBackend libraries to have CodeGen suffix, for by Daniel Dunbar · 13 years ago
  25. f4e8cb1 AVX2: Add variable shift from memory. by Nadav Rotem · 13 years ago
  26. 8281926 For immediate encodings of icmp, zero or sign extend first. Then by Chad Rosier · 13 years ago
  27. 13293dc build/Make & CMake: Pass the appropriate --native-target and --enable-targets by Daniel Dunbar · 13 years ago
  28. e5345b6 llvm-build: Add --native-target and --enable-targets options, and add logic to by Daniel Dunbar · 13 years ago
  29. 9f65f84 llvm-build: Change CBackend and CppBackend to not use library_name. This will by Daniel Dunbar · 13 years ago
  30. 4e2b002 llvm-build: Add an explicit component type to represent targets. by Daniel Dunbar · 13 years ago
  31. 86de950 Tidy up. by Jim Grosbach · 13 years ago
  32. 30b4e6b Thumb2 assembly parsing STMDB w/ optional .w suffix. by Jim Grosbach · 13 years ago
  33. 1e962ce Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM. by Eli Friedman · 13 years ago
  34. 909511e The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12. by Chad Rosier · 13 years ago
  35. 9a0fef9 AVX2: Add patterns for variable shift operations by Nadav Rotem · 13 years ago
  36. 013292f Remove unnecessary include. by Devang Patel · 13 years ago
  37. f92f39d Add AVX2 support for vselect of v32i8 by Nadav Rotem · 13 years ago
  38. 46e01fc Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions. by Craig Topper · 13 years ago
  39. db865cb Add instruction selection for AVX2 integer comparisons. by Craig Topper · 13 years ago
  40. a876204 Add AVX2 instruction lowering for add, sub, and mul. by Craig Topper · 13 years ago
  41. 6f4c56b Add support for encoding immediates in icmp and fcmp. Hopefully, this will by Chad Rosier · 13 years ago
  42. 099dcdb Hide cpu name checking in ARMSubtarget. by Evan Cheng · 13 years ago
  43. 9056fd3 Properly handle Mips MC relocations and lower cpload and cprestore macros to MCInsts. by Bruno Cardoso Lopes · 13 years ago
  44. 77e6488 Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs. by Evan Cheng · 13 years ago
  45. a86af3e ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this. by Chad Rosier · 13 years ago
  46. 22d43e3 Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported. by Lang Hames · 13 years ago
  47. 67f0267 Added invariant field to the DAG.getLoad method and changed all calls. by Pete Cooper · 13 years ago
  48. cf81b61 This patch handles unaligned loads and stores in Mips JIT. Mips backend by Bruno Cardoso Lopes · 13 years ago
  49. 1a262aa PPCInstrInfo.cpp: Fix one "unused" warning. by NAKAMURA Takumi · 13 years ago
  50. 337e63a Make sure to mark vector extload's as expand on ARM. Fixes PR11319. by Eli Friedman · 13 years ago
  51. 6e1b87a Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222 by Evan Cheng · 13 years ago
  52. 7c1a2ac Enable support for returning i1, i8, and i16. Nothing special todo as it's the by Chad Rosier · 13 years ago
  53. 00779a9 Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling convention as well. by Chad Rosier · 13 years ago
  54. fecb954 Various Mips64 floating point instruction patterns. by Akira Hatanaka · 13 years ago
  55. 82ee43d Add definition of the base class for floating point comparison instructions by Akira Hatanaka · 13 years ago
  56. 9bef4a4 Add code needed for copying between 64-bit integer and floating pointer by Akira Hatanaka · 13 years ago
  57. d084e7f Add definitions of 64-bit instructions which move data between integer and by Akira Hatanaka · 13 years ago
  58. 66f7239 Simplify some uses of utohexstr. by Benjamin Kramer · 13 years ago
  59. 8873ea7 Simplify code. No functionality change. by Benjamin Kramer · 13 years ago
  60. 77a8ab8 Expand V_SET0 to xorps by default. by Jakob Stoklund Olesen · 13 years ago
  61. c9c59e5 Add definition of 64-bit load upper immediate. by Akira Hatanaka · 13 years ago
  62. e8e99cb Include RegSaveAreaSize in the computation of stack size. by Akira Hatanaka · 13 years ago
  63. be5a008 Define functions that get or set the size of area on callee's stack frame which by Akira Hatanaka · 13 years ago
  64. 5384958 Use array_lengthof to compute the number of iterations of a loop. by Akira Hatanaka · 13 years ago
  65. d0e9704 Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted by Akira Hatanaka · 13 years ago
  66. 5beeac0 Make the type of shift amount i32 in order to reduce the number of shift by Akira Hatanaka · 13 years ago
  67. a608b93 Add 64-bit to 32-bit trunc pattern. by Akira Hatanaka · 13 years ago
  68. 28f0327 Add AVX2 variable shift instructions and intrinsics. by Craig Topper · 13 years ago
  69. d50ebef Add AVX2 VPMOVMASK instructions and intrinsics. by Craig Topper · 13 years ago
  70. 9a7fc32 Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects. by Craig Topper · 13 years ago
  71. cacd78c More AVX2 instructions and their intrinsics. by Craig Topper · 13 years ago
  72. 7b135ae Replace (Lower|Upper)caseString in favor of StringRef's newest methods. by Benjamin Kramer · 13 years ago
  73. b263cfb Add more AVX2 instructions and intrinsics. by Craig Topper · 13 years ago
  74. 011369b Add support for passing i1, i8, and i16 call parameters. Also, be sure to by Chad Rosier · 13 years ago
  75. 4eb73c5 Add more PRI.64 macros for MSVC and use them throughout the codebase. by Benjamin Kramer · 13 years ago
  76. 071de11 Allow i1 to be promoted to i32 for ARM APCS calling convention. by Chad Rosier · 13 years ago
  77. 418a20d Enhanced vzeroupper insertion pass that avoids inserting vzeroupper where it is unnecessary through local analysis. Patch from Bruno Cardoso Lopes, with some additional changes. by Eli Friedman · 13 years ago
  78. 9c8c096 Cannot create a result register for non-legal types. by Chad Rosier · 13 years ago
  79. 1ed7ead When materializing an i32, SExt vs ZExt doesn't matter when we're trying to fit by Chad Rosier · 13 years ago
  80. 5668649 Enable support for materializing i1, i8, and i16 integers via move immediate. by Chad Rosier · 13 years ago
  81. 2a2d3bc build/cmake: Coalesce the configuration time header include fragment generation by Daniel Dunbar · 13 years ago
  82. 0e063f5 build/cmake: Use tblgen macro directly instead of llvm_tablegen, which just by Daniel Dunbar · 13 years ago
  83. 1014eac Add missing argument for atomic instructions in c++ backend. PR11268, part 2. by Eli Friedman · 13 years ago
  84. 4435959 Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions by Craig Topper · 13 years ago
  85. 98520aa Fix some minor scheduling itinerary bug. It's not expected to actually affect codegen. by Evan Cheng · 13 years ago
  86. a4c975b Indentation. by Chad Rosier · 13 years ago
  87. 2ec6ba0 Add fast-isel support for returning i1, i8, and i16. by Chad Rosier · 13 years ago
  88. dd21ce8 Reapply r143206, with fixes. Disallow physical register lifetimes by Dan Gohman · 13 years ago
  89. 999481f fixed global array handling for ptx to use the correct bit widths by Dan Bailey · 13 years ago
  90. 00ade8b build: Add initial cut at LLVMBuild.txt files. by Daniel Dunbar · 13 years ago
  91. 966d8f9 Add new X86 AVX2 VBROADCAST instructions. by Craig Topper · 13 years ago
  92. 33ad4cc Add support for sign-extending non-legal types in SelectSIToFP(). by Chad Rosier · 13 years ago
  93. e88f495 Fixed parameter name. by Lang Hames · 13 years ago
  94. 537a9f7 Try to lower memset/memcpy/memmove to vector instructions on ARM where the alignment permits. by Lang Hames · 13 years ago
  95. 07fa757 Add support for comparing integer non-legal types. by Chad Rosier · 13 years ago
  96. 3a81c52 Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. by Owen Anderson · 13 years ago
  97. bd513ea The rules disallowing single-register reglist operands only apply to the POP alias, not to LDM/STM instructions. Revert r143552. by Owen Anderson · 13 years ago
  98. 87f24f5 Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case. by Owen Anderson · 13 years ago
  99. 1e512f4 Factor out an EmitIntExt function. No functionality change intended. by Chad Rosier · 13 years ago
  100. 8778b0c More AVX2 instructions and intrinsics. by Craig Topper · 13 years ago