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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 79f06f3cbcf2cb0394d33382186c31f2967cb400 / lib / Target
  1. 25e2eb3 Add a bunch more X86 AVX2 instructions and their corresponding intrinsics. by Craig Topper · 13 years ago
  2. fe409dd Factor out a SelectTrunc function. No functionality change intended. by Chad Rosier · 13 years ago
  3. d70b178 ARM label operands can be quoted. by Jim Grosbach · 13 years ago
  4. 1ae3b2d ARM label operands can have an optional '#' before them. by Jim Grosbach · 13 years ago
  5. 1a2a45b Fix disassembly of some VST1 instructions. by Owen Anderson · 13 years ago
  6. 85f37f3 rename getHostTriple into getDefaultTargetTriple by Sebastian Pop · 13 years ago
  7. dcf660d Teach the x86 backend a couple tricks for dealing with v16i8 sra by a constant splat value. Fixes PR11289. by Eli Friedman · 13 years ago
  8. b5e39cc Don't fold negative offsets into cp / dp accesses to avoid relocation errors. by Richard Osborne · 13 years ago
  9. 06b2915 ARM VLD/VST assembly parsing for symbolic address operands. by Jim Grosbach · 13 years ago
  10. 218d71d Add support for new atomics to cpp backend. Misc other fixes while I'm here. PR11268. by Eli Friedman · 13 years ago
  11. c46f912 ARM VST1 w/ writeback assembly parsing and encoding. by Jim Grosbach · 13 years ago
  12. 2dc6846 ARM writeback vs. stride operands for VST/VLD. by Jim Grosbach · 13 years ago
  13. 65ebfa6 More not-crashing NEON disassembly updates for the vld refactoring. by Owen Anderson · 13 years ago
  14. 79e56ed Begin adding AVX2 instructions. No selection support yet other than intrinsics. by Craig Topper · 13 years ago
  15. e95b37f Switch new .file directive emission off by default, change llc's flag for it to by Nick Lewycky · 13 years ago
  16. 3a5e201 Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag. by Craig Topper · 13 years ago
  17. e0c4cc4 X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift and zero out the bits where zeros should've been shifted in. by Benjamin Kramer · 13 years ago
  18. 5065a50 by Nadav Rotem · 13 years ago
  19. e3aaf0c PPC: Disable moves for all CR subregisters. by Benjamin Kramer · 13 years ago
  20. 2ad3a89 Revert r143206, as there are still some failing tests. by Dan Gohman · 13 years ago
  21. a47e0da ARM mode 'mov' to 'mvn' assembler alias. by Jim Grosbach · 13 years ago
  22. 5ac24b0 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". by Jim Grosbach · 13 years ago
  23. 57838c6 Specify that the high bit of the alignment field is fixed to 0 on these instructions. by Owen Anderson · 13 years ago
  24. 512fde3 Make changes necessary in LowerFormalArguments to support Mips64. by Akira Hatanaka · 13 years ago
  25. 0f746d1 Make changes necessary in LowerCall to support Mips64. by Akira Hatanaka · 13 years ago
  26. ac60627 Add variable IsO32 to MipsTargetLowering. by Akira Hatanaka · 13 years ago
  27. 101a983 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. by Owen Anderson · 13 years ago
  28. 26b4f62 Reapply r143177 and r143179 (reverting r143188), with scheduler by Dan Gohman · 13 years ago
  29. 1752298 Revert r143202. by Owen Anderson · 13 years ago
  30. a5679cb Specify fixed bits on CPS instructions to enable roundtripping. by Owen Anderson · 13 years ago
  31. 5ce8e93 Thumb2 ADD/SUB instructions encoding selection outside IT block. by Jim Grosbach · 13 years ago
  32. 4866548 Speculatively disable Dan's commits 143177 and 143179 to see if by Duncan Sands · 13 years ago
  33. 0ffd02d Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW by Dan Gohman · 13 years ago
  34. ae74e2d ARM Allow 'q' registers in VLD/VST vector lists. by Jim Grosbach · 13 years ago
  35. fa86eb4 Remove the Alpha backend. by Dan Gohman · 13 years ago
  36. f2652f5 Add some NEON stores to the VLD decoding hook that were accidentally omitted previously. by Owen Anderson · 13 years ago
  37. 47a896b Also set addrmode6 alignment when align==size. by Jakob Stoklund Olesen · 13 years ago
  38. d619acd ARM isel for vld1, opcode selection for register stride post-index pseudos. by Jim Grosbach · 13 years ago
  39. 7861c3f Avoid partial CPSR dependency from loop backedges. rdar://10357570 by Evan Cheng · 13 years ago
  40. 98f3dff Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and by Kevin Enderby · 13 years ago
  41. 2aee84d Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix. by Jim Grosbach · 13 years ago
  42. 195041f Thumb2 t2MVNi assembly parsing to recognize ".w" suffix. by Jim Grosbach · 13 years ago
  43. d11ed82 A branch predicated on a constant can just FastEmit an unconditional branch. by Chad Rosier · 13 years ago
  44. 3835309 Rename NonScalarIntSafe to something more appropriate. by Lang Hames · 13 years ago
  45. 1acd83a Add a TODO comment. FastISel works by parsing each basic block from the bottom by Chad Rosier · 13 years ago
  46. b9b7957 Factor a little more code into EmitCmp, which should have been done in the first by Chad Rosier · 13 years ago
  47. ac99463 Use EmitCmp in SelectBranch. No functional change intended. by Chad Rosier · 13 years ago
  48. 2e048e0 Factor out an EmitCmp function that can be used by both SelectCmp and by Chad Rosier · 13 years ago
  49. e6fd12e Thumb2 ldr pc-relative encoding fixes. by Jim Grosbach · 13 years ago
  50. 5ec87ab Fixes an issue reported by -verify-machineinstrs. by Rafael Espindola · 13 years ago
  51. 78794d3 ARM parse parenthesized expressions for label references. by Jim Grosbach · 13 years ago
  52. b367d04 This commit introduces two fake instructions MORESTACK_RET and by Rafael Espindola · 13 years ago
  53. 23ac055 Make sure short memsets on ARM lower to stores, even when optimizing for size. by Lang Hames · 13 years ago
  54. 20d912f Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern. by Jim Grosbach · 13 years ago
  55. e5bef7f Revert r142530 at least temporarily while a discussion is had on llvm-commits regarding exactly how much optsize should optimize for size over performance. by James Molloy · 13 years ago
  56. eb360ae Use a worklist to prevent the iterator from becoming invalidated because of the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot. by Bill Wendling · 13 years ago
  57. 918bdf0 Revert part of r142530. The patch potentially hurts performance especially by Evan Cheng · 13 years ago
  58. 7be0d8b Corrects previously incorrect $sp change in MipsCompilationCallback. by Bruno Cardoso Lopes · 13 years ago
  59. fd92758 ARM assembly parsing and encoding for VLD1 with writeback. by Jim Grosbach · 13 years ago
  60. c9ff319 Remove the Blackfin backend. by Dan Gohman · 13 years ago
  61. 062c27f Remove the SystemZ backend. by Dan Gohman · 13 years ago
  62. 6612871 Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction. by Jim Grosbach · 13 years ago
  63. 974c3ce ARM assembly parsing and encoding for VLD1 w/ writeback. by Jim Grosbach · 13 years ago
  64. 2adfd84 Don't crash on variable insertelement on ARM. PR10258. by Eli Friedman · 13 years ago
  65. 452c9fa ARMConstantPoolMBB::print should print BB number. by Evan Cheng · 13 years ago
  66. f121d4f ARM assembly parsing and encoding for VLD1 w/ writeback. by Jim Grosbach · 13 years ago
  67. a028cb5 ARM refactor am6offset usage for VLD1. by Jim Grosbach · 13 years ago
  68. 22766c6 Add support to the old JIT for acquire/release loads and stores on x86. PR11207. by Eli Friedman · 13 years ago
  69. 1d4b94f Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. by Owen Anderson · 13 years ago
  70. 887422c Change this overloaded use of Sched::Latency to be an overloaded by Dan Gohman · 13 years ago
  71. e214879 Remove the explicit request for "Latency" scheduling from MSP430, by Dan Gohman · 13 years ago
  72. ea830cd Thumb2 LDM instructions can target PC. Make sure to encode it. by Jim Grosbach · 13 years ago
  73. ac580fb Add X86 SARX, SHRX, and SHLX instructions. by Craig Topper · 13 years ago
  74. 9106886 Add X86 RORX instruction by Craig Topper · 13 years ago
  75. 8301760 Add X86 MULX instruction for disassembler. by Craig Topper · 13 years ago
  76. d07221a Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 multiply instructions. by Craig Topper · 13 years ago
  77. 1c7cab0 Move various generated tables into read-only memory, fixing up const correctness along the way. by Benjamin Kramer · 13 years ago
  78. bf486f0 Fix pr11193. by Nadav Rotem · 13 years ago
  79. 3b55bcb The different flavors of ARM have different valid subsets of registers. Check by Bill Wendling · 13 years ago
  80. 7d59e94 Assembly parsing for 4-register sequential variant of VLD2. by Jim Grosbach · 13 years ago
  81. abe29f3 Assembly parsing for 2-register sequential variant of VLD2. by Jim Grosbach · 13 years ago
  82. 795974e Assembly parsing for 4-register variant of VLD1. by Jim Grosbach · 13 years ago
  83. 9f769c6 Assembly parsing for 3-register variant of VLD1. by Jim Grosbach · 13 years ago
  84. 4d2df7a ARM VLD parsing and encoding. by Jim Grosbach · 13 years ago
  85. a55723f Don't automatically set the "fc" bits on MSR instructions if the user didn't ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing. by Owen Anderson · 13 years ago
  86. 4ba8dae Nuke an #if0 that got accidentally left in. by Jim Grosbach · 13 years ago
  87. f7dc1f6 whitespace. by Jim Grosbach · 13 years ago
  88. 3a312b8 Remove some outdated comments. by Jim Grosbach · 13 years ago
  89. c066193 Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with custom isel lowering code. by Craig Topper · 13 years ago
  90. 2660f84 Fix unused variable warning. by Richard Smith · 13 years ago
  91. 773762c Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. by Owen Anderson · 13 years ago
  92. 70c067e Disable the PPC hazard recognizer. It currently only supports by Dan Gohman · 13 years ago
  93. e9f08e0 Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures. by Owen Anderson · 13 years ago
  94. 531d3ad Add missing operand. <rdar://problem/10313323> by Bill Wendling · 13 years ago
  95. 2b516b9 Haven't yet found a nice way to handle TargetData verification in the by Lang Hames · 13 years ago
  96. 28e7809 Tidy up. Trailing whitespace. by Jim Grosbach · 13 years ago
  97. cc5c616 ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. by Jim Grosbach · 13 years ago
  98. 3e8ba1d ARM VTBX (one register) assembly parsing and encoding. by Jim Grosbach · 13 years ago
  99. 514e538 Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( by Chad Rosier · 13 years ago
  100. 57e77a2 Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10291355 by Evan Cheng · 13 years ago