Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / ade490a8297f7d7c9763ef173ce8b7607355b4e7 / utils
  1. d5b03f2 Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. by Evan Cheng · 13 years ago
  2. 6844f7b Hide more details in tablegen generated MCRegisterInfo ctor function. by Evan Cheng · 13 years ago
  3. 94b01f6 Add MCInstrInfo registeration machinery. by Evan Cheng · 13 years ago
  4. 22fee2d Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc by Evan Cheng · 13 years ago
  5. e837dea - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and by Evan Cheng · 13 years ago
  6. 4987033f Alternative name enum should go into the enum portion. by Evan Cheng · 13 years ago
  7. 6b8f1e3 ARM Assembly support for Thumb mov-immediate. by Jim Grosbach · 13 years ago
  8. 4db3748 Remove RCBarriers from TargetInstrDesc. by Evan Cheng · 13 years ago
  9. bea6f61 Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. by Owen Anderson · 13 years ago
  10. ebbbfd0 More refactoring. MC doesn't need know about subreg indices. by Evan Cheng · 13 years ago
  11. 73f50d9 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc by Evan Cheng · 13 years ago
  12. 025b37b Remove dead typedefs. by Evan Cheng · 13 years ago
  13. 5e6b460 Rename TargetRegisterDesc to MCRegisterDesc by Evan Cheng · 13 years ago
  14. 9c99cfe Revert "Shorten some ARM builtin names by removing unnecessary "neon" prefix." by Bob Wilson · 13 years ago
  15. e9e0e3a Shorten some ARM builtin names by removing unnecessary "neon" prefix. by Bob Wilson · 13 years ago
  16. f5fa52e - Add MCRegisterInfo registration machinery. Also added x86 registration routines. by Evan Cheng · 13 years ago
  17. 5c10b63 Make the generated InitXXXMCRegisterInfo function "static inline", so it doesn't get emitted into multiple object files. by Benjamin Kramer · 13 years ago
  18. a347f85 Starting to refactor Target to separate out code that's needed to fully describe by Evan Cheng · 13 years ago
  19. f2a5842 lit support for REQUIRES: asserts. by Andrew Trick · 13 years ago
  20. a7b1d17 Unbreak the CMake build by Francois Pichet · 13 years ago
  21. 0b6a44a Consolidate some TableGen diagnostic helper functions. by Jim Grosbach · 13 years ago
  22. 9b718e8 Skip fields that don't exist in the Register class. by Jakob Stoklund Olesen · 13 years ago
  23. 4ce25d5 Add a RegisterTuples class to Target.td and TableGen. by Jakob Stoklund Olesen · 13 years ago
  24. b231866 fix the varargs version of StructType::get to not require an LLVMContext, making usage by Chris Lattner · 13 years ago
  25. c6596e2 Use the correct comparator to avoid depending on pointer values. by Jakob Stoklund Olesen · 13 years ago
  26. abdbc84 Store CodeGenRegisters as pointers so they won't be reallocated. by Jakob Stoklund Olesen · 13 years ago
  27. 54c47c1 Remove MethodProtos/MethodBodies and allocation_order_begin/end. by Jakob Stoklund Olesen · 13 years ago
  28. b4c7048 Provide AltOrders for specifying alternative allocation orders. by Jakob Stoklund Olesen · 13 years ago
  29. 23b0766 Fix formatting. by Owen Anderson · 13 years ago
  30. 2559011 Prempt some obnoxious compiler from complaing about signed/unsigned compares. by Jakob Stoklund Olesen · 13 years ago
  31. 0cc0929 Make sure to pass an unsigned to a printf format that is always %u. by Jakob Stoklund Olesen · 13 years ago
  32. 05c087d Add support to lit for build mode requirements. e.g. by Andrew Trick · 13 years ago
  33. 77b4b13 Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. by Owen Anderson · 13 years ago
  34. f14bacc Update the Clang diagnostic emitter to emit IDs for diagnostic categories. by John McCall · 13 years ago
  35. 3a3465b Add a new function attribute, nonlazybind, which inhibits lazy-loading by John McCall · 13 years ago
  36. 1e56a2a Replace the statically generated hashtables for checking register relationships with just scanning the (typically tiny) static lists. by Owen Anderson · 13 years ago
  37. 59f26aa Use a SetTheory instance to expand register lists in register classes. by Jakob Stoklund Olesen · 13 years ago
  38. ae1920b Give CodeGenRegisterClass a real sorted member set. by Jakob Stoklund Olesen · 13 years ago
  39. 393c404 Improve the heuristic to emit the alias if the number of hard-coded registers by Bill Wendling · 13 years ago
  40. 7b9cafd Move the list of register classes into CodeGenRegBank as well. by Jakob Stoklund Olesen · 13 years ago
  41. 952036d Fix a compile time regression caused by too small hash tables. by Jakob Stoklund Olesen · 13 years ago
  42. 740e5b3 Heuristic: If the number of operands in the alias are more than the number of by Bill Wendling · 13 years ago
  43. b95fd2d Tweak hash function and compress hash tables. by Jakob Stoklund Olesen · 13 years ago
  44. bf710cc Remove now dead code. by Jakob Stoklund Olesen · 13 years ago
  45. 4091b05 Extract the generateHashTable function. by Jakob Stoklund Olesen · 13 years ago
  46. 026dc22 Compute lists of sub-regs, super-regs, and overlapping regs. by Jakob Stoklund Olesen · 13 years ago
  47. b5923db Move the list of registers into CodeGenRegBank. by Jakob Stoklund Olesen · 13 years ago
  48. dc29c44 Move some sub-register index calculations to CodeGenRegisters.cpp by Jakob Stoklund Olesen · 13 years ago
  49. f1e2b23 Move TableGen's register bank classes to their own source file. by Jakob Stoklund Olesen · 13 years ago
  50. e450a00 Add special-case range checking for VCVT_N intrinsic immediate operands. by Bob Wilson · 13 years ago
  51. 36a300a Fixed a few illegal paths with llvm_unreachable. Patch by Cameron McInally. by Chad Rosier · 13 years ago
  52. c017bc1 Drop a RecordKeeper reference that wasn't necessary. by Jakob Stoklund Olesen · 13 years ago
  53. 1023f5a Silence compiler warnings. by Jakob Stoklund Olesen · 13 years ago
  54. 1de9982 Teach TableGen to evaluate DAG expressions as set operations. by Jakob Stoklund Olesen · 13 years ago
  55. b2afe87 Rework the logic to not rely on undefined behaviour (1LL << 64). Also simplify. by Nick Lewycky · 13 years ago
  56. f462e3f Make it possible to have unallocatable register classes. by Jakob Stoklund Olesen · 13 years ago
  57. dd13790 Add new -d option to tblgen. It writes a make(1)-style dependency file. by Joerg Sonnenberger · 13 years ago
  58. 895c1e2 Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value by Bruno Cardoso Lopes · 13 years ago
  59. 6e03294 Use the dwarf->llvm mapping to print register names in the cfi directives. by Rafael Espindola · 13 years ago
  60. 7a067cc Introduce the DwarfRegAlias class for declaring that two registers have the by Rafael Espindola · 13 years ago
  61. bd0fa4c Change how tblgen generates attributes for intrinsics to use a single by John McCall · 13 years ago
  62. 7bf114c Fix the root cause of the bootstrap failure: by Rafael Espindola · 13 years ago
  63. 804cb23 [tablegen] A couple of changes to ClangDiagnosticEmmitter. by Argyrios Kyrtzidis · 13 years ago
  64. f415d8b Use a more efficient data structure for the "operand map". The number of by Bill Wendling · 13 years ago
  65. 3a2d255 Fix PR9947 by placing OPFL_MemRefs on the node using memory operands rather than by Cameron Zwarich · 13 years ago
  66. 2a8eb72 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. by Tanya Lattner · 13 years ago
  67. c81c970 vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. by Tanya Lattner · 13 years ago
  68. 4bfc6fb Downgrade a tablegen warning to an error. by Jakob Stoklund Olesen · 13 years ago
  69. 183c627 Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32 by Mon P Wang · 13 years ago
  70. 123cab9 Teach TableGen to automatically generate missing SubRegIndex instances. by Jakob Stoklund Olesen · 13 years ago
  71. 5d754bf Improve diagnostics for some parse errors. Not asserting when a user input by Jim Grosbach · 13 years ago
  72. 96883ec ParseFile() may throw, so extend the try/catch to handle that. by Jim Grosbach · 13 years ago
  73. 3a21c55 llvmc: Make it possible to provide an argument to (join). by Mikhail Glushenkov · 13 years ago
  74. 9f1569a The system suppression file should catch these, but since they *once again* are by Nick Lewycky · 13 years ago
  75. b9d5af0 Tidy up. Add missing newline to generated file. by Jim Grosbach · 13 years ago
  76. 206a10c Filter out pattterns from the FastISel emitter which it doesn't actually know how to handle. No significant functionality change at the moment, but it's necessary for some changes I'm planning. by Eli Friedman · 13 years ago
  77. bcffb1f Rename profile_rt.so to libprofile_rt.so under configure+make (it already was by Nick Lewycky · 13 years ago
  78. 4cdcb47 Fix a bug in tblgen that caused incorrect encodings on instructions that specified operands with "bit" instead of "bits<1>". by Owen Anderson · 13 years ago
  79. 4e699cf Add a TODO. by Mikhail Glushenkov · 13 years ago
  80. ddcdcc8 Remove unused STL header includes. by Jay Foad · 13 years ago
  81. 597fa65 Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should by Johnny Chen · 13 years ago
  82. c1fe100 Define Neon load/store intrinsics for Clang as macros instead of functions. by Bob Wilson · 13 years ago
  83. 69ba413 Don't allow per-register spill size and alignment. by Jakob Stoklund Olesen · 13 years ago
  84. 6bfba2e Prefer cheap registers for busy live ranges. by Jakob Stoklund Olesen · 13 years ago
  85. 721ef66 Invert the meaning of printAliasInstr's return value. It now returns by Eric Christopher · 13 years ago
  86. 5755715 Enhance the fixed-length disassembler to support the callbacks necessary for symbolic disassembly. by Owen Anderson · 13 years ago
  87. 202a7a1 Add a new bit that ImmLeaf's can opt into, which allows them to duck out of by Chris Lattner · 13 years ago
  88. 1518afd Implement major new fastisel functionality: the matcher can now handle immediates with by Chris Lattner · 13 years ago
  89. 9bfd5f3 introduce a new OpKind abstraction which wraps up operand flavors in a tidy little wrapper. by Chris Lattner · 13 years ago
  90. a90dbc1 change OperandsSignature to use SmallVector<char> instead of std::vector<string> by Chris Lattner · 13 years ago
  91. 4447d65 since the VT is fixed for a ImmLeaf, there is no reason to expose it to the matching code. by Chris Lattner · 13 years ago
  92. 7ed1391 now that predicates have a decent abstraction layer on them, introduce a new by Chris Lattner · 13 years ago
  93. 5437906 Rework our internal representation of node predicates to expose more by Chris Lattner · 13 years ago
  94. 461cd70 remove some debugging code I added. by Chris Lattner · 13 years ago
  95. 602fc06 1. merge fast-isel-shift-imm.ll into fast-isel-x86-64.ll by Chris Lattner · 13 years ago
  96. 4954e9f Initial work to improve documentation for Clang's diagnostics, from Matthieu Monrocq by Douglas Gregor · 13 years ago
  97. b6a6388 Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332 by Evan Cheng · 13 years ago
  98. 7a2bdde Fix a ton of comment typos found by codespell. Patch by by Chris Lattner · 13 years ago
  99. eef965f Add an option to not print the alias of an instruction. It defaults to "print by Bill Wendling · 13 years ago
  100. de16508 Thumb disassembler was erroneously rejecting "blx sp" instruction. by Johnny Chen · 13 years ago