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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / c038a7833565ecf92a699371d448135a097c9e2f / lib
  1. c038a78 Now that Reassociate's LinearizeExprTree can look through arbitrary expression by Duncan Sands · 12 years ago
  2. 4db738a Reapply r158337, this time properly protect Darwin/PPC host CPU use with __ppc__. by Hal Finkel · 12 years ago
  3. 3e61374 Satisfy C++ aliasing rules, per suggestion by Chandler. by Argyrios Kyrtzidis · 12 years ago
  4. 138c2b4 Revert r158337 "Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName()." by Jakob Stoklund Olesen · 12 years ago
  5. 793537d For llvm::sys::ThreadLocalImpl instead of malloc'ing the platform-specific by Argyrios Kyrtzidis · 12 years ago
  6. 0eb3a35 misched: When querying RegisterPressureTracker, always save current and max pressure. by Andrew Trick · 12 years ago
  7. 4487479 misched: regpressure getMaxPressureDelta, revert accidental checkin. by Andrew Trick · 12 years ago
  8. 7bb39d8 Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName(). by Hal Finkel · 12 years ago
  9. 5a53c6e Enable MFOCRF generation on the PPC A2 core. by Hal Finkel · 12 years ago
  10. bd5cafd Rename the PPC target feature gpul to mfocrf. by Hal Finkel · 12 years ago
  11. 9770be9 Add A2 to the list of PPC CPUs recognized by Linux host CPU-type detection. by Hal Finkel · 12 years ago
  12. 0a1852b Emit the two-operand form of the PPC mfcr instruction as mfocrf. by Hal Finkel · 12 years ago
  13. 2bd0acd Add local CPU detection for Linux PPC. by Hal Finkel · 12 years ago
  14. 622382f Add POWER6 and POWER7 CPU types to the PPC backend. by Hal Finkel · 12 years ago
  15. 6f36fa9 Write llvm-tblgen backends as functions instead of sub-classes. by Jakob Stoklund Olesen · 12 years ago
  16. ad5c880 Re-enable the CMN instruction. by Bill Wendling · 12 years ago
  17. 7a99b46 InstCombine: factor code better. by Benjamin Kramer · 12 years ago
  18. 66821d9 InstCombine: Turn (zext A) == (B & (1<<X)-1) into A == (trunc B), narrowing the compare. by Benjamin Kramer · 12 years ago
  19. 71ffcfe Enable ILP scheduling for all nodes by default on PPC. by Hal Finkel · 12 years ago
  20. 3c98ce2 Add AutoUpgrade support for the SSE4 ptest intrinsics. by Nadav Rotem · 12 years ago
  21. 01a90f4 Use critical anti-dep. breaking on all PPC targets, but also add other register classes. by Hal Finkel · 12 years ago
  22. cfd3ed9 Add intrinsics for immediate form of XOP vprot instructions. Use i128mem instead of f128mem for integer XOP instructions. by Craig Topper · 12 years ago
  23. 0a3e33b Improve ext/trunc patterns on PPC64. by Hal Finkel · 12 years ago
  24. 2a5dc43 Use XOP vpcom intrinsics in patterns instead of a target specific SDNode type. Remove the custom lowering code that selected the SDNode type. by Craig Topper · 12 years ago
  25. c29106b Replace XOP vpcom intrinsics with fewer intrinsics that take the immediate as an argument. by Craig Topper · 12 years ago
  26. 133fe75 Disabling a spurious deprecation warning about using PathV1 from within the PathV1 implementation file. by Aaron Ballman · 12 years ago
  27. 19472a6 Fixing a typo in the comments. by Aaron Ballman · 12 years ago
  28. f33a79c Allocate the contents of DwarfDebug's StringMaps in a single big BumpPtrAllocator. by Benjamin Kramer · 12 years ago
  29. af0d459 Silence a gcc-4.6 warning: GCC fails to understand that secondReg and cmpOp2 are by Duncan Sands · 12 years ago
  30. 8bf75ed Enable tail merging on PPC. by Hal Finkel · 12 years ago
  31. ba17293 Register pressure: added getPressureAfterInstr. by Andrew Trick · 12 years ago
  32. 8879480 Sketch a LiveRegMatrix analysis pass. by Jakob Stoklund Olesen · 12 years ago
  33. b9bfe48 Test commit by Jack Carter · 12 years ago
  34. fe17bdb Also compute MBB live-in lists in the new rewriter pass. by Jakob Stoklund Olesen · 12 years ago
  35. 77592fe Convert comments to proper Doxygen comments. by Dmitri Gribenko · 12 years ago
  36. 05ec712 Reintroduce VirtRegRewriter. by Jakob Stoklund Olesen · 12 years ago
  37. 0f68fbb canonicalize: -%a + 42 into 42 - %a by Nuno Lopes · 12 years ago
  38. 791e2e0 Start implementing pre-ra if-converter: using speculation and selects to eliminate branches. by Evan Cheng · 12 years ago
  39. eb81df7 TargetInstrInfo hooks implemented in codegen should be declared pure virtual. by Andrew Trick · 12 years ago
  40. 841f426 Reapply commit 158073 with a fix (the testcase was already committed). The by Duncan Sands · 12 years ago
  41. 16b16ac Remove the TODO statement in the PPC README re: CTR loops by Hal Finkel · 12 years ago
  42. 7255d2a Enable PPC CTR loop formation by default. by Hal Finkel · 12 years ago
  43. 7e56312 Mark the PPC CTRRC and CTRRC8 register classes as non-allocatable. by Hal Finkel · 12 years ago
  44. 45d53b8 Enable optimization for integer ABS on X86 if Subtarget has CMOV. by Manman Ren · 12 years ago
  45. 28dd960 Fix a crash in APInt::lshr when shiftAmt > BitWidth. by Chad Rosier · 12 years ago
  46. c36d033 Fix Target->Codegen dependence. by Andrew Trick · 12 years ago
  47. eb90adf BoundsChecking: add support for ConstantPointerNull. fixes a bunch of instrumentation failures in loops with reallocs by Nuno Lopes · 12 years ago
  48. 09fdc7b Disable the PPC CTR-Loops pass by default. by Hal Finkel · 12 years ago
  49. daa03ec Fix a bug in the new PPC CTR-Loops pass. by Hal Finkel · 12 years ago
  50. 99f823f Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form CTR-based loop branching code. by Hal Finkel · 12 years ago
  51. 69938a8 Revert commit 158073 while waiting for a fix. The issue is that reassociate by Duncan Sands · 12 years ago
  52. 9236362 X86: optimize generated code for integer ABS by Manman Ren · 12 years ago
  53. bdcae38 Do not optimize the used bits of the x86 vselect condition operand, when the condition operand is a vector of 1-bit predicates. by Nadav Rotem · 12 years ago
  54. 2f6622c Fix a bug in FoldSelectOpOp. Bitcast ops may change the number of vector elements, which may disagree with the select condition type. by Nadav Rotem · 12 years ago
  55. 397f4e3 Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency. by Andrew Trick · 12 years ago
  56. 68b1654 ARM getOperandLatency rewrite. by Andrew Trick · 12 years ago
  57. f377071 ARM getOperandLatency should return -1 for unknown, consistent with API by Andrew Trick · 12 years ago
  58. ed7a51e Fix ARM getInstrLatency logic to work with the current API. by Andrew Trick · 12 years ago
  59. e6fc9d4 PR13046: we can't replace usage of SUB with CMP in the lowering phase. by Manman Ren · 12 years ago
  60. c07f5bb Use a base register instead of an index register with the local dynamic model. by Rafael Espindola · 12 years ago
  61. 83569cb Move terminator machine verification to check MachineBasicBlock::instr_iterator instead of MBB::iterator by Pete Cooper · 12 years ago
  62. 87253c2 X86: replace SUB with CMP if possible by Manman Ren · 12 years ago
  63. 2afde77 Revert r157755. by Manman Ren · 12 years ago
  64. 1f9c3ec Properly verify liveness with bundled machine instructions. by Jakob Stoklund Olesen · 12 years ago
  65. 8e5271d Add accessors for all private members of DisasmContext. by Benjamin Kramer · 12 years ago
  66. 1525260 Move RegisterClassInfo.h. by Andrew Trick · 12 years ago
  67. afc2657 Move RegisterPressure.h. by Andrew Trick · 12 years ago
  68. 95a9d93 Round 2 of dead private variable removal. by Benjamin Kramer · 12 years ago
  69. a7542d5 Remove unused private fields found by clang's new -Wunused-private-field. by Benjamin Kramer · 12 years ago
  70. a97b180 Add support for dynamic stack realignment in the presence of dynamic allocas on by Chad Rosier · 12 years ago
  71. 8b421c8 Fix combine of uno && ord -> false so that the ordering of the fcmps doesn't by Chad Rosier · 12 years ago
  72. 461e7ea Remove dead debug option -disable-rematerialization. by Jakob Stoklund Olesen · 12 years ago
  73. b933586 Grab-bag of reassociate tweaks. Unify handling of dead instructions and by Duncan Sands · 12 years ago
  74. d14e4e1 Stop leaking RegScavengers from TailDuplication. by Benjamin Kramer · 12 years ago
  75. c8f2fcc Correct decoder for T1 conditional B encoding by Richard Barton · 12 years ago
  76. 3949b83 Mark several instructions SSE2 instead of SSE3 as they should be. by Craig Topper · 12 years ago
  77. 0e5a60b Move LiveUnionArray into LiveIntervalUnion.h by Jakob Stoklund Olesen · 12 years ago
  78. 2fd0923 Don't print register names in LiveIntervalUnion::print(). by Jakob Stoklund Olesen · 12 years ago
  79. 05b46f0 Suppress -Wunused-variable in -Asserts build by Matt Beaumont-Gay · 12 years ago
  80. b77ec7d Simplify LiveInterval::print(). by Jakob Stoklund Olesen · 12 years ago
  81. 34c6f98 Add experimental support for register unit liveness. by Jakob Stoklund Olesen · 12 years ago
  82. 4e53a40 Implement LiveRangeCalc::extendToUses() and createDeadDefs(). by Jakob Stoklund Olesen · 12 years ago
  83. d88d278 MachineInstr::eraseFromParent fix for removing bundled instrs. by Andrew Trick · 12 years ago
  84. b7e0289 misched: API for minimum vs. expected latency. by Andrew Trick · 12 years ago
  85. 5afba6f Add a new intrinsic: llvm.fmuladd. This intrinsic represents a multiply-add by Lang Hames · 12 years ago
  86. 09b5df8 Fix header file include order in NVPTX backend NV_CONTRIB by Yuan Lin · 12 years ago
  87. 1247376 LoopUnroll: always check for NULL LoopPassManager by Andrew Trick · 12 years ago
  88. 3e77af4 PPC32 uses R2 as the TLS register. Fix the copy and paste. by Roman Divacky · 12 years ago
  89. 1d98530 X86 itinerary properties. by Andrew Trick · 12 years ago
  90. f94f051 ARM itinerary properties. by Andrew Trick · 12 years ago
  91. fc99299 misched: Added MultiIssueItineraries. by Andrew Trick · 12 years ago
  92. 4eb4e5e sdsched: Use the right heuristics when -mcpu is not provided and we have no itinerary. by Andrew Trick · 12 years ago
  93. d327d3d misched: Allow disabling scoreboard hazard checking for subtargets with a by Andrew Trick · 12 years ago
  94. d05b461 whitespace by Andrew Trick · 12 years ago
  95. 76e9e83 misched: comments from code review. by Andrew Trick · 12 years ago
  96. afb32f7 Remove the last remat-related code from LiveIntervalAnalysis. by Jakob Stoklund Olesen · 12 years ago
  97. 3dfd59b Stop using LiveIntervals::isReMaterializable(). by Jakob Stoklund Olesen · 12 years ago
  98. e061053 Revert commit r157966 by Joel Jones · 12 years ago
  99. dd52bf2 This change handles a another case for generating the bic instruction by Joel Jones · 12 years ago
  100. 84423c8 Delete dead code. by Jakob Stoklund Olesen · 12 years ago