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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / dab3d29605a5c83db41b28176273ef55961120c1 / test
  1. dbd4fe2 - Register v16i16 as valid VR256 register class by Bruno Cardoso Lopes · 13 years ago
  2. 65b74e1 Add support for 256-bit versions of VPERMIL instruction. This is a new by Bruno Cardoso Lopes · 13 years ago
  3. c205a09 LSR, correct fix for rdar://9786536. Silly casting bug. by Andrew Trick · 13 years ago
  4. c2c988e LSR must sometimes sign-extend before generating double constants. by Andrew Trick · 13 years ago
  5. 37eb38d LSR crashes on an empty IVUsers list. by Andrew Trick · 13 years ago
  6. 4ec14b0 While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value. by Devang Patel · 13 years ago
  7. 73bfa4a Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef. by Eli Friedman · 13 years ago
  8. a4d0bd8 Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389. by Eli Friedman · 13 years ago
  9. 88d1bc8 Add parsing/encoding tests for ARM ORR instruction. by Jim Grosbach · 13 years ago
  10. a678514 Consolidate ARM NOP encoding test. by Jim Grosbach · 13 years ago
  11. c3635c2 ARM parsing and encoding tests for MVN by Jim Grosbach · 13 years ago
  12. ab40f4b ARM assembly parsing of MUL instruction. by Jim Grosbach · 13 years ago
  13. 0381c21 PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS. by Eli Friedman · 13 years ago
  14. e76a33b Add MCObjectFileInfo and sink the MCSections initialization code from by Evan Cheng · 13 years ago
  15. 86c9814 indvars: Added getInsertPointForUses to find a valid place to truncate the IV. by Andrew Trick · 13 years ago
  16. 03c45f6 New pointer rotate test. by Eric Christopher · 13 years ago
  17. 9e92152 indvars test case for r135558. by Andrew Trick · 13 years ago
  18. f22d957 indvars -disable-iv-rewrite fix: derived GEP IVs by Andrew Trick · 13 years ago
  19. db54826 Lower memory barriers to sync instructions. by Akira Hatanaka · 13 years ago
  20. 70955c2 Fix an obvious typo that's preventing x86 (32-bit) from using .literal16. by Evan Cheng · 13 years ago
  21. 3610604 PR10386: Don't try to split an edge from an indirectbr. by Eli Friedman · 13 years ago
  22. b29b4dd Tweak ARM assembly parsing and printing of MSR instruction. by Jim Grosbach · 13 years ago
  23. 80d01dd ARM assembly parsing of MRS instruction. by Jim Grosbach · 13 years ago
  24. ccfd931 ARM assembly parsing for MRC/MRC2/MRRC/MRRC2. by Jim Grosbach · 13 years ago
  25. cc7ecc7 Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or by Akira Hatanaka · 13 years ago
  26. 2317fe1 Move mr[r]c[2] ARM tests and tidy up a bit. by Jim Grosbach · 13 years ago
  27. 1a2be4d ARM testcases for MOVT. by Jim Grosbach · 13 years ago
  28. 5f16057 ARM assembly parsing for MOV (register). by Jim Grosbach · 13 years ago
  29. ffa3225 ARM assembly parsing for MOV (immediate). by Jim Grosbach · 13 years ago
  30. 0ec2aa2 Whitespace. by Jim Grosbach · 13 years ago
  31. 70564a9 Remove redundant instructions. by Akira Hatanaka · 13 years ago
  32. c8007ab Add intrinsics for the zext / sext instructions. by Richard Osborne · 13 years ago
  33. 829bef1 Add intrinsics for the testct, testwct instructions. by Richard Osborne · 13 years ago
  34. dee3dd9 Add intrinsics for the peek and endin instructions. by Richard Osborne · 13 years ago
  35. bb2518c Remove bogus test: for all possible inputs of %X, the 'sub nsw' is guaranteed by Nick Lewycky · 13 years ago
  36. 4396613 Introduce MCCodeGenInfo, which keeps information that can affect codegen by Evan Cheng · 13 years ago
  37. 497a397 by Devang Patel · 13 years ago
  38. 3a594f4 FileCheck-ize a couple tests. by Eli Friedman · 13 years ago
  39. 1360bc8 by Devang Patel · 13 years ago
  40. fc933c0 indvars: LinearFunctionTestReplace for non-canonical IVs. by Andrew Trick · 13 years ago
  41. a921164 Do not treat atomic.load.sub differently than other atomic binary intrinsics. by Akira Hatanaka · 13 years ago
  42. 0d7d0b5 Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from by Akira Hatanaka · 13 years ago
  43. fc47933 Fix a crash when building 177.mesa for armv6. by Jakob Stoklund Olesen · 13 years ago
  44. 3aaa010 Add AVX 128-bit sqrt versions by Bruno Cardoso Lopes · 13 years ago
  45. b8c129e Delete empty unused file. by Nick Lewycky · 13 years ago
  46. af37cb5 More minor adjustments. by Eric Christopher · 13 years ago
  47. 7105259 Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873. by Eli Friedman · 13 years ago
  48. 4201eca Add AVX 128-bit patterns for sint_to_fp by Bruno Cardoso Lopes · 13 years ago
  49. 465c7aa Finish propagating %asmtmp->%1 change. by Eric Christopher · 13 years ago
  50. 7305c55 fix rdar://9776316 - type remapping needed for inline asm blobs, by Chris Lattner · 13 years ago
  51. 5bc37dd Fix a couple of things: by Bruno Cardoso Lopes · 13 years ago
  52. 5232cc6 PR10370: Make sure we know how to relax push correctly on x86-64. by Eli Friedman · 13 years ago
  53. 72d6f34 A real testcase for r135286. by Chad Rosier · 13 years ago
  54. d03ed6b Update these tests, no longer outputting names for the variables. by Eric Christopher · 13 years ago
  55. 96a7db0 Add testcase for r135286. by Chad Rosier · 13 years ago
  56. 43967a9 Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler. by Owen Anderson · 13 years ago
  57. 33c16a2 ARM diagnostic when 's' suffix on mnemonic that can't set flags. by Jim Grosbach · 13 years ago
  58. 70d8fcf Add some testcases for ARM MLA/MLS instructions. by Jim Grosbach · 13 years ago
  59. c8ae39e ARM MCRR/MCRR2 immediate operand range checking. by Jim Grosbach · 13 years ago
  60. e540c74 ARM MCR/MCR2 assembly parsing operand constraints. by Jim Grosbach · 13 years ago
  61. 1134be2 Enable some tests we now handle correctly. by Jim Grosbach · 13 years ago
  62. 5427ede Check register class matching instead of width of type matching by Eric Christopher · 13 years ago
  63. 62f67f8 Add 256-bit load/store recognition and matching in several places. by Bruno Cardoso Lopes · 13 years ago
  64. 3b14a5c Update ARM Assembly of LDM/STM. by Jim Grosbach · 13 years ago
  65. 791feea ARM ISB assembly parsing tests. by Jim Grosbach · 13 years ago
  66. 9dec507 ARM ISB instruction assembly parsing. by Jim Grosbach · 13 years ago
  67. 2b88e8f Add a testcase for r135123. by Eric Christopher · 13 years ago
  68. 3ff2551 Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient. by Benjamin Kramer · 13 years ago
  69. 00a6665 ARM tests for EOR instruction parsing and encoding. by Jim Grosbach · 13 years ago
  70. 6a86fea Remove duplicate tests. by Jim Grosbach · 13 years ago
  71. e77494e ARM Assembler support for DSB instruction. by Jim Grosbach · 13 years ago
  72. 032434d ARM Assembler support for DMB instruction. by Jim Grosbach · 13 years ago
  73. 6f9f884 ARM Assembler support for DBG instruction. by Jim Grosbach · 13 years ago
  74. 53c9588 We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases. by Bruno Cardoso Lopes · 13 years ago
  75. 14ab1c3 ARM parsing and encoding tests for CMN/CMP. by Jim Grosbach · 13 years ago
  76. d986bc6 Shuffle ARM assembly tests a bit. by Jim Grosbach · 13 years ago
  77. 83ab070 Range checking for CDP[2] immediates. by Jim Grosbach · 13 years ago
  78. 466b022 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more by Bruno Cardoso Lopes · 13 years ago
  79. 2a01946 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. by Eli Friedman · 13 years ago
  80. 9bb098a Fix predicates for Thumb co-processor instructions. by Jim Grosbach · 13 years ago
  81. f333d47 Testcases for ARM assembly BX/BXJ instructions. by Jim Grosbach · 13 years ago
  82. 37023b0 Testcases for ARM assembly BLX/BL instructions. by Jim Grosbach · 13 years ago
  83. fff76ee Range checking for 16-bit immediates in ARM assembly. by Jim Grosbach · 13 years ago
  84. 3fd6e75 Change test case, one that actually failed before my commit. by Evan Cheng · 13 years ago
  85. 21101d6 Add tests for ARM parsing of 'BKPT' instruction. by Jim Grosbach · 13 years ago
  86. 76cbe02 Fix copy-pasto. by Jim Grosbach · 13 years ago
  87. e52240c Add tests for ARM parsing of 'BIC' instruction. by Jim Grosbach · 13 years ago
  88. 7ed6d22 Add some FIXMEs. by Jim Grosbach · 13 years ago
  89. 93a635c It's not safe to fold (fptrunc (sqrt (fpext x))) to (sqrtf x) if there is another use of sqrt. rdar://9763193 by Evan Cheng · 13 years ago
  90. 59642c2 Add tests for ARM parsing of 'AND' instruction. by Jim Grosbach · 13 years ago
  91. 1990672 Improve ARM assembly parsing diagnostics a bit. by Jim Grosbach · 13 years ago
  92. da9f278 Add tests for ARM parsing of 'ADD' instruction by Jim Grosbach · 13 years ago
  93. 37ee464 Destination register operand is optional for ADC and SBC ARM. by Jim Grosbach · 13 years ago
  94. e8606dc Flesh out ARM Parser support for shifted-register operands. by Jim Grosbach · 13 years ago
  95. 61905f0 AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd by Bruno Cardoso Lopes · 13 years ago
  96. e721f5c Improve codegen for select's: if (x != 0) x = 1 if (x == 1) x = 1 by Evan Cheng · 13 years ago
  97. dc89561 Add check for predicate w/o S bit. by Jim Grosbach · 13 years ago
  98. 92bf81d Improve test cases from r134746. by Jim Grosbach · 13 years ago
  99. b9484ca Comment correction. by Andrew Trick · 13 years ago
  100. 3f00e31 Fix recognition of ARM 'adcs' mnemonic. by Jim Grosbach · 13 years ago