- dc66eda Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee by Bob Wilson · 15 years ago
- b05b801 Convert test to FileCheck. by Bob Wilson · 15 years ago
- e269ead Convert a test to use FileCheck. by Bob Wilson · 15 years ago
- bde87c4 Test expects SSE, give him SSE. by Benjamin Kramer · 15 years ago
- 1d81e0e Restore arch on these test, they fail on arm. by Benjamin Kramer · 15 years ago
- a01818c Mark as XFAIL on darwin 8. PR 7886. by Dale Johannesen · 15 years ago
- 703af3a Temporarily disable tail calls on ARM to work around some linker problems. by Bob Wilson · 15 years ago
- 1b40510 Revert 110491. While not wrong, it was based on a by Dale Johannesen · 15 years ago
- 642eb02 - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. by Bruno Cardoso Lopes · 15 years ago
- 8c05a85 Begin to support some vector operations for AVX 256-bit intructions. The long by Bruno Cardoso Lopes · 15 years ago
- fd56f3c This is x86 only test. by Devang Patel · 15 years ago
- 4fd393c Add testcases for all AVX 256-bit intrinsics added in the last couple days by Bruno Cardoso Lopes · 15 years ago
- 1d72aee Reapply r109881 using a more strict command line for llc. by Bruno Cardoso Lopes · 15 years ago
- b5aa11f fix silly typo by Jim Grosbach · 15 years ago
- 7166e62 Add a target triple, as the runtime library invocation varies a bit by by Jim Grosbach · 15 years ago
- e1f0859 Fix test and re-enable it. by Evan Cheng · 15 years ago
- 3cc5d13 Temporarily disable some failing tests, until they can be properly investigated. by Dan Gohman · 15 years ago
- fcba5e6 cortex m4 has floating point support, but only single precision. by Jim Grosbach · 15 years ago
- f63fed1 Temporarily disable some failing tests, until they can be properly investigated. by Dan Gohman · 15 years ago
- de2b151 Consider this code snippet: by Bill Wendling · 15 years ago
- 7b4d311 Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors. by Evan Cheng · 15 years ago
- d6b4632 Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) by Evan Cheng · 15 years ago
- c7569ed Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit by Evan Cheng · 15 years ago
- 11db068 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the by Evan Cheng · 15 years ago
- d771041 Update test to match output of optimize compares for ARM. by Bill Wendling · 15 years ago
- bb47d3b The optimize comparisons pass removes the "cmp" instruction this is checking for. by Bill Wendling · 15 years ago
- ac09680 Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object. by Evan Cheng · 15 years ago
- 4bd828f Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP by Daniel Dunbar · 15 years ago
- dc08309 Fix test for more architectures. Patch by Tobias Grosser. by Jakob Stoklund Olesen · 15 years ago
- 0e28b15 Fix failing testcase. by Tobias Grosser · 15 years ago
- 2936807 Handle TAG_constant for integers. by Devang Patel · 15 years ago
- c9aed19 Fix ARM hasFP() semantics. It should return true whenever FP register is by Evan Cheng · 15 years ago
- 99534bb Have SPU handle halfvec stores aligned by 8 bytes. by Kalle Raiskila · 15 years ago
- 7f6eb63 Use sdmem and sse_load_f64 (etc.) for the vector by Dale Johannesen · 15 years ago
- 55e9587 Fix eabi calling convention when a 64 bit value shadows r3. by Rafael Espindola · 15 years ago
- e74a088 Add an option to always emit realignment code for a particular module. by Eric Christopher · 15 years ago
- baefea4 Move x86 specific tests into test/CodeGen/X86. by Devang Patel · 15 years ago
- a34c885 Move x86-specific tests out of test/Transforms/LoopStrengthReduce and by Dan Gohman · 15 years ago
- feaac8f tests: CodeGen/X86/GC tests require X86. by Daniel Dunbar · 15 years ago
- af33b7b The lower invoke pass needs to have unreachable code elimination run after it by Bill Wendling · 15 years ago
- 7752442 PR7814: Truncates cannot be ignored for signed comparisons. by Eli Friedman · 15 years ago
- 547b6ed Testcase for r110248. by Bill Wendling · 15 years ago
- b884666 call-imm.ll test case regex fix. Patch by Dimitry Andric! by Stuart Hastings · 15 years ago
- bc2697c Make SPU backend handle insertelement and store for "half vectors" by Kalle Raiskila · 15 years ago
- 67b453b Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABA by Bob Wilson · 15 years ago
- 0055f97 OK, that's it. This test is going away now. But don't worry, I am taking it to a by Jakob Stoklund Olesen · 15 years ago
- e1c9159 More SPU v2f32 stuff added: insertelement and shuffle. by Kalle Raiskila · 15 years ago
- c9fda99 Add preliminary v2f32 support for SPU. Like with v2i32, we just by Kalle Raiskila · 15 years ago
- 82fe467 Add preliminary v2i32 support for SPU backend. As there are no by Kalle Raiskila · 15 years ago
- e383701 PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR. by Eli Friedman · 15 years ago
- 348e026 PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually by Eli Friedman · 15 years ago
- 6945ef3 Revert new AVX intrinsic tests. They are breaking buildbots and Bruno is by Bob Wilson · 15 years ago
- 74273b8 A *bunch* of tests for AVX intrinsics by Bruno Cardoso Lopes · 15 years ago
- ad78a88 Fix for bug reported by Evzen Muller on llvm-commits: make sure to correctly by Eli Friedman · 15 years ago
- 6ccfc50 Many Thumb2 instructions can reference the full ARM register set (i.e., by Jim Grosbach · 15 years ago
- f630c71 Implement vector constants which are splat of by Dale Johannesen · 15 years ago
- 5140921 Implement a vectorized algorithm for <16 x i8> << <16 x i8> by Nate Begeman · 15 years ago
- bdcb5af ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller types coming in future patches. by Nate Begeman · 15 years ago
- e0efc21 Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself by Nate Begeman · 15 years ago
- b5a0ef9 Currently EH lowering code expects typeinfo to be global only. by Anton Korobeynikov · 15 years ago
- 3144687 - Allow target to specify when is register pressure "too high". In most cases, by Evan Cheng · 15 years ago
- cd20c6f Use the proper type for shift counts. This fixes a bootstrap error. by Dan Gohman · 15 years ago
- a4f4d69 DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits by Dan Gohman · 15 years ago
- 9a9d275 Custom lower the memory barrier instructions and add support by Eric Christopher · 15 years ago
- 4a863e2 More register pressure aware scheduling work. by Evan Cheng · 15 years ago
- ab69588 Baby steps towards ARM fast-isel. by Eric Christopher · 15 years ago
- bc56501 Fix calling convention on ARM if vfp2+ is enabled. by Rafael Espindola · 15 years ago
- fc3678a Fix SCEV denormalization of expressions where the exit value from by Dan Gohman · 15 years ago
- f27ca42 update tests for smarter BIC usage by Jim Grosbach · 15 years ago
- 6bf8eee The same problem was being tracked in PR7652. by Duncan Sands · 15 years ago
- 4677379 Fix PR7174, a couple o Mips fixes: by Bruno Cardoso Lopes · 15 years ago
- 29e9daa Fix Mips PR7473. Patch by stetorvs@gmail.com by Bruno Cardoso Lopes · 15 years ago
- c6e59b7 After a custom inserter, in a block which has constant instructions, by Dan Gohman · 15 years ago
- 54026c0 Remove r108639 now that it is handled by InstCombine instead. by Owen Anderson · 15 years ago
- fd73c91 Add a testcase for r108639. by Owen Anderson · 15 years ago
- 5423856 Add combiner patterns to more effectively utilize the BFI (bitfield insert) by Jim Grosbach · 15 years ago
- 469bbdb Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction by Jim Grosbach · 15 years ago
- dc86704 Consider this function: by Bill Wendling · 15 years ago
- 468a2a4 Remove the X86::FP_REG_KILL pseudo-instruction and the X86FloatingPointRegKill by Jakob Stoklund Olesen · 15 years ago
- 3df1d5c Feed the right output into FileCheck. by Benjamin Kramer · 15 years ago
- 04c528a Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway. by Jakob Stoklund Olesen · 15 years ago
- 18c479c Add forgotten test case. by Jakob Stoklund Olesen · 15 years ago
- e667e01 Use the source-order scheduler instead of the "fast" scheduler at -O0, by Dan Gohman · 15 years ago
- bdc09d9 The SelectionDAGBuilder's handling of debug info, on rare by Dale Johannesen · 15 years ago
- a60f0e7 Revert. This isn't the correct way to go. by Bill Wendling · 15 years ago
- e9bf7e6 Handle code gen for the unreachable instruction if it's the only instruction in by Bill Wendling · 15 years ago
- 60108e9 Split -enable-finite-only-fp-math to two options: by Evan Cheng · 15 years ago
- 6a624a6 fix the definitions of ConstTextCoalSection/ConstDataCoalSection by Chris Lattner · 15 years ago
- 07538ad Fix crash reported in PR7653. by Devang Patel · 15 years ago
- c88c1a4 Watch out for a constant offset cancelling out a base register, forming by Dan Gohman · 15 years ago
- c7c601e Make it a .ll test case. by Devang Patel · 15 years ago
- 502e0aa Improve 64-subtraction of immediates when parts of the immediate can fit by Jim Grosbach · 15 years ago
- 2dd50e6 Delete fast-isel's trivial load optimization; it breaks debugging because by Dan Gohman · 15 years ago
- 7a52e65 Fix test to appease the buildbots. by Bob Wilson · 15 years ago
- dedd974 Fix for PR7193 was overly conservative. The only case where sibcall callee by Evan Cheng · 15 years ago
- 7e3f0d2 Add support for NEON VMVN immediate instructions. by Bob Wilson · 15 years ago
- 44a44ad Re-enable the test with fix. by Evan Cheng · 15 years ago
- f4e5947 temporarily disable to test to fix buildbots. by Chris Lattner · 15 years ago
- db89809 Teach ProcessImplicitDefs to transform more COPY instructions into IMPLICIT_DEF (and subsequently eliminate them). This allows machine LICM to hoist IMPLICIT_DEF's. PR7620. by Evan Cheng · 15 years ago
- 9e82bf1 Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes. by Bob Wilson · 15 years ago