Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 1 | /************************************************************************** |
| 2 | |
| 3 | Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and |
| 4 | VA Linux Systems Inc., Fremont, California. |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 5 | Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. |
| 6 | |
| 7 | The Weather Channel (TM) funded Tungsten Graphics to develop the |
| 8 | initial release of the Radeon 8500 driver under the XFree86 license. |
| 9 | This notice must be preserved. |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 10 | |
| 11 | All Rights Reserved. |
| 12 | |
| 13 | Permission is hereby granted, free of charge, to any person obtaining |
| 14 | a copy of this software and associated documentation files (the |
| 15 | "Software"), to deal in the Software without restriction, including |
| 16 | without limitation the rights to use, copy, modify, merge, publish, |
| 17 | distribute, sublicense, and/or sell copies of the Software, and to |
| 18 | permit persons to whom the Software is furnished to do so, subject to |
| 19 | the following conditions: |
| 20 | |
| 21 | The above copyright notice and this permission notice (including the |
| 22 | next paragraph) shall be included in all copies or substantial |
| 23 | portions of the Software. |
| 24 | |
| 25 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 26 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 27 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 28 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| 29 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| 30 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| 31 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 32 | |
| 33 | **************************************************************************/ |
| 34 | |
| 35 | /* |
| 36 | * Authors: |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 37 | * Gareth Hughes <gareth@valinux.com> |
| 38 | * Keith Whitwell <keith@tungstengraphics.com> |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 39 | * Kevin E. Martin <martin@valinux.com> |
| 40 | * Nicolai Haehnle <prefect_@gmx.net> |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 41 | */ |
| 42 | |
| 43 | #ifndef __RADEON_CONTEXT_H__ |
| 44 | #define __RADEON_CONTEXT_H__ |
| 45 | |
Eric Anholt | 8a1df96 | 2005-05-31 04:04:24 +0000 | [diff] [blame] | 46 | #include "tnl/t_vertex.h" |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 47 | #include "dri_util.h" |
Jon Smirl | 6ddfdff | 2004-03-12 20:03:54 +0000 | [diff] [blame] | 48 | #include "drm.h" |
| 49 | #include "radeon_drm.h" |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 50 | #include "texmem.h" |
| 51 | |
| 52 | #include "macros.h" |
| 53 | #include "mtypes.h" |
| 54 | #include "colormac.h" |
| 55 | |
| 56 | struct radeon_context; |
| 57 | typedef struct radeon_context radeonContextRec; |
| 58 | typedef struct radeon_context *radeonContextPtr; |
| 59 | |
Roland Scheidegger | 08e62a1 | 2006-03-28 17:22:57 +0000 | [diff] [blame] | 60 | /* This union is used to avoid warnings/miscompilation |
| 61 | with float to uint32_t casts due to strict-aliasing */ |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 62 | typedef union { |
| 63 | GLfloat f; |
| 64 | uint32_t ui32; |
| 65 | } float_ui32_type; |
Roland Scheidegger | 08e62a1 | 2006-03-28 17:22:57 +0000 | [diff] [blame] | 66 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 67 | #include "radeon_lock.h" |
| 68 | #include "radeon_screen.h" |
| 69 | #include "mm.h" |
| 70 | |
Keith Whitwell | 57c9814 | 2003-11-24 15:21:14 +0000 | [diff] [blame] | 71 | #include "math/m_vector.h" |
| 72 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 73 | #define TEX_0 0x1 |
| 74 | #define TEX_1 0x2 |
| 75 | #define TEX_2 0x4 |
| 76 | #define TEX_ALL 0x7 |
| 77 | |
| 78 | /* Rasterizing fallbacks */ |
| 79 | /* See correponding strings in r200_swtcl.c */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 80 | #define RADEON_FALLBACK_TEXTURE 0x0001 |
| 81 | #define RADEON_FALLBACK_DRAW_BUFFER 0x0002 |
| 82 | #define RADEON_FALLBACK_STENCIL 0x0004 |
| 83 | #define RADEON_FALLBACK_RENDER_MODE 0x0008 |
| 84 | #define RADEON_FALLBACK_BLEND_EQ 0x0010 |
| 85 | #define RADEON_FALLBACK_BLEND_FUNC 0x0020 |
| 86 | #define RADEON_FALLBACK_DISABLE 0x0040 |
| 87 | #define RADEON_FALLBACK_BORDER_MODE 0x0080 |
| 88 | |
| 89 | /* The blit width for texture uploads |
| 90 | */ |
| 91 | #define BLIT_WIDTH_BYTES 1024 |
| 92 | |
| 93 | /* Use the templated vertex format: |
| 94 | */ |
| 95 | #define COLOR_IS_RGBA |
| 96 | #define TAG(x) radeon##x |
| 97 | #include "tnl_dd/t_dd_vertex.h" |
| 98 | #undef TAG |
| 99 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 100 | typedef void (*radeon_tri_func) (radeonContextPtr, |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 101 | radeonVertex *, |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 102 | radeonVertex *, radeonVertex *); |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 103 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 104 | typedef void (*radeon_line_func) (radeonContextPtr, |
| 105 | radeonVertex *, radeonVertex *); |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 106 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 107 | typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *); |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 108 | |
| 109 | struct radeon_colorbuffer_state { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 110 | GLuint clear; |
| 111 | int roundEnable; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 112 | }; |
| 113 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 114 | struct radeon_depthbuffer_state { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 115 | GLuint clear; |
| 116 | GLfloat scale; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 117 | }; |
| 118 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 119 | struct radeon_scissor_state { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 120 | drm_clip_rect_t rect; |
| 121 | GLboolean enabled; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 122 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 123 | GLuint numClipRects; /* Cliprects active */ |
| 124 | GLuint numAllocedClipRects; /* Cliprects available */ |
| 125 | drm_clip_rect_t *pClipRects; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 126 | }; |
| 127 | |
| 128 | struct radeon_stencilbuffer_state { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 129 | GLboolean hwBuffer; |
| 130 | GLuint clear; /* rb3d_stencilrefmask value */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | struct radeon_stipple_state { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 134 | GLuint mask[32]; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 135 | }; |
| 136 | |
Roland Scheidegger | 30daa75 | 2005-10-13 14:30:20 +0000 | [diff] [blame] | 137 | /* used for both tcl_vtx and vc_frmt tex bits (they are identical) */ |
| 138 | #define RADEON_ST_BIT(unit) \ |
| 139 | (unit == 0 ? RADEON_CP_VC_FRMT_ST0 : (RADEON_CP_VC_FRMT_ST1 >> 2) << (2 * unit)) |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 140 | |
Roland Scheidegger | 30daa75 | 2005-10-13 14:30:20 +0000 | [diff] [blame] | 141 | #define RADEON_Q_BIT(unit) \ |
| 142 | (unit == 0 ? RADEON_CP_VC_FRMT_Q0 : (RADEON_CP_VC_FRMT_Q1 >> 2) << (2 * unit)) |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 143 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 144 | typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr; |
| 145 | |
| 146 | /* Texture object in locally shared texture space. |
| 147 | */ |
| 148 | struct radeon_tex_obj { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 149 | driTextureObject base; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 150 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 151 | GLuint bufAddr; /* Offset to start of locally |
| 152 | shared texture block */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 153 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 154 | GLuint dirty_state; /* Flags (1 per texunit) for |
| 155 | whether or not this texobj |
| 156 | has dirty hardware state |
| 157 | (pp_*) that needs to be |
| 158 | brought into the |
| 159 | texunit. */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 160 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 161 | drm_radeon_tex_image_t image[6][RADEON_MAX_TEXTURE_LEVELS]; |
| 162 | /* Six, for the cube faces */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 163 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 164 | GLuint pp_txfilter; /* hardware register values */ |
| 165 | GLuint pp_txformat; |
| 166 | GLuint pp_txoffset; /* Image location in texmem. |
| 167 | All cube faces follow. */ |
| 168 | GLuint pp_txsize; /* npot only */ |
| 169 | GLuint pp_txpitch; /* npot only */ |
| 170 | GLuint pp_border_color; |
| 171 | GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 172 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 173 | GLboolean border_fallback; |
Roland Scheidegger | 4837ea3 | 2005-02-10 22:36:06 +0000 | [diff] [blame] | 174 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 175 | GLuint tile_bits; /* hw texture tile bits used on this texture */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 176 | }; |
| 177 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 178 | struct radeon_texture_env_state { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 179 | radeonTexObjPtr texobj; |
| 180 | GLenum format; |
| 181 | GLenum envMode; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 182 | }; |
| 183 | |
| 184 | struct radeon_texture_state { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 185 | struct radeon_texture_env_state unit[RADEON_MAX_TEXTURE_UNITS]; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 186 | }; |
| 187 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 188 | struct radeon_state_atom { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 189 | struct radeon_state_atom *next, *prev; |
| 190 | const char *name; /* for debug */ |
| 191 | int cmd_size; /* size in bytes */ |
| 192 | GLuint is_tcl; |
| 193 | int *cmd; /* one or more cmd's */ |
| 194 | int *lastcmd; /* one or more cmd's */ |
| 195 | GLboolean dirty; /* dirty-mark in emit_state_list */ |
| 196 | GLboolean(*check) (GLcontext *); /* is this state active? */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 197 | }; |
Roland Scheidegger | 4837ea3 | 2005-02-10 22:36:06 +0000 | [diff] [blame] | 198 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 199 | /* Trying to keep these relatively short as the variables are becoming |
| 200 | * extravagently long. Drop the driver name prefix off the front of |
| 201 | * everything - I think we know which driver we're in by now, and keep the |
| 202 | * prefix to 3 letters unless absolutely impossible. |
| 203 | */ |
| 204 | |
| 205 | #define CTX_CMD_0 0 |
| 206 | #define CTX_PP_MISC 1 |
| 207 | #define CTX_PP_FOG_COLOR 2 |
| 208 | #define CTX_RE_SOLID_COLOR 3 |
| 209 | #define CTX_RB3D_BLENDCNTL 4 |
| 210 | #define CTX_RB3D_DEPTHOFFSET 5 |
| 211 | #define CTX_RB3D_DEPTHPITCH 6 |
| 212 | #define CTX_RB3D_ZSTENCILCNTL 7 |
| 213 | #define CTX_CMD_1 8 |
| 214 | #define CTX_PP_CNTL 9 |
| 215 | #define CTX_RB3D_CNTL 10 |
| 216 | #define CTX_RB3D_COLOROFFSET 11 |
| 217 | #define CTX_CMD_2 12 |
| 218 | #define CTX_RB3D_COLORPITCH 13 |
| 219 | #define CTX_STATE_SIZE 14 |
| 220 | |
| 221 | #define SET_CMD_0 0 |
| 222 | #define SET_SE_CNTL 1 |
| 223 | #define SET_SE_COORDFMT 2 |
| 224 | #define SET_CMD_1 3 |
| 225 | #define SET_SE_CNTL_STATUS 4 |
| 226 | #define SET_STATE_SIZE 5 |
| 227 | |
| 228 | #define LIN_CMD_0 0 |
| 229 | #define LIN_RE_LINE_PATTERN 1 |
| 230 | #define LIN_RE_LINE_STATE 2 |
| 231 | #define LIN_CMD_1 3 |
| 232 | #define LIN_SE_LINE_WIDTH 4 |
| 233 | #define LIN_STATE_SIZE 5 |
| 234 | |
| 235 | #define MSK_CMD_0 0 |
| 236 | #define MSK_RB3D_STENCILREFMASK 1 |
| 237 | #define MSK_RB3D_ROPCNTL 2 |
| 238 | #define MSK_RB3D_PLANEMASK 3 |
| 239 | #define MSK_STATE_SIZE 4 |
| 240 | |
| 241 | #define VPT_CMD_0 0 |
| 242 | #define VPT_SE_VPORT_XSCALE 1 |
| 243 | #define VPT_SE_VPORT_XOFFSET 2 |
| 244 | #define VPT_SE_VPORT_YSCALE 3 |
| 245 | #define VPT_SE_VPORT_YOFFSET 4 |
| 246 | #define VPT_SE_VPORT_ZSCALE 5 |
| 247 | #define VPT_SE_VPORT_ZOFFSET 6 |
| 248 | #define VPT_STATE_SIZE 7 |
| 249 | |
| 250 | #define MSC_CMD_0 0 |
| 251 | #define MSC_RE_MISC 1 |
| 252 | #define MSC_STATE_SIZE 2 |
| 253 | |
| 254 | #define TEX_CMD_0 0 |
| 255 | #define TEX_PP_TXFILTER 1 |
| 256 | #define TEX_PP_TXFORMAT 2 |
| 257 | #define TEX_PP_TXOFFSET 3 |
| 258 | #define TEX_PP_TXCBLEND 4 |
| 259 | #define TEX_PP_TXABLEND 5 |
| 260 | #define TEX_PP_TFACTOR 6 |
| 261 | #define TEX_CMD_1 7 |
| 262 | #define TEX_PP_BORDER_COLOR 8 |
| 263 | #define TEX_STATE_SIZE 9 |
| 264 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 265 | #define TXR_CMD_0 0 /* rectangle textures */ |
| 266 | #define TXR_PP_TEX_SIZE 1 /* 0x1d04, 0x1d0c for NPOT! */ |
| 267 | #define TXR_PP_TEX_PITCH 2 /* 0x1d08, 0x1d10 for NPOT! */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 268 | #define TXR_STATE_SIZE 3 |
| 269 | |
Roland Scheidegger | 247f3b3 | 2005-10-15 23:45:53 +0000 | [diff] [blame] | 270 | #define CUBE_CMD_0 0 |
| 271 | #define CUBE_PP_CUBIC_FACES 1 |
| 272 | #define CUBE_CMD_1 2 |
| 273 | #define CUBE_PP_CUBIC_OFFSET_0 3 |
| 274 | #define CUBE_PP_CUBIC_OFFSET_1 4 |
| 275 | #define CUBE_PP_CUBIC_OFFSET_2 5 |
| 276 | #define CUBE_PP_CUBIC_OFFSET_3 6 |
| 277 | #define CUBE_PP_CUBIC_OFFSET_4 7 |
| 278 | #define CUBE_STATE_SIZE 8 |
| 279 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 280 | #define ZBS_CMD_0 0 |
| 281 | #define ZBS_SE_ZBIAS_FACTOR 1 |
| 282 | #define ZBS_SE_ZBIAS_CONSTANT 2 |
| 283 | #define ZBS_STATE_SIZE 3 |
| 284 | |
| 285 | #define TCL_CMD_0 0 |
| 286 | #define TCL_OUTPUT_VTXFMT 1 |
| 287 | #define TCL_OUTPUT_VTXSEL 2 |
| 288 | #define TCL_MATRIX_SELECT_0 3 |
| 289 | #define TCL_MATRIX_SELECT_1 4 |
| 290 | #define TCL_UCP_VERT_BLEND_CTL 5 |
| 291 | #define TCL_TEXTURE_PROC_CTL 6 |
| 292 | #define TCL_LIGHT_MODEL_CTL 7 |
| 293 | #define TCL_PER_LIGHT_CTL_0 8 |
| 294 | #define TCL_PER_LIGHT_CTL_1 9 |
| 295 | #define TCL_PER_LIGHT_CTL_2 10 |
| 296 | #define TCL_PER_LIGHT_CTL_3 11 |
| 297 | #define TCL_STATE_SIZE 12 |
| 298 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 299 | #define MTL_CMD_0 0 |
| 300 | #define MTL_EMMISSIVE_RED 1 |
| 301 | #define MTL_EMMISSIVE_GREEN 2 |
| 302 | #define MTL_EMMISSIVE_BLUE 3 |
| 303 | #define MTL_EMMISSIVE_ALPHA 4 |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 304 | #define MTL_AMBIENT_RED 5 |
| 305 | #define MTL_AMBIENT_GREEN 6 |
| 306 | #define MTL_AMBIENT_BLUE 7 |
| 307 | #define MTL_AMBIENT_ALPHA 8 |
| 308 | #define MTL_DIFFUSE_RED 9 |
| 309 | #define MTL_DIFFUSE_GREEN 10 |
| 310 | #define MTL_DIFFUSE_BLUE 11 |
| 311 | #define MTL_DIFFUSE_ALPHA 12 |
| 312 | #define MTL_SPECULAR_RED 13 |
| 313 | #define MTL_SPECULAR_GREEN 14 |
| 314 | #define MTL_SPECULAR_BLUE 15 |
| 315 | #define MTL_SPECULAR_ALPHA 16 |
| 316 | #define MTL_SHININESS 17 |
| 317 | #define MTL_STATE_SIZE 18 |
| 318 | |
| 319 | #define VTX_CMD_0 0 |
| 320 | #define VTX_SE_COORD_FMT 1 |
| 321 | #define VTX_STATE_SIZE 2 |
| 322 | |
| 323 | #define MAT_CMD_0 0 |
| 324 | #define MAT_ELT_0 1 |
| 325 | #define MAT_STATE_SIZE 17 |
| 326 | |
| 327 | #define GRD_CMD_0 0 |
| 328 | #define GRD_VERT_GUARD_CLIP_ADJ 1 |
| 329 | #define GRD_VERT_GUARD_DISCARD_ADJ 2 |
| 330 | #define GRD_HORZ_GUARD_CLIP_ADJ 3 |
| 331 | #define GRD_HORZ_GUARD_DISCARD_ADJ 4 |
| 332 | #define GRD_STATE_SIZE 5 |
| 333 | |
| 334 | /* position changes frequently when lighting in modelpos - separate |
| 335 | * out to new state item? |
| 336 | */ |
| 337 | #define LIT_CMD_0 0 |
| 338 | #define LIT_AMBIENT_RED 1 |
| 339 | #define LIT_AMBIENT_GREEN 2 |
| 340 | #define LIT_AMBIENT_BLUE 3 |
| 341 | #define LIT_AMBIENT_ALPHA 4 |
| 342 | #define LIT_DIFFUSE_RED 5 |
| 343 | #define LIT_DIFFUSE_GREEN 6 |
| 344 | #define LIT_DIFFUSE_BLUE 7 |
| 345 | #define LIT_DIFFUSE_ALPHA 8 |
| 346 | #define LIT_SPECULAR_RED 9 |
| 347 | #define LIT_SPECULAR_GREEN 10 |
| 348 | #define LIT_SPECULAR_BLUE 11 |
| 349 | #define LIT_SPECULAR_ALPHA 12 |
| 350 | #define LIT_POSITION_X 13 |
| 351 | #define LIT_POSITION_Y 14 |
| 352 | #define LIT_POSITION_Z 15 |
| 353 | #define LIT_POSITION_W 16 |
| 354 | #define LIT_DIRECTION_X 17 |
| 355 | #define LIT_DIRECTION_Y 18 |
| 356 | #define LIT_DIRECTION_Z 19 |
| 357 | #define LIT_DIRECTION_W 20 |
Michel Dänzer | 5d00e13 | 2004-01-23 03:19:47 +0000 | [diff] [blame] | 358 | #define LIT_ATTEN_QUADRATIC 21 |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 359 | #define LIT_ATTEN_LINEAR 22 |
Michel Dänzer | 5d00e13 | 2004-01-23 03:19:47 +0000 | [diff] [blame] | 360 | #define LIT_ATTEN_CONST 23 |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 361 | #define LIT_ATTEN_XXX 24 |
| 362 | #define LIT_CMD_1 25 |
| 363 | #define LIT_SPOT_DCD 26 |
| 364 | #define LIT_SPOT_EXPONENT 27 |
| 365 | #define LIT_SPOT_CUTOFF 28 |
| 366 | #define LIT_SPECULAR_THRESH 29 |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 367 | #define LIT_RANGE_CUTOFF 30 /* ? */ |
Michel Dänzer | 5d00e13 | 2004-01-23 03:19:47 +0000 | [diff] [blame] | 368 | #define LIT_ATTEN_CONST_INV 31 |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 369 | #define LIT_STATE_SIZE 32 |
| 370 | |
| 371 | /* Fog |
| 372 | */ |
| 373 | #define FOG_CMD_0 0 |
| 374 | #define FOG_R 1 |
| 375 | #define FOG_C 2 |
| 376 | #define FOG_D 3 |
| 377 | #define FOG_PAD 4 |
| 378 | #define FOG_STATE_SIZE 5 |
| 379 | |
| 380 | /* UCP |
| 381 | */ |
| 382 | #define UCP_CMD_0 0 |
| 383 | #define UCP_X 1 |
| 384 | #define UCP_Y 2 |
| 385 | #define UCP_Z 3 |
| 386 | #define UCP_W 4 |
| 387 | #define UCP_STATE_SIZE 5 |
| 388 | |
| 389 | /* GLT - Global ambient |
| 390 | */ |
| 391 | #define GLT_CMD_0 0 |
| 392 | #define GLT_RED 1 |
| 393 | #define GLT_GREEN 2 |
| 394 | #define GLT_BLUE 3 |
| 395 | #define GLT_ALPHA 4 |
| 396 | #define GLT_STATE_SIZE 5 |
| 397 | |
| 398 | /* EYE |
| 399 | */ |
| 400 | #define EYE_CMD_0 0 |
| 401 | #define EYE_X 1 |
| 402 | #define EYE_Y 2 |
| 403 | #define EYE_Z 3 |
| 404 | #define EYE_RESCALE_FACTOR 4 |
| 405 | #define EYE_STATE_SIZE 5 |
| 406 | |
| 407 | #define SHN_CMD_0 0 |
| 408 | #define SHN_SHININESS 1 |
| 409 | #define SHN_STATE_SIZE 2 |
| 410 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 411 | struct radeon_hw_state { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 412 | /* Head of the linked list of state atoms. */ |
| 413 | struct radeon_state_atom atomlist; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 414 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 415 | /* Hardware state, stored as cmdbuf commands: |
| 416 | * -- Need to doublebuffer for |
| 417 | * - eliding noop statechange loops? (except line stipple count) |
| 418 | */ |
| 419 | struct radeon_state_atom ctx; |
| 420 | struct radeon_state_atom set; |
| 421 | struct radeon_state_atom lin; |
| 422 | struct radeon_state_atom msk; |
| 423 | struct radeon_state_atom vpt; |
| 424 | struct radeon_state_atom tcl; |
| 425 | struct radeon_state_atom msc; |
| 426 | struct radeon_state_atom tex[3]; |
| 427 | struct radeon_state_atom cube[3]; |
| 428 | struct radeon_state_atom zbs; |
| 429 | struct radeon_state_atom mtl; |
| 430 | struct radeon_state_atom mat[6]; |
| 431 | struct radeon_state_atom lit[8]; /* includes vec, scl commands */ |
| 432 | struct radeon_state_atom ucp[6]; |
| 433 | struct radeon_state_atom eye; /* eye pos */ |
| 434 | struct radeon_state_atom grd; /* guard band clipping */ |
| 435 | struct radeon_state_atom fog; |
| 436 | struct radeon_state_atom glt; |
| 437 | struct radeon_state_atom txr[3]; /* for NPOT */ |
Eric Anholt | 6f3cc6a | 2004-08-17 01:41:29 +0000 | [diff] [blame] | 438 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 439 | int max_state_size; /* Number of bytes necessary for a full state emit. */ |
| 440 | GLboolean is_dirty, all_dirty; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 441 | }; |
| 442 | |
| 443 | struct radeon_state { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 444 | /* Derived state for internal purposes: |
| 445 | */ |
| 446 | struct radeon_colorbuffer_state color; |
| 447 | struct radeon_depthbuffer_state depth; |
| 448 | struct radeon_scissor_state scissor; |
| 449 | struct radeon_stencilbuffer_state stencil; |
| 450 | struct radeon_stipple_state stipple; |
| 451 | struct radeon_texture_state texture; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 452 | }; |
| 453 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 454 | /* Need refcounting on dma buffers: |
| 455 | */ |
| 456 | struct radeon_dma_buffer { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 457 | int refcount; /* the number of retained regions in buf */ |
| 458 | drmBufPtr buf; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 459 | }; |
| 460 | |
Jon Smirl | bcc6edd | 2003-10-21 06:05:39 +0000 | [diff] [blame] | 461 | #define GET_START(rvb) (rmesa->radeonScreen->gart_buffer_offset + \ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 462 | (rvb)->address - rmesa->dma.buf0_address + \ |
| 463 | (rvb)->start) |
| 464 | |
| 465 | /* A retained region, eg vertices for indexed vertices. |
| 466 | */ |
| 467 | struct radeon_dma_region { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 468 | struct radeon_dma_buffer *buf; |
| 469 | char *address; /* == buf->address */ |
| 470 | int start, end, ptr; /* offsets from start of buf */ |
| 471 | int aos_start; |
| 472 | int aos_stride; |
| 473 | int aos_size; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 474 | }; |
| 475 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 476 | struct radeon_dma { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 477 | /* Active dma region. Allocations for vertices and retained |
| 478 | * regions come from here. Also used for emitting random vertices, |
| 479 | * these may be flushed by calling flush_current(); |
| 480 | */ |
| 481 | struct radeon_dma_region current; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 482 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 483 | void (*flush) (radeonContextPtr); |
| 484 | |
| 485 | char *buf0_address; /* start of buf[0], for index calcs */ |
| 486 | GLuint nr_released_bufs; /* flush after so many buffers released */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 487 | }; |
| 488 | |
| 489 | struct radeon_dri_mirror { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 490 | __DRIcontextPrivate *context; /* DRI context */ |
| 491 | __DRIscreenPrivate *screen; /* DRI screen */ |
Ian Romanick | 3beaff1 | 2006-10-18 20:27:11 +0000 | [diff] [blame] | 492 | |
| 493 | /** |
| 494 | * DRI drawable bound to this context for drawing. |
| 495 | */ |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 496 | __DRIdrawablePrivate *drawable; |
Ian Romanick | 3beaff1 | 2006-10-18 20:27:11 +0000 | [diff] [blame] | 497 | |
| 498 | /** |
| 499 | * DRI drawable bound to this context for reading. |
| 500 | */ |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 501 | __DRIdrawablePrivate *readable; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 502 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 503 | drm_context_t hwContext; |
| 504 | drm_hw_lock_t *hwLock; |
| 505 | int fd; |
| 506 | int drmMinor; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 507 | }; |
| 508 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 509 | #define RADEON_CMD_BUF_SZ (8*1024) |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 510 | |
| 511 | struct radeon_store { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 512 | GLuint statenr; |
| 513 | GLuint primnr; |
| 514 | char cmd_buf[RADEON_CMD_BUF_SZ]; |
| 515 | int cmd_used; |
| 516 | int elts_start; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 517 | }; |
| 518 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 519 | /* radeon_tcl.c |
| 520 | */ |
| 521 | struct radeon_tcl_info { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 522 | GLuint vertex_format; |
| 523 | GLuint hw_primitive; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 524 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 525 | /* Temporary for cases where incoming vertex data is incompatible |
| 526 | * with maos code. |
| 527 | */ |
| 528 | GLvector4f ObjClean; |
Keith Whitwell | 57c9814 | 2003-11-24 15:21:14 +0000 | [diff] [blame] | 529 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 530 | struct radeon_dma_region *aos_components[8]; |
| 531 | GLuint nr_aos_components; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 532 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 533 | GLuint *Elts; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 534 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 535 | struct radeon_dma_region indexed_verts; |
| 536 | struct radeon_dma_region obj; |
| 537 | struct radeon_dma_region rgba; |
| 538 | struct radeon_dma_region spec; |
| 539 | struct radeon_dma_region fog; |
| 540 | struct radeon_dma_region tex[RADEON_MAX_TEXTURE_UNITS]; |
| 541 | struct radeon_dma_region norm; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 542 | }; |
| 543 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 544 | /* radeon_swtcl.c |
| 545 | */ |
| 546 | struct radeon_swtcl_info { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 547 | GLuint RenderIndex; |
| 548 | GLuint vertex_size; |
| 549 | GLuint vertex_format; |
Eric Anholt | 8a1df96 | 2005-05-31 04:04:24 +0000 | [diff] [blame] | 550 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 551 | struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX]; |
| 552 | GLuint vertex_attr_count; |
Eric Anholt | 8a1df96 | 2005-05-31 04:04:24 +0000 | [diff] [blame] | 553 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 554 | GLubyte *verts; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 555 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 556 | /* Fallback rasterization functions |
| 557 | */ |
| 558 | radeon_point_func draw_point; |
| 559 | radeon_line_func draw_line; |
| 560 | radeon_tri_func draw_tri; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 561 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 562 | GLuint hw_primitive; |
| 563 | GLenum render_primitive; |
| 564 | GLuint numverts; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 565 | |
Eric Anholt | 8a1df96 | 2005-05-31 04:04:24 +0000 | [diff] [blame] | 566 | /** |
| 567 | * Offset of the 4UB color data within a hardware (swtcl) vertex. |
| 568 | */ |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 569 | GLuint coloroffset; |
Eric Anholt | 8a1df96 | 2005-05-31 04:04:24 +0000 | [diff] [blame] | 570 | |
| 571 | /** |
| 572 | * Offset of the 3UB specular color data within a hardware (swtcl) vertex. |
| 573 | */ |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 574 | GLuint specoffset; |
Eric Anholt | 8a1df96 | 2005-05-31 04:04:24 +0000 | [diff] [blame] | 575 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 576 | GLboolean needproj; |
Eric Anholt | 8a1df96 | 2005-05-31 04:04:24 +0000 | [diff] [blame] | 577 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 578 | struct radeon_dma_region indexed_verts; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 579 | }; |
| 580 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 581 | struct radeon_ioctl { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 582 | GLuint vertex_offset; |
| 583 | GLuint vertex_size; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 584 | }; |
| 585 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 586 | #define RADEON_MAX_PRIMS 64 |
| 587 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 588 | struct radeon_prim { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 589 | GLuint start; |
| 590 | GLuint end; |
| 591 | GLuint prim; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 592 | }; |
| 593 | |
Roland Scheidegger | 30daa75 | 2005-10-13 14:30:20 +0000 | [diff] [blame] | 594 | /* A maximum total of 20 elements per vertex: 3 floats for position, 3 |
| 595 | * floats for normal, 4 floats for color, 4 bytes for secondary color, |
| 596 | * 3 floats for each texture unit (9 floats total). |
| 597 | * |
| 598 | * The position data is never actually stored here, so 3 elements could be |
| 599 | * trimmed out of the buffer. This number is only valid for vtxfmt! |
| 600 | */ |
| 601 | #define RADEON_MAX_VERTEX_SIZE 20 |
| 602 | |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 603 | struct radeon_context { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 604 | GLcontext *glCtx; /* Mesa context */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 605 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 606 | /* Driver and hardware state management |
| 607 | */ |
| 608 | struct radeon_hw_state hw; |
| 609 | struct radeon_state state; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 610 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 611 | /* Texture object bookkeeping |
| 612 | */ |
| 613 | unsigned nr_heaps; |
| 614 | driTexHeap *texture_heaps[RADEON_NR_TEX_HEAPS]; |
| 615 | driTextureObject swapped; |
| 616 | int texture_depth; |
| 617 | float initialMaxAnisotropy; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 618 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 619 | /* Rasterization and vertex state: |
| 620 | */ |
| 621 | GLuint TclFallback; |
| 622 | GLuint Fallback; |
| 623 | GLuint NewGLState; |
| 624 | DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 625 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 626 | /* Vertex buffers |
| 627 | */ |
| 628 | struct radeon_ioctl ioctl; |
| 629 | struct radeon_dma dma; |
| 630 | struct radeon_store store; |
| 631 | /* A full state emit as of the first state emit in the main store, in case |
| 632 | * the context is lost. |
| 633 | */ |
| 634 | struct radeon_store backup_store; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 635 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 636 | /* Page flipping |
| 637 | */ |
| 638 | GLuint doPageFlip; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 639 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 640 | /* Busy waiting |
| 641 | */ |
| 642 | GLuint do_usleeps; |
| 643 | GLuint do_irqs; |
| 644 | GLuint irqsEmitted; |
| 645 | drm_radeon_irq_wait_t iw; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 646 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 647 | /* Drawable, cliprect and scissor information |
| 648 | */ |
| 649 | GLuint numClipRects; /* Cliprects for the draw buffer */ |
| 650 | drm_clip_rect_t *pClipRects; |
| 651 | unsigned int lastStamp; |
| 652 | GLboolean lost_context; |
| 653 | GLboolean save_on_next_emit; |
| 654 | radeonScreenPtr radeonScreen; /* Screen private DRI data */ |
| 655 | drm_radeon_sarea_t *sarea; /* Private SAREA data */ |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 656 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 657 | /* TCL stuff |
| 658 | */ |
| 659 | GLmatrix TexGenMatrix[RADEON_MAX_TEXTURE_UNITS]; |
| 660 | GLboolean recheck_texgen[RADEON_MAX_TEXTURE_UNITS]; |
| 661 | GLboolean TexGenNeedNormals[RADEON_MAX_TEXTURE_UNITS]; |
| 662 | GLuint TexGenEnabled; |
| 663 | GLuint NeedTexMatrix; |
| 664 | GLuint TexMatColSwap; |
| 665 | GLmatrix tmpmat[RADEON_MAX_TEXTURE_UNITS]; |
| 666 | GLuint last_ReallyEnabled; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 667 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 668 | /* VBI |
| 669 | */ |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 670 | int64_t swap_ust; |
| 671 | int64_t swap_missed_ust; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 672 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 673 | GLuint swap_count; |
| 674 | GLuint swap_missed_count; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 675 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 676 | /* radeon_tcl.c |
| 677 | */ |
| 678 | struct radeon_tcl_info tcl; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 679 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 680 | /* radeon_swtcl.c |
| 681 | */ |
| 682 | struct radeon_swtcl_info swtcl; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 683 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 684 | /* Mirrors of some DRI state |
| 685 | */ |
| 686 | struct radeon_dri_mirror dri; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 687 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 688 | /* Configuration cache |
| 689 | */ |
| 690 | driOptionCache optionCache; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 691 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 692 | GLboolean using_hyperz; |
| 693 | GLboolean texmicrotile; |
Jon Smirl | bcc6edd | 2003-10-21 06:05:39 +0000 | [diff] [blame] | 694 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 695 | /* Performance counters |
| 696 | */ |
| 697 | GLuint boxes; /* Draw performance boxes */ |
| 698 | GLuint hardwareWentIdle; |
| 699 | GLuint c_clears; |
| 700 | GLuint c_drawWaits; |
| 701 | GLuint c_textureSwaps; |
| 702 | GLuint c_textureBytes; |
| 703 | GLuint c_vertexBuffers; |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 704 | }; |
| 705 | |
| 706 | #define RADEON_CONTEXT(ctx) ((radeonContextPtr)(ctx->DriverCtx)) |
| 707 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 708 | static __inline GLuint radeonPackColor(GLuint cpp, |
| 709 | GLubyte r, GLubyte g, |
| 710 | GLubyte b, GLubyte a) |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 711 | { |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 712 | switch (cpp) { |
| 713 | case 2: |
| 714 | return PACK_COLOR_565(r, g, b); |
| 715 | case 4: |
| 716 | return PACK_COLOR_8888(a, r, g, b); |
| 717 | default: |
| 718 | return 0; |
| 719 | } |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 720 | } |
| 721 | |
| 722 | #define RADEON_OLD_PACKETS 1 |
| 723 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 724 | extern void radeonDestroyContext(__DRIcontextPrivate * driContextPriv); |
| 725 | extern GLboolean radeonCreateContext(const __GLcontextModes * glVisual, |
| 726 | __DRIcontextPrivate * driContextPriv, |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 727 | void *sharedContextPrivate); |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 728 | extern void radeonSwapBuffers(__DRIdrawablePrivate * dPriv); |
Brian Paul | f2ad1b6 | 2006-03-31 15:48:04 +0000 | [diff] [blame] | 729 | extern void radeonCopySubBuffer(__DRIdrawablePrivate * dPriv, |
| 730 | int x, int y, int w, int h); |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 731 | extern GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv, |
| 732 | __DRIdrawablePrivate * driDrawPriv, |
| 733 | __DRIdrawablePrivate * driReadPriv); |
| 734 | extern GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv); |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 735 | |
| 736 | /* ================================================================ |
| 737 | * Debugging: |
| 738 | */ |
| 739 | #define DO_DEBUG 1 |
| 740 | |
| 741 | #if DO_DEBUG |
| 742 | extern int RADEON_DEBUG; |
| 743 | #else |
| 744 | #define RADEON_DEBUG 0 |
| 745 | #endif |
| 746 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 747 | #define DEBUG_TEXTURE 0x0001 |
| 748 | #define DEBUG_STATE 0x0002 |
| 749 | #define DEBUG_IOCTL 0x0004 |
| 750 | #define DEBUG_PRIMS 0x0008 |
| 751 | #define DEBUG_VERTS 0x0010 |
| 752 | #define DEBUG_FALLBACKS 0x0020 |
| 753 | #define DEBUG_VFMT 0x0040 |
| 754 | #define DEBUG_CODEGEN 0x0080 |
| 755 | #define DEBUG_VERBOSE 0x0100 |
| 756 | #define DEBUG_DRI 0x0200 |
| 757 | #define DEBUG_DMA 0x0400 |
| 758 | #define DEBUG_SANITY 0x0800 |
| 759 | #define DEBUG_SYNC 0x1000 |
Brian Paul | 5df82c8 | 2003-08-22 20:11:43 +0000 | [diff] [blame] | 760 | |
Oliver McFadden | 4d5d4e1 | 2007-05-09 21:06:28 +0000 | [diff] [blame] | 761 | #endif /* __RADEON_CONTEXT_H__ */ |