Keith Whitwell | 2f5f7c0 | 2009-10-23 16:55:02 +0100 | [diff] [blame] | 1 | /* |
| 2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. |
| 3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to |
| 4 | develop this 3D driver. |
| 5 | |
| 6 | Permission is hereby granted, free of charge, to any person obtaining |
| 7 | a copy of this software and associated documentation files (the |
| 8 | "Software"), to deal in the Software without restriction, including |
| 9 | without limitation the rights to use, copy, modify, merge, publish, |
| 10 | distribute, sublicense, and/or sell copies of the Software, and to |
| 11 | permit persons to whom the Software is furnished to do so, subject to |
| 12 | the following conditions: |
| 13 | |
| 14 | The above copyright notice and this permission notice (including the |
| 15 | next paragraph) shall be included in all copies or substantial |
| 16 | portions of the Software. |
| 17 | |
| 18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| 22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| 23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| 24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 25 | |
| 26 | **********************************************************************/ |
| 27 | /* |
| 28 | * Authors: |
| 29 | * Keith Whitwell <keith@tungstengraphics.com> |
| 30 | */ |
| 31 | |
| 32 | |
| 33 | #ifndef BRW_DEFINES_H |
| 34 | #define BRW_DEFINES_H |
| 35 | |
| 36 | /* 3D state: |
| 37 | */ |
| 38 | #define _3DOP_3DSTATE_PIPELINED 0x0 |
| 39 | #define _3DOP_3DSTATE_NONPIPELINED 0x1 |
| 40 | #define _3DOP_3DCONTROL 0x2 |
| 41 | #define _3DOP_3DPRIMITIVE 0x3 |
| 42 | |
| 43 | #define _3DSTATE_PIPELINED_POINTERS 0x00 |
| 44 | #define _3DSTATE_BINDING_TABLE_POINTERS 0x01 |
| 45 | #define _3DSTATE_VERTEX_BUFFERS 0x08 |
| 46 | #define _3DSTATE_VERTEX_ELEMENTS 0x09 |
| 47 | #define _3DSTATE_INDEX_BUFFER 0x0A |
| 48 | #define _3DSTATE_VF_STATISTICS 0x0B |
| 49 | #define _3DSTATE_DRAWING_RECTANGLE 0x00 |
| 50 | #define _3DSTATE_CONSTANT_COLOR 0x01 |
| 51 | #define _3DSTATE_SAMPLER_PALETTE_LOAD 0x02 |
| 52 | #define _3DSTATE_CHROMA_KEY 0x04 |
| 53 | #define _3DSTATE_DEPTH_BUFFER 0x05 |
| 54 | #define _3DSTATE_POLY_STIPPLE_OFFSET 0x06 |
| 55 | #define _3DSTATE_POLY_STIPPLE_PATTERN 0x07 |
| 56 | #define _3DSTATE_LINE_STIPPLE 0x08 |
| 57 | #define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09 |
| 58 | #define _3DCONTROL 0x00 |
| 59 | |
| 60 | #define PIPE_CONTROL_NOWRITE 0x00 |
| 61 | #define PIPE_CONTROL_WRITEIMMEDIATE 0x01 |
| 62 | #define PIPE_CONTROL_WRITEDEPTH 0x02 |
| 63 | #define PIPE_CONTROL_WRITETIMESTAMP 0x03 |
| 64 | |
| 65 | #define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00 |
| 66 | #define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01 |
| 67 | |
| 68 | #define _3DPRIM_POINTLIST 0x01 |
| 69 | #define _3DPRIM_LINELIST 0x02 |
| 70 | #define _3DPRIM_LINESTRIP 0x03 |
| 71 | #define _3DPRIM_TRILIST 0x04 |
| 72 | #define _3DPRIM_TRISTRIP 0x05 |
| 73 | #define _3DPRIM_TRIFAN 0x06 |
| 74 | #define _3DPRIM_QUADLIST 0x07 |
| 75 | #define _3DPRIM_QUADSTRIP 0x08 |
| 76 | #define _3DPRIM_LINELIST_ADJ 0x09 |
| 77 | #define _3DPRIM_LINESTRIP_ADJ 0x0A |
| 78 | #define _3DPRIM_TRILIST_ADJ 0x0B |
| 79 | #define _3DPRIM_TRISTRIP_ADJ 0x0C |
| 80 | #define _3DPRIM_TRISTRIP_REVERSE 0x0D |
| 81 | #define _3DPRIM_POLYGON 0x0E |
| 82 | #define _3DPRIM_RECTLIST 0x0F |
| 83 | #define _3DPRIM_LINELOOP 0x10 |
| 84 | #define _3DPRIM_POINTLIST_BF 0x11 |
| 85 | #define _3DPRIM_LINESTRIP_CONT 0x12 |
| 86 | #define _3DPRIM_LINESTRIP_BF 0x13 |
| 87 | #define _3DPRIM_LINESTRIP_CONT_BF 0x14 |
| 88 | #define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 |
| 89 | |
| 90 | #define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0 |
| 91 | #define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1 |
| 92 | |
| 93 | #define BRW_ANISORATIO_2 0 |
| 94 | #define BRW_ANISORATIO_4 1 |
| 95 | #define BRW_ANISORATIO_6 2 |
| 96 | #define BRW_ANISORATIO_8 3 |
| 97 | #define BRW_ANISORATIO_10 4 |
| 98 | #define BRW_ANISORATIO_12 5 |
| 99 | #define BRW_ANISORATIO_14 6 |
| 100 | #define BRW_ANISORATIO_16 7 |
| 101 | |
| 102 | #define BRW_BLENDFACTOR_ONE 0x1 |
| 103 | #define BRW_BLENDFACTOR_SRC_COLOR 0x2 |
| 104 | #define BRW_BLENDFACTOR_SRC_ALPHA 0x3 |
| 105 | #define BRW_BLENDFACTOR_DST_ALPHA 0x4 |
| 106 | #define BRW_BLENDFACTOR_DST_COLOR 0x5 |
| 107 | #define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 |
| 108 | #define BRW_BLENDFACTOR_CONST_COLOR 0x7 |
| 109 | #define BRW_BLENDFACTOR_CONST_ALPHA 0x8 |
| 110 | #define BRW_BLENDFACTOR_SRC1_COLOR 0x9 |
| 111 | #define BRW_BLENDFACTOR_SRC1_ALPHA 0x0A |
| 112 | #define BRW_BLENDFACTOR_ZERO 0x11 |
| 113 | #define BRW_BLENDFACTOR_INV_SRC_COLOR 0x12 |
| 114 | #define BRW_BLENDFACTOR_INV_SRC_ALPHA 0x13 |
| 115 | #define BRW_BLENDFACTOR_INV_DST_ALPHA 0x14 |
| 116 | #define BRW_BLENDFACTOR_INV_DST_COLOR 0x15 |
| 117 | #define BRW_BLENDFACTOR_INV_CONST_COLOR 0x17 |
| 118 | #define BRW_BLENDFACTOR_INV_CONST_ALPHA 0x18 |
| 119 | #define BRW_BLENDFACTOR_INV_SRC1_COLOR 0x19 |
| 120 | #define BRW_BLENDFACTOR_INV_SRC1_ALPHA 0x1A |
| 121 | |
| 122 | #define BRW_BLENDFUNCTION_ADD 0 |
| 123 | #define BRW_BLENDFUNCTION_SUBTRACT 1 |
| 124 | #define BRW_BLENDFUNCTION_REVERSE_SUBTRACT 2 |
| 125 | #define BRW_BLENDFUNCTION_MIN 3 |
| 126 | #define BRW_BLENDFUNCTION_MAX 4 |
| 127 | |
| 128 | #define BRW_ALPHATEST_FORMAT_UNORM8 0 |
| 129 | #define BRW_ALPHATEST_FORMAT_FLOAT32 1 |
| 130 | |
| 131 | #define BRW_CHROMAKEY_KILL_ON_ANY_MATCH 0 |
| 132 | #define BRW_CHROMAKEY_REPLACE_BLACK 1 |
| 133 | |
| 134 | #define BRW_CLIP_API_OGL 0 |
| 135 | #define BRW_CLIP_API_DX 1 |
| 136 | |
| 137 | #define BRW_CLIPMODE_NORMAL 0 |
| 138 | #define BRW_CLIPMODE_CLIP_ALL 1 |
| 139 | #define BRW_CLIPMODE_CLIP_NON_REJECTED 2 |
| 140 | #define BRW_CLIPMODE_REJECT_ALL 3 |
| 141 | #define BRW_CLIPMODE_ACCEPT_ALL 4 |
| 142 | #define BRW_CLIPMODE_KERNEL_CLIP 5 |
| 143 | |
| 144 | #define BRW_CLIP_NDCSPACE 0 |
| 145 | #define BRW_CLIP_SCREENSPACE 1 |
| 146 | |
| 147 | #define BRW_COMPAREFUNCTION_ALWAYS 0 |
| 148 | #define BRW_COMPAREFUNCTION_NEVER 1 |
| 149 | #define BRW_COMPAREFUNCTION_LESS 2 |
| 150 | #define BRW_COMPAREFUNCTION_EQUAL 3 |
| 151 | #define BRW_COMPAREFUNCTION_LEQUAL 4 |
| 152 | #define BRW_COMPAREFUNCTION_GREATER 5 |
| 153 | #define BRW_COMPAREFUNCTION_NOTEQUAL 6 |
| 154 | #define BRW_COMPAREFUNCTION_GEQUAL 7 |
| 155 | |
| 156 | #define BRW_COVERAGE_PIXELS_HALF 0 |
| 157 | #define BRW_COVERAGE_PIXELS_1 1 |
| 158 | #define BRW_COVERAGE_PIXELS_2 2 |
| 159 | #define BRW_COVERAGE_PIXELS_4 3 |
| 160 | |
| 161 | #define BRW_CULLMODE_BOTH 0 |
| 162 | #define BRW_CULLMODE_NONE 1 |
| 163 | #define BRW_CULLMODE_FRONT 2 |
| 164 | #define BRW_CULLMODE_BACK 3 |
| 165 | |
| 166 | #define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM 0 |
| 167 | #define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT 1 |
| 168 | |
| 169 | #define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0 |
| 170 | #define BRW_DEPTHFORMAT_D32_FLOAT 1 |
| 171 | #define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT 2 |
| 172 | #define BRW_DEPTHFORMAT_D16_UNORM 5 |
| 173 | |
| 174 | #define BRW_FLOATING_POINT_IEEE_754 0 |
| 175 | #define BRW_FLOATING_POINT_NON_IEEE_754 1 |
| 176 | |
| 177 | #define BRW_FRONTWINDING_CW 0 |
| 178 | #define BRW_FRONTWINDING_CCW 1 |
| 179 | |
| 180 | #define BRW_SPRITE_POINT_ENABLE 16 |
| 181 | |
| 182 | #define BRW_INDEX_BYTE 0 |
| 183 | #define BRW_INDEX_WORD 1 |
| 184 | #define BRW_INDEX_DWORD 2 |
| 185 | |
| 186 | #define BRW_LOGICOPFUNCTION_CLEAR 0 |
| 187 | #define BRW_LOGICOPFUNCTION_NOR 1 |
| 188 | #define BRW_LOGICOPFUNCTION_AND_INVERTED 2 |
| 189 | #define BRW_LOGICOPFUNCTION_COPY_INVERTED 3 |
| 190 | #define BRW_LOGICOPFUNCTION_AND_REVERSE 4 |
| 191 | #define BRW_LOGICOPFUNCTION_INVERT 5 |
| 192 | #define BRW_LOGICOPFUNCTION_XOR 6 |
| 193 | #define BRW_LOGICOPFUNCTION_NAND 7 |
| 194 | #define BRW_LOGICOPFUNCTION_AND 8 |
| 195 | #define BRW_LOGICOPFUNCTION_EQUIV 9 |
| 196 | #define BRW_LOGICOPFUNCTION_NOOP 10 |
| 197 | #define BRW_LOGICOPFUNCTION_OR_INVERTED 11 |
| 198 | #define BRW_LOGICOPFUNCTION_COPY 12 |
| 199 | #define BRW_LOGICOPFUNCTION_OR_REVERSE 13 |
| 200 | #define BRW_LOGICOPFUNCTION_OR 14 |
| 201 | #define BRW_LOGICOPFUNCTION_SET 15 |
| 202 | |
| 203 | #define BRW_MAPFILTER_NEAREST 0x0 |
| 204 | #define BRW_MAPFILTER_LINEAR 0x1 |
| 205 | #define BRW_MAPFILTER_ANISOTROPIC 0x2 |
| 206 | |
| 207 | #define BRW_MIPFILTER_NONE 0 |
| 208 | #define BRW_MIPFILTER_NEAREST 1 |
| 209 | #define BRW_MIPFILTER_LINEAR 3 |
| 210 | |
| 211 | #define BRW_POLYGON_FRONT_FACING 0 |
| 212 | #define BRW_POLYGON_BACK_FACING 1 |
| 213 | |
| 214 | #define BRW_PREFILTER_ALWAYS 0x0 |
| 215 | #define BRW_PREFILTER_NEVER 0x1 |
| 216 | #define BRW_PREFILTER_LESS 0x2 |
| 217 | #define BRW_PREFILTER_EQUAL 0x3 |
| 218 | #define BRW_PREFILTER_LEQUAL 0x4 |
| 219 | #define BRW_PREFILTER_GREATER 0x5 |
| 220 | #define BRW_PREFILTER_NOTEQUAL 0x6 |
| 221 | #define BRW_PREFILTER_GEQUAL 0x7 |
| 222 | |
| 223 | #define BRW_PROVOKING_VERTEX_0 0 |
| 224 | #define BRW_PROVOKING_VERTEX_1 1 |
| 225 | #define BRW_PROVOKING_VERTEX_2 2 |
| 226 | |
| 227 | #define BRW_RASTRULE_UPPER_LEFT 0 |
| 228 | #define BRW_RASTRULE_UPPER_RIGHT 1 |
| 229 | /* These are listed as "Reserved, but not seen as useful" |
| 230 | * in Intel documentation (page 212, "Point Rasterization Rule", |
| 231 | * section 7.4 "SF Pipeline State Summary", of document |
| 232 | * "Intel® 965 Express Chipset Family and Intel® G35 Express |
| 233 | * Chipset Graphics Controller Programmer's Reference Manual, |
| 234 | * Volume 2: 3D/Media", Revision 1.0b as of January 2008, |
| 235 | * available at |
| 236 | * http://intellinuxgraphics.org/documentation.html |
| 237 | * at the time of this writing). |
| 238 | * |
| 239 | * These appear to be supported on at least some |
| 240 | * i965-family devices, and the BRW_RASTRULE_LOWER_RIGHT |
| 241 | * is useful when using OpenGL to render to a FBO |
| 242 | * (which has the pixel coordinate Y orientation inverted |
| 243 | * with respect to the normal OpenGL pixel coordinate system). |
| 244 | */ |
| 245 | #define BRW_RASTRULE_LOWER_LEFT 2 |
| 246 | #define BRW_RASTRULE_LOWER_RIGHT 3 |
| 247 | |
| 248 | #define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0 |
| 249 | #define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1 |
| 250 | #define BRW_RENDERTARGET_CLAMPRANGE_FORMAT 2 |
| 251 | |
| 252 | #define BRW_STENCILOP_KEEP 0 |
| 253 | #define BRW_STENCILOP_ZERO 1 |
| 254 | #define BRW_STENCILOP_REPLACE 2 |
| 255 | #define BRW_STENCILOP_INCRSAT 3 |
| 256 | #define BRW_STENCILOP_DECRSAT 4 |
| 257 | #define BRW_STENCILOP_INCR 5 |
| 258 | #define BRW_STENCILOP_DECR 6 |
| 259 | #define BRW_STENCILOP_INVERT 7 |
| 260 | |
| 261 | #define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0 |
| 262 | #define BRW_SURFACE_MIPMAPLAYOUT_RIGHT 1 |
| 263 | |
| 264 | #define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 |
| 265 | #define BRW_SURFACEFORMAT_R32G32B32A32_SINT 0x001 |
| 266 | #define BRW_SURFACEFORMAT_R32G32B32A32_UINT 0x002 |
| 267 | #define BRW_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 |
| 268 | #define BRW_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 |
| 269 | #define BRW_SURFACEFORMAT_R64G64_FLOAT 0x005 |
| 270 | #define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 |
| 271 | #define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 |
| 272 | #define BRW_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 |
| 273 | #define BRW_SURFACEFORMAT_R32G32B32_FLOAT 0x040 |
| 274 | #define BRW_SURFACEFORMAT_R32G32B32_SINT 0x041 |
| 275 | #define BRW_SURFACEFORMAT_R32G32B32_UINT 0x042 |
| 276 | #define BRW_SURFACEFORMAT_R32G32B32_UNORM 0x043 |
| 277 | #define BRW_SURFACEFORMAT_R32G32B32_SNORM 0x044 |
| 278 | #define BRW_SURFACEFORMAT_R32G32B32_SSCALED 0x045 |
| 279 | #define BRW_SURFACEFORMAT_R32G32B32_USCALED 0x046 |
| 280 | #define BRW_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 |
| 281 | #define BRW_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 |
| 282 | #define BRW_SURFACEFORMAT_R16G16B16A16_SINT 0x082 |
| 283 | #define BRW_SURFACEFORMAT_R16G16B16A16_UINT 0x083 |
| 284 | #define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 |
| 285 | #define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 |
| 286 | #define BRW_SURFACEFORMAT_R32G32_SINT 0x086 |
| 287 | #define BRW_SURFACEFORMAT_R32G32_UINT 0x087 |
| 288 | #define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 |
| 289 | #define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089 |
| 290 | #define BRW_SURFACEFORMAT_L32A32_FLOAT 0x08A |
| 291 | #define BRW_SURFACEFORMAT_R32G32_UNORM 0x08B |
| 292 | #define BRW_SURFACEFORMAT_R32G32_SNORM 0x08C |
| 293 | #define BRW_SURFACEFORMAT_R64_FLOAT 0x08D |
| 294 | #define BRW_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E |
| 295 | #define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F |
| 296 | #define BRW_SURFACEFORMAT_A32X32_FLOAT 0x090 |
| 297 | #define BRW_SURFACEFORMAT_L32X32_FLOAT 0x091 |
| 298 | #define BRW_SURFACEFORMAT_I32X32_FLOAT 0x092 |
| 299 | #define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 |
| 300 | #define BRW_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 |
| 301 | #define BRW_SURFACEFORMAT_R32G32_SSCALED 0x095 |
| 302 | #define BRW_SURFACEFORMAT_R32G32_USCALED 0x096 |
| 303 | #define BRW_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 |
| 304 | #define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1 |
| 305 | #define BRW_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 |
| 306 | #define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 |
| 307 | #define BRW_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 |
| 308 | #define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 |
| 309 | #define BRW_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 |
| 310 | #define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8 |
| 311 | #define BRW_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 |
| 312 | #define BRW_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA |
| 313 | #define BRW_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB |
| 314 | #define BRW_SURFACEFORMAT_R16G16_UNORM 0x0CC |
| 315 | #define BRW_SURFACEFORMAT_R16G16_SNORM 0x0CD |
| 316 | #define BRW_SURFACEFORMAT_R16G16_SINT 0x0CE |
| 317 | #define BRW_SURFACEFORMAT_R16G16_UINT 0x0CF |
| 318 | #define BRW_SURFACEFORMAT_R16G16_FLOAT 0x0D0 |
| 319 | #define BRW_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 |
| 320 | #define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 |
| 321 | #define BRW_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3 |
| 322 | #define BRW_SURFACEFORMAT_R32_SINT 0x0D6 |
| 323 | #define BRW_SURFACEFORMAT_R32_UINT 0x0D7 |
| 324 | #define BRW_SURFACEFORMAT_R32_FLOAT 0x0D8 |
| 325 | #define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9 |
| 326 | #define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA |
| 327 | #define BRW_SURFACEFORMAT_L16A16_UNORM 0x0DF |
| 328 | #define BRW_SURFACEFORMAT_I24X8_UNORM 0x0E0 |
| 329 | #define BRW_SURFACEFORMAT_L24X8_UNORM 0x0E1 |
| 330 | #define BRW_SURFACEFORMAT_A24X8_UNORM 0x0E2 |
| 331 | #define BRW_SURFACEFORMAT_I32_FLOAT 0x0E3 |
| 332 | #define BRW_SURFACEFORMAT_L32_FLOAT 0x0E4 |
| 333 | #define BRW_SURFACEFORMAT_A32_FLOAT 0x0E5 |
| 334 | #define BRW_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9 |
| 335 | #define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA |
| 336 | #define BRW_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB |
| 337 | #define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC |
| 338 | #define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED |
| 339 | #define BRW_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE |
| 340 | #define BRW_SURFACEFORMAT_L16A16_FLOAT 0x0F0 |
| 341 | #define BRW_SURFACEFORMAT_R32_UNORM 0x0F1 |
| 342 | #define BRW_SURFACEFORMAT_R32_SNORM 0x0F2 |
| 343 | #define BRW_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3 |
| 344 | #define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4 |
| 345 | #define BRW_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5 |
| 346 | #define BRW_SURFACEFORMAT_R16G16_SSCALED 0x0F6 |
| 347 | #define BRW_SURFACEFORMAT_R16G16_USCALED 0x0F7 |
| 348 | #define BRW_SURFACEFORMAT_R32_SSCALED 0x0F8 |
| 349 | #define BRW_SURFACEFORMAT_R32_USCALED 0x0F9 |
| 350 | #define BRW_SURFACEFORMAT_B5G6R5_UNORM 0x100 |
| 351 | #define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101 |
| 352 | #define BRW_SURFACEFORMAT_B5G5R5A1_UNORM 0x102 |
| 353 | #define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103 |
| 354 | #define BRW_SURFACEFORMAT_B4G4R4A4_UNORM 0x104 |
| 355 | #define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105 |
| 356 | #define BRW_SURFACEFORMAT_R8G8_UNORM 0x106 |
| 357 | #define BRW_SURFACEFORMAT_R8G8_SNORM 0x107 |
| 358 | #define BRW_SURFACEFORMAT_R8G8_SINT 0x108 |
| 359 | #define BRW_SURFACEFORMAT_R8G8_UINT 0x109 |
| 360 | #define BRW_SURFACEFORMAT_R16_UNORM 0x10A |
| 361 | #define BRW_SURFACEFORMAT_R16_SNORM 0x10B |
| 362 | #define BRW_SURFACEFORMAT_R16_SINT 0x10C |
| 363 | #define BRW_SURFACEFORMAT_R16_UINT 0x10D |
| 364 | #define BRW_SURFACEFORMAT_R16_FLOAT 0x10E |
| 365 | #define BRW_SURFACEFORMAT_I16_UNORM 0x111 |
| 366 | #define BRW_SURFACEFORMAT_L16_UNORM 0x112 |
| 367 | #define BRW_SURFACEFORMAT_A16_UNORM 0x113 |
| 368 | #define BRW_SURFACEFORMAT_L8A8_UNORM 0x114 |
| 369 | #define BRW_SURFACEFORMAT_I16_FLOAT 0x115 |
| 370 | #define BRW_SURFACEFORMAT_L16_FLOAT 0x116 |
| 371 | #define BRW_SURFACEFORMAT_A16_FLOAT 0x117 |
| 372 | #define BRW_SURFACEFORMAT_L8A8_UNORM_SRGB 0x118 |
| 373 | #define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 |
| 374 | #define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A |
| 375 | #define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B |
| 376 | #define BRW_SURFACEFORMAT_R8G8_SSCALED 0x11C |
| 377 | #define BRW_SURFACEFORMAT_R8G8_USCALED 0x11D |
| 378 | #define BRW_SURFACEFORMAT_R16_SSCALED 0x11E |
| 379 | #define BRW_SURFACEFORMAT_R16_USCALED 0x11F |
| 380 | #define BRW_SURFACEFORMAT_R8_UNORM 0x140 |
| 381 | #define BRW_SURFACEFORMAT_R8_SNORM 0x141 |
| 382 | #define BRW_SURFACEFORMAT_R8_SINT 0x142 |
| 383 | #define BRW_SURFACEFORMAT_R8_UINT 0x143 |
| 384 | #define BRW_SURFACEFORMAT_A8_UNORM 0x144 |
| 385 | #define BRW_SURFACEFORMAT_I8_UNORM 0x145 |
| 386 | #define BRW_SURFACEFORMAT_L8_UNORM 0x146 |
| 387 | #define BRW_SURFACEFORMAT_P4A4_UNORM 0x147 |
| 388 | #define BRW_SURFACEFORMAT_A4P4_UNORM 0x148 |
| 389 | #define BRW_SURFACEFORMAT_R8_SSCALED 0x149 |
| 390 | #define BRW_SURFACEFORMAT_R8_USCALED 0x14A |
| 391 | #define BRW_SURFACEFORMAT_L8_UNORM_SRGB 0x14C |
| 392 | #define BRW_SURFACEFORMAT_R1_UINT 0x181 |
| 393 | #define BRW_SURFACEFORMAT_YCRCB_NORMAL 0x182 |
| 394 | #define BRW_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 |
| 395 | #define BRW_SURFACEFORMAT_BC1_UNORM 0x186 |
| 396 | #define BRW_SURFACEFORMAT_BC2_UNORM 0x187 |
| 397 | #define BRW_SURFACEFORMAT_BC3_UNORM 0x188 |
| 398 | #define BRW_SURFACEFORMAT_BC4_UNORM 0x189 |
| 399 | #define BRW_SURFACEFORMAT_BC5_UNORM 0x18A |
| 400 | #define BRW_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B |
| 401 | #define BRW_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C |
| 402 | #define BRW_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D |
| 403 | #define BRW_SURFACEFORMAT_MONO8 0x18E |
| 404 | #define BRW_SURFACEFORMAT_YCRCB_SWAPUV 0x18F |
| 405 | #define BRW_SURFACEFORMAT_YCRCB_SWAPY 0x190 |
| 406 | #define BRW_SURFACEFORMAT_DXT1_RGB 0x191 |
| 407 | #define BRW_SURFACEFORMAT_FXT1 0x192 |
| 408 | #define BRW_SURFACEFORMAT_R8G8B8_UNORM 0x193 |
| 409 | #define BRW_SURFACEFORMAT_R8G8B8_SNORM 0x194 |
| 410 | #define BRW_SURFACEFORMAT_R8G8B8_SSCALED 0x195 |
| 411 | #define BRW_SURFACEFORMAT_R8G8B8_USCALED 0x196 |
| 412 | #define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197 |
| 413 | #define BRW_SURFACEFORMAT_R64G64B64_FLOAT 0x198 |
| 414 | #define BRW_SURFACEFORMAT_BC4_SNORM 0x199 |
| 415 | #define BRW_SURFACEFORMAT_BC5_SNORM 0x19A |
| 416 | #define BRW_SURFACEFORMAT_R16G16B16_UNORM 0x19C |
| 417 | #define BRW_SURFACEFORMAT_R16G16B16_SNORM 0x19D |
| 418 | #define BRW_SURFACEFORMAT_R16G16B16_SSCALED 0x19E |
| 419 | #define BRW_SURFACEFORMAT_R16G16B16_USCALED 0x19F |
Keith Whitwell | 4a3e002 | 2009-11-01 17:18:56 +0000 | [diff] [blame] | 420 | #define BRW_SURFACEFORMAT_INVALID 0xFFF |
Keith Whitwell | 2f5f7c0 | 2009-10-23 16:55:02 +0100 | [diff] [blame] | 421 | |
| 422 | #define BRW_SURFACERETURNFORMAT_FLOAT32 0 |
| 423 | #define BRW_SURFACERETURNFORMAT_S1 1 |
| 424 | |
| 425 | #define BRW_SURFACE_1D 0 |
| 426 | #define BRW_SURFACE_2D 1 |
| 427 | #define BRW_SURFACE_3D 2 |
| 428 | #define BRW_SURFACE_CUBE 3 |
| 429 | #define BRW_SURFACE_BUFFER 4 |
| 430 | #define BRW_SURFACE_NULL 7 |
| 431 | |
| 432 | #define BRW_TEXCOORDMODE_WRAP 0 |
| 433 | #define BRW_TEXCOORDMODE_MIRROR 1 |
| 434 | #define BRW_TEXCOORDMODE_CLAMP 2 |
| 435 | #define BRW_TEXCOORDMODE_CUBE 3 |
| 436 | #define BRW_TEXCOORDMODE_CLAMP_BORDER 4 |
| 437 | #define BRW_TEXCOORDMODE_MIRROR_ONCE 5 |
| 438 | |
| 439 | #define BRW_THREAD_PRIORITY_NORMAL 0 |
| 440 | #define BRW_THREAD_PRIORITY_HIGH 1 |
| 441 | |
| 442 | #define BRW_TILEWALK_XMAJOR 0 |
| 443 | #define BRW_TILEWALK_YMAJOR 1 |
| 444 | |
| 445 | #define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS 0 |
| 446 | #define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS 1 |
| 447 | |
| 448 | /* Execution Unit (EU) defines |
| 449 | */ |
| 450 | |
| 451 | #define BRW_ALIGN_1 0 |
| 452 | #define BRW_ALIGN_16 1 |
| 453 | |
| 454 | #define BRW_ADDRESS_DIRECT 0 |
| 455 | #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1 |
| 456 | |
| 457 | #define BRW_CHANNEL_X 0 |
| 458 | #define BRW_CHANNEL_Y 1 |
| 459 | #define BRW_CHANNEL_Z 2 |
| 460 | #define BRW_CHANNEL_W 3 |
| 461 | |
| 462 | #define BRW_COMPRESSION_NONE 0 |
| 463 | #define BRW_COMPRESSION_2NDHALF 1 |
| 464 | #define BRW_COMPRESSION_COMPRESSED 2 |
| 465 | |
| 466 | #define BRW_CONDITIONAL_NONE 0 |
| 467 | #define BRW_CONDITIONAL_Z 1 |
| 468 | #define BRW_CONDITIONAL_NZ 2 |
| 469 | #define BRW_CONDITIONAL_EQ 1 /* Z */ |
| 470 | #define BRW_CONDITIONAL_NEQ 2 /* NZ */ |
| 471 | #define BRW_CONDITIONAL_G 3 |
| 472 | #define BRW_CONDITIONAL_GE 4 |
| 473 | #define BRW_CONDITIONAL_L 5 |
| 474 | #define BRW_CONDITIONAL_LE 6 |
| 475 | #define BRW_CONDITIONAL_R 7 |
| 476 | #define BRW_CONDITIONAL_O 8 |
| 477 | #define BRW_CONDITIONAL_U 9 |
| 478 | |
| 479 | #define BRW_DEBUG_NONE 0 |
| 480 | #define BRW_DEBUG_BREAKPOINT 1 |
| 481 | |
| 482 | #define BRW_DEPENDENCY_NORMAL 0 |
| 483 | #define BRW_DEPENDENCY_NOTCLEARED 1 |
| 484 | #define BRW_DEPENDENCY_NOTCHECKED 2 |
| 485 | #define BRW_DEPENDENCY_DISABLE 3 |
| 486 | |
| 487 | #define BRW_EXECUTE_1 0 |
| 488 | #define BRW_EXECUTE_2 1 |
| 489 | #define BRW_EXECUTE_4 2 |
| 490 | #define BRW_EXECUTE_8 3 |
| 491 | #define BRW_EXECUTE_16 4 |
| 492 | #define BRW_EXECUTE_32 5 |
| 493 | |
| 494 | #define BRW_HORIZONTAL_STRIDE_0 0 |
| 495 | #define BRW_HORIZONTAL_STRIDE_1 1 |
| 496 | #define BRW_HORIZONTAL_STRIDE_2 2 |
| 497 | #define BRW_HORIZONTAL_STRIDE_4 3 |
| 498 | |
| 499 | #define BRW_INSTRUCTION_NORMAL 0 |
| 500 | #define BRW_INSTRUCTION_SATURATE 1 |
| 501 | |
| 502 | #define BRW_MASK_ENABLE 0 |
| 503 | #define BRW_MASK_DISABLE 1 |
| 504 | |
| 505 | #define BRW_OPCODE_MOV 1 |
| 506 | #define BRW_OPCODE_SEL 2 |
| 507 | #define BRW_OPCODE_NOT 4 |
| 508 | #define BRW_OPCODE_AND 5 |
| 509 | #define BRW_OPCODE_OR 6 |
| 510 | #define BRW_OPCODE_XOR 7 |
| 511 | #define BRW_OPCODE_SHR 8 |
| 512 | #define BRW_OPCODE_SHL 9 |
| 513 | #define BRW_OPCODE_RSR 10 |
| 514 | #define BRW_OPCODE_RSL 11 |
| 515 | #define BRW_OPCODE_ASR 12 |
| 516 | #define BRW_OPCODE_CMP 16 |
| 517 | #define BRW_OPCODE_CMPN 17 |
| 518 | #define BRW_OPCODE_JMPI 32 |
| 519 | #define BRW_OPCODE_IF 34 |
| 520 | #define BRW_OPCODE_IFF 35 |
| 521 | #define BRW_OPCODE_ELSE 36 |
| 522 | #define BRW_OPCODE_ENDIF 37 |
| 523 | #define BRW_OPCODE_DO 38 |
| 524 | #define BRW_OPCODE_WHILE 39 |
| 525 | #define BRW_OPCODE_BREAK 40 |
| 526 | #define BRW_OPCODE_CONTINUE 41 |
| 527 | #define BRW_OPCODE_HALT 42 |
| 528 | #define BRW_OPCODE_MSAVE 44 |
| 529 | #define BRW_OPCODE_MRESTORE 45 |
| 530 | #define BRW_OPCODE_PUSH 46 |
| 531 | #define BRW_OPCODE_POP 47 |
| 532 | #define BRW_OPCODE_WAIT 48 |
| 533 | #define BRW_OPCODE_SEND 49 |
| 534 | #define BRW_OPCODE_ADD 64 |
| 535 | #define BRW_OPCODE_MUL 65 |
| 536 | #define BRW_OPCODE_AVG 66 |
| 537 | #define BRW_OPCODE_FRC 67 |
| 538 | #define BRW_OPCODE_RNDU 68 |
| 539 | #define BRW_OPCODE_RNDD 69 |
| 540 | #define BRW_OPCODE_RNDE 70 |
| 541 | #define BRW_OPCODE_RNDZ 71 |
| 542 | #define BRW_OPCODE_MAC 72 |
| 543 | #define BRW_OPCODE_MACH 73 |
| 544 | #define BRW_OPCODE_LZD 74 |
| 545 | #define BRW_OPCODE_SAD2 80 |
| 546 | #define BRW_OPCODE_SADA2 81 |
| 547 | #define BRW_OPCODE_DP4 84 |
| 548 | #define BRW_OPCODE_DPH 85 |
| 549 | #define BRW_OPCODE_DP3 86 |
| 550 | #define BRW_OPCODE_DP2 87 |
| 551 | #define BRW_OPCODE_DPA2 88 |
| 552 | #define BRW_OPCODE_LINE 89 |
| 553 | #define BRW_OPCODE_NOP 126 |
| 554 | |
| 555 | #define BRW_PREDICATE_NONE 0 |
| 556 | #define BRW_PREDICATE_NORMAL 1 |
| 557 | #define BRW_PREDICATE_ALIGN1_ANYV 2 |
| 558 | #define BRW_PREDICATE_ALIGN1_ALLV 3 |
| 559 | #define BRW_PREDICATE_ALIGN1_ANY2H 4 |
| 560 | #define BRW_PREDICATE_ALIGN1_ALL2H 5 |
| 561 | #define BRW_PREDICATE_ALIGN1_ANY4H 6 |
| 562 | #define BRW_PREDICATE_ALIGN1_ALL4H 7 |
| 563 | #define BRW_PREDICATE_ALIGN1_ANY8H 8 |
| 564 | #define BRW_PREDICATE_ALIGN1_ALL8H 9 |
| 565 | #define BRW_PREDICATE_ALIGN1_ANY16H 10 |
| 566 | #define BRW_PREDICATE_ALIGN1_ALL16H 11 |
| 567 | #define BRW_PREDICATE_ALIGN16_REPLICATE_X 2 |
| 568 | #define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3 |
| 569 | #define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4 |
| 570 | #define BRW_PREDICATE_ALIGN16_REPLICATE_W 5 |
| 571 | #define BRW_PREDICATE_ALIGN16_ANY4H 6 |
| 572 | #define BRW_PREDICATE_ALIGN16_ALL4H 7 |
| 573 | |
| 574 | #define BRW_ARCHITECTURE_REGISTER_FILE 0 |
| 575 | #define BRW_GENERAL_REGISTER_FILE 1 |
| 576 | #define BRW_MESSAGE_REGISTER_FILE 2 |
| 577 | #define BRW_IMMEDIATE_VALUE 3 |
| 578 | |
| 579 | #define BRW_REGISTER_TYPE_UD 0 |
| 580 | #define BRW_REGISTER_TYPE_D 1 |
| 581 | #define BRW_REGISTER_TYPE_UW 2 |
| 582 | #define BRW_REGISTER_TYPE_W 3 |
| 583 | #define BRW_REGISTER_TYPE_UB 4 |
| 584 | #define BRW_REGISTER_TYPE_B 5 |
| 585 | #define BRW_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */ |
| 586 | #define BRW_REGISTER_TYPE_HF 6 |
| 587 | #define BRW_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */ |
| 588 | #define BRW_REGISTER_TYPE_F 7 |
| 589 | |
| 590 | #define BRW_ARF_NULL 0x00 |
| 591 | #define BRW_ARF_ADDRESS 0x10 |
| 592 | #define BRW_ARF_ACCUMULATOR 0x20 |
| 593 | #define BRW_ARF_FLAG 0x30 |
| 594 | #define BRW_ARF_MASK 0x40 |
| 595 | #define BRW_ARF_MASK_STACK 0x50 |
| 596 | #define BRW_ARF_MASK_STACK_DEPTH 0x60 |
| 597 | #define BRW_ARF_STATE 0x70 |
| 598 | #define BRW_ARF_CONTROL 0x80 |
| 599 | #define BRW_ARF_NOTIFICATION_COUNT 0x90 |
| 600 | #define BRW_ARF_IP 0xA0 |
| 601 | |
| 602 | #define BRW_AMASK 0 |
| 603 | #define BRW_IMASK 1 |
| 604 | #define BRW_LMASK 2 |
| 605 | #define BRW_CMASK 3 |
| 606 | |
| 607 | |
| 608 | |
| 609 | #define BRW_THREAD_NORMAL 0 |
| 610 | #define BRW_THREAD_ATOMIC 1 |
| 611 | #define BRW_THREAD_SWITCH 2 |
| 612 | |
| 613 | #define BRW_VERTICAL_STRIDE_0 0 |
| 614 | #define BRW_VERTICAL_STRIDE_1 1 |
| 615 | #define BRW_VERTICAL_STRIDE_2 2 |
| 616 | #define BRW_VERTICAL_STRIDE_4 3 |
| 617 | #define BRW_VERTICAL_STRIDE_8 4 |
| 618 | #define BRW_VERTICAL_STRIDE_16 5 |
| 619 | #define BRW_VERTICAL_STRIDE_32 6 |
| 620 | #define BRW_VERTICAL_STRIDE_64 7 |
| 621 | #define BRW_VERTICAL_STRIDE_128 8 |
| 622 | #define BRW_VERTICAL_STRIDE_256 9 |
| 623 | #define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF |
| 624 | |
| 625 | #define BRW_WIDTH_1 0 |
| 626 | #define BRW_WIDTH_2 1 |
| 627 | #define BRW_WIDTH_4 2 |
| 628 | #define BRW_WIDTH_8 3 |
| 629 | #define BRW_WIDTH_16 4 |
| 630 | |
| 631 | #define BRW_STATELESS_BUFFER_BOUNDARY_1K 0 |
| 632 | #define BRW_STATELESS_BUFFER_BOUNDARY_2K 1 |
| 633 | #define BRW_STATELESS_BUFFER_BOUNDARY_4K 2 |
| 634 | #define BRW_STATELESS_BUFFER_BOUNDARY_8K 3 |
| 635 | #define BRW_STATELESS_BUFFER_BOUNDARY_16K 4 |
| 636 | #define BRW_STATELESS_BUFFER_BOUNDARY_32K 5 |
| 637 | #define BRW_STATELESS_BUFFER_BOUNDARY_64K 6 |
| 638 | #define BRW_STATELESS_BUFFER_BOUNDARY_128K 7 |
| 639 | #define BRW_STATELESS_BUFFER_BOUNDARY_256K 8 |
| 640 | #define BRW_STATELESS_BUFFER_BOUNDARY_512K 9 |
| 641 | #define BRW_STATELESS_BUFFER_BOUNDARY_1M 10 |
| 642 | #define BRW_STATELESS_BUFFER_BOUNDARY_2M 11 |
| 643 | |
| 644 | #define BRW_POLYGON_FACING_FRONT 0 |
| 645 | #define BRW_POLYGON_FACING_BACK 1 |
| 646 | |
| 647 | #define BRW_MESSAGE_TARGET_NULL 0 |
| 648 | #define BRW_MESSAGE_TARGET_MATH 1 |
| 649 | #define BRW_MESSAGE_TARGET_SAMPLER 2 |
| 650 | #define BRW_MESSAGE_TARGET_GATEWAY 3 |
| 651 | #define BRW_MESSAGE_TARGET_DATAPORT_READ 4 |
| 652 | #define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5 |
| 653 | #define BRW_MESSAGE_TARGET_URB 6 |
| 654 | #define BRW_MESSAGE_TARGET_THREAD_SPAWNER 7 |
| 655 | |
| 656 | #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0 |
| 657 | #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2 |
| 658 | #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3 |
| 659 | |
| 660 | #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 |
| 661 | #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 |
| 662 | #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 |
| 663 | #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 |
| 664 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 |
| 665 | #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 |
| 666 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 |
| 667 | #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 |
| 668 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 |
| 669 | #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 |
| 670 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 |
| 671 | #define BRW_SAMPLER_MESSAGE_SIMD8_RESINFO 2 |
| 672 | #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2 |
| 673 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3 |
| 674 | #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3 |
| 675 | #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3 |
| 676 | |
| 677 | #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_IGDNG 0 |
| 678 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_IGDNG 0 |
| 679 | #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_IGDNG 0 |
| 680 | #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_IGDNG 1 |
| 681 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_BIAS_IGDNG 1 |
| 682 | #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS_IGDNG 1 |
| 683 | #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_IGDNG 2 |
| 684 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_IGDNG 2 |
| 685 | #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD_IGDNG 2 |
| 686 | #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_COMPARE_IGDNG 3 |
| 687 | #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE_IGDNG 3 |
| 688 | #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE_IGDNG 3 |
| 689 | |
| 690 | /* for IGDNG only */ |
| 691 | #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0 |
| 692 | #define BRW_SAMPLER_SIMD_MODE_SIMD8 1 |
| 693 | #define BRW_SAMPLER_SIMD_MODE_SIMD16 2 |
| 694 | #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3 |
| 695 | |
| 696 | #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 |
| 697 | #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 |
| 698 | #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2 |
| 699 | #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3 |
| 700 | #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4 |
| 701 | |
| 702 | #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 |
| 703 | #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 |
| 704 | |
| 705 | #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 |
| 706 | #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 |
| 707 | |
| 708 | #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 |
| 709 | #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 |
| 710 | #define BRW_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ 2 |
| 711 | #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 |
| 712 | |
| 713 | #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0 |
| 714 | #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1 |
| 715 | #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 |
| 716 | |
| 717 | #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 |
| 718 | #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 |
| 719 | #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 |
| 720 | #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 |
| 721 | #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 |
| 722 | |
| 723 | #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 |
| 724 | #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 |
| 725 | #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2 |
| 726 | #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 |
| 727 | #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 |
| 728 | #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 |
| 729 | #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 |
| 730 | |
| 731 | #define BRW_MATH_FUNCTION_INV 1 |
| 732 | #define BRW_MATH_FUNCTION_LOG 2 |
| 733 | #define BRW_MATH_FUNCTION_EXP 3 |
| 734 | #define BRW_MATH_FUNCTION_SQRT 4 |
| 735 | #define BRW_MATH_FUNCTION_RSQ 5 |
| 736 | #define BRW_MATH_FUNCTION_SIN 6 /* was 7 */ |
| 737 | #define BRW_MATH_FUNCTION_COS 7 /* was 8 */ |
| 738 | #define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */ |
| 739 | #define BRW_MATH_FUNCTION_TAN 9 |
| 740 | #define BRW_MATH_FUNCTION_POW 10 |
| 741 | #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 |
| 742 | #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12 |
| 743 | #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13 |
| 744 | |
| 745 | #define BRW_MATH_INTEGER_UNSIGNED 0 |
| 746 | #define BRW_MATH_INTEGER_SIGNED 1 |
| 747 | |
| 748 | #define BRW_MATH_PRECISION_FULL 0 |
| 749 | #define BRW_MATH_PRECISION_PARTIAL 1 |
| 750 | |
| 751 | #define BRW_MATH_SATURATE_NONE 0 |
| 752 | #define BRW_MATH_SATURATE_SATURATE 1 |
| 753 | |
| 754 | #define BRW_MATH_DATA_VECTOR 0 |
| 755 | #define BRW_MATH_DATA_SCALAR 1 |
| 756 | |
| 757 | #define BRW_URB_OPCODE_WRITE 0 |
| 758 | |
| 759 | #define BRW_URB_SWIZZLE_NONE 0 |
| 760 | #define BRW_URB_SWIZZLE_INTERLEAVE 1 |
| 761 | #define BRW_URB_SWIZZLE_TRANSPOSE 2 |
| 762 | |
| 763 | #define BRW_SCRATCH_SPACE_SIZE_1K 0 |
| 764 | #define BRW_SCRATCH_SPACE_SIZE_2K 1 |
| 765 | #define BRW_SCRATCH_SPACE_SIZE_4K 2 |
| 766 | #define BRW_SCRATCH_SPACE_SIZE_8K 3 |
| 767 | #define BRW_SCRATCH_SPACE_SIZE_16K 4 |
| 768 | #define BRW_SCRATCH_SPACE_SIZE_32K 5 |
| 769 | #define BRW_SCRATCH_SPACE_SIZE_64K 6 |
| 770 | #define BRW_SCRATCH_SPACE_SIZE_128K 7 |
| 771 | #define BRW_SCRATCH_SPACE_SIZE_256K 8 |
| 772 | #define BRW_SCRATCH_SPACE_SIZE_512K 9 |
| 773 | #define BRW_SCRATCH_SPACE_SIZE_1M 10 |
| 774 | #define BRW_SCRATCH_SPACE_SIZE_2M 11 |
| 775 | |
| 776 | |
| 777 | |
| 778 | |
| 779 | #define CMD_URB_FENCE 0x6000 |
| 780 | #define CMD_CS_URB_STATE 0x6001 |
| 781 | #define CMD_CONST_BUFFER 0x6002 |
| 782 | |
| 783 | #define CMD_STATE_BASE_ADDRESS 0x6101 |
| 784 | #define CMD_STATE_INSN_POINTER 0x6102 |
| 785 | #define CMD_PIPELINE_SELECT_965 0x6104 |
| 786 | #define CMD_PIPELINE_SELECT_GM45 0x6904 |
| 787 | |
| 788 | #define CMD_PIPELINED_STATE_POINTERS 0x7800 |
| 789 | #define CMD_BINDING_TABLE_PTRS 0x7801 |
| 790 | |
| 791 | #define CMD_VERTEX_BUFFER 0x7808 |
| 792 | # define BRW_VB0_INDEX_SHIFT 27 |
| 793 | # define BRW_VB0_ACCESS_VERTEXDATA (0 << 26) |
| 794 | # define BRW_VB0_ACCESS_INSTANCEDATA (1 << 26) |
| 795 | # define BRW_VB0_PITCH_SHIFT 0 |
| 796 | |
| 797 | #define CMD_VERTEX_ELEMENT 0x7809 |
| 798 | # define BRW_VE0_INDEX_SHIFT 27 |
| 799 | # define BRW_VE0_FORMAT_SHIFT 16 |
| 800 | # define BRW_VE0_VALID (1 << 26) |
| 801 | # define BRW_VE0_SRC_OFFSET_SHIFT 0 |
| 802 | # define BRW_VE1_COMPONENT_NOSTORE 0 |
| 803 | # define BRW_VE1_COMPONENT_STORE_SRC 1 |
| 804 | # define BRW_VE1_COMPONENT_STORE_0 2 |
| 805 | # define BRW_VE1_COMPONENT_STORE_1_FLT 3 |
| 806 | # define BRW_VE1_COMPONENT_STORE_1_INT 4 |
| 807 | # define BRW_VE1_COMPONENT_STORE_VID 5 |
| 808 | # define BRW_VE1_COMPONENT_STORE_IID 6 |
| 809 | # define BRW_VE1_COMPONENT_STORE_PID 7 |
| 810 | # define BRW_VE1_COMPONENT_0_SHIFT 28 |
| 811 | # define BRW_VE1_COMPONENT_1_SHIFT 24 |
| 812 | # define BRW_VE1_COMPONENT_2_SHIFT 20 |
| 813 | # define BRW_VE1_COMPONENT_3_SHIFT 16 |
| 814 | # define BRW_VE1_DST_OFFSET_SHIFT 0 |
| 815 | |
| 816 | #define CMD_INDEX_BUFFER 0x780a |
| 817 | #define CMD_VF_STATISTICS_965 0x780b |
| 818 | #define CMD_VF_STATISTICS_GM45 0x680b |
| 819 | |
| 820 | #define CMD_DRAW_RECT 0x7900 |
| 821 | #define CMD_BLEND_CONSTANT_COLOR 0x7901 |
| 822 | #define CMD_CHROMA_KEY 0x7904 |
| 823 | #define CMD_DEPTH_BUFFER 0x7905 |
| 824 | #define CMD_POLY_STIPPLE_OFFSET 0x7906 |
| 825 | #define CMD_POLY_STIPPLE_PATTERN 0x7907 |
| 826 | #define CMD_LINE_STIPPLE_PATTERN 0x7908 |
| 827 | #define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7909 |
| 828 | #define CMD_AA_LINE_PARAMETERS 0x790a |
| 829 | |
| 830 | #define CMD_PIPE_CONTROL 0x7a00 |
| 831 | |
| 832 | #define CMD_3D_PRIM 0x7b00 |
| 833 | |
| 834 | #define CMD_MI_FLUSH 0x0200 |
| 835 | |
| 836 | |
| 837 | /* Various values from the R0 vertex header: |
| 838 | */ |
| 839 | #define R02_PRIM_END 0x1 |
| 840 | #define R02_PRIM_START 0x2 |
| 841 | |
Keith Whitwell | 2f5f7c0 | 2009-10-23 16:55:02 +0100 | [diff] [blame] | 842 | #define URB_SIZES(brw) (BRW_IS_IGDNG(brw) ? 1024 : \ |
| 843 | (BRW_IS_G4X(brw) ? 384 : 256)) /* 512 bit units */ |
| 844 | |
Keith Whitwell | 9b18ca0 | 2009-11-01 12:08:14 +0000 | [diff] [blame] | 845 | |
Keith Whitwell | 9b18ca0 | 2009-11-01 12:08:14 +0000 | [diff] [blame] | 846 | |
Keith Whitwell | 2f5f7c0 | 2009-10-23 16:55:02 +0100 | [diff] [blame] | 847 | #endif |