Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 1 | #include "pipe/p_context.h" |
| 2 | #include "pipe/p_defines.h" |
| 3 | #include "pipe/p_state.h" |
Ben Skeggs | 6b3ca67 | 2009-06-05 11:21:08 +1000 | [diff] [blame] | 4 | #include "pipe/p_inlines.h" |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 5 | |
| 6 | #include "pipe/p_shader_tokens.h" |
Ben Skeggs | fda01b5 | 2008-08-07 11:26:17 +1000 | [diff] [blame] | 7 | #include "tgsi/tgsi_parse.h" |
| 8 | #include "tgsi/tgsi_util.h" |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 9 | |
| 10 | #include "nv30_context.h" |
| 11 | |
| 12 | #define SWZ_X 0 |
| 13 | #define SWZ_Y 1 |
| 14 | #define SWZ_Z 2 |
| 15 | #define SWZ_W 3 |
| 16 | #define MASK_X 1 |
| 17 | #define MASK_Y 2 |
| 18 | #define MASK_Z 4 |
| 19 | #define MASK_W 8 |
| 20 | #define MASK_ALL (MASK_X|MASK_Y|MASK_Z|MASK_W) |
| 21 | #define DEF_SCALE NV30_FP_OP_DST_SCALE_1X |
| 22 | #define DEF_CTEST NV30_FP_OP_COND_TR |
| 23 | #include "nv30_shader.h" |
| 24 | |
| 25 | #define swz(s,x,y,z,w) nv30_sr_swz((s), SWZ_##x, SWZ_##y, SWZ_##z, SWZ_##w) |
| 26 | #define neg(s) nv30_sr_neg((s)) |
| 27 | #define abs(s) nv30_sr_abs((s)) |
| 28 | #define scale(s,v) nv30_sr_scale((s), NV30_FP_OP_DST_SCALE_##v) |
| 29 | |
| 30 | #define MAX_CONSTS 128 |
| 31 | #define MAX_IMM 32 |
| 32 | struct nv30_fpc { |
| 33 | struct nv30_fragment_program *fp; |
| 34 | |
| 35 | uint attrib_map[PIPE_MAX_SHADER_INPUTS]; |
| 36 | |
| 37 | int high_temp; |
| 38 | int temp_temp_count; |
| 39 | int num_regs; |
| 40 | |
| 41 | uint depth_id; |
| 42 | uint colour_id; |
| 43 | |
| 44 | unsigned inst_offset; |
| 45 | |
| 46 | struct { |
| 47 | int pipe; |
| 48 | float vals[4]; |
| 49 | } consts[MAX_CONSTS]; |
| 50 | int nr_consts; |
| 51 | |
| 52 | struct nv30_sreg imm[MAX_IMM]; |
| 53 | unsigned nr_imm; |
| 54 | }; |
| 55 | |
| 56 | static INLINE struct nv30_sreg |
| 57 | temp(struct nv30_fpc *fpc) |
| 58 | { |
| 59 | int idx; |
| 60 | |
| 61 | idx = fpc->temp_temp_count++; |
| 62 | idx += fpc->high_temp + 1; |
| 63 | return nv30_sr(NV30SR_TEMP, idx); |
| 64 | } |
| 65 | |
| 66 | static INLINE struct nv30_sreg |
| 67 | constant(struct nv30_fpc *fpc, int pipe, float vals[4]) |
| 68 | { |
| 69 | int idx; |
| 70 | |
| 71 | if (fpc->nr_consts == MAX_CONSTS) |
| 72 | assert(0); |
| 73 | idx = fpc->nr_consts++; |
| 74 | |
| 75 | fpc->consts[idx].pipe = pipe; |
| 76 | if (pipe == -1) |
| 77 | memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float)); |
| 78 | return nv30_sr(NV30SR_CONST, idx); |
| 79 | } |
| 80 | |
| 81 | #define arith(cc,s,o,d,m,s0,s1,s2) \ |
| 82 | nv30_fp_arith((cc), (s), NV30_FP_OP_OPCODE_##o, \ |
| 83 | (d), (m), (s0), (s1), (s2)) |
| 84 | #define tex(cc,s,o,u,d,m,s0,s1,s2) \ |
| 85 | nv30_fp_tex((cc), (s), NV30_FP_OP_OPCODE_##o, (u), \ |
| 86 | (d), (m), (s0), none, none) |
| 87 | |
| 88 | static void |
| 89 | grow_insns(struct nv30_fpc *fpc, int size) |
| 90 | { |
| 91 | struct nv30_fragment_program *fp = fpc->fp; |
| 92 | |
| 93 | fp->insn_len += size; |
| 94 | fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len); |
| 95 | } |
| 96 | |
| 97 | static void |
| 98 | emit_src(struct nv30_fpc *fpc, int pos, struct nv30_sreg src) |
| 99 | { |
| 100 | struct nv30_fragment_program *fp = fpc->fp; |
| 101 | uint32_t *hw = &fp->insn[fpc->inst_offset]; |
| 102 | uint32_t sr = 0; |
| 103 | |
| 104 | switch (src.type) { |
| 105 | case NV30SR_INPUT: |
| 106 | sr |= (NV30_FP_REG_TYPE_INPUT << NV30_FP_REG_TYPE_SHIFT); |
| 107 | hw[0] |= (src.index << NV30_FP_OP_INPUT_SRC_SHIFT); |
| 108 | break; |
| 109 | case NV30SR_OUTPUT: |
| 110 | sr |= NV30_FP_REG_SRC_HALF; |
| 111 | /* fall-through */ |
| 112 | case NV30SR_TEMP: |
| 113 | sr |= (NV30_FP_REG_TYPE_TEMP << NV30_FP_REG_TYPE_SHIFT); |
| 114 | sr |= (src.index << NV30_FP_REG_SRC_SHIFT); |
| 115 | break; |
| 116 | case NV30SR_CONST: |
| 117 | grow_insns(fpc, 4); |
| 118 | hw = &fp->insn[fpc->inst_offset]; |
| 119 | if (fpc->consts[src.index].pipe >= 0) { |
| 120 | struct nv30_fragment_program_data *fpd; |
| 121 | |
| 122 | fp->consts = realloc(fp->consts, ++fp->nr_consts * |
| 123 | sizeof(*fpd)); |
| 124 | fpd = &fp->consts[fp->nr_consts - 1]; |
| 125 | fpd->offset = fpc->inst_offset + 4; |
| 126 | fpd->index = fpc->consts[src.index].pipe; |
| 127 | memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4); |
| 128 | } else { |
| 129 | memcpy(&fp->insn[fpc->inst_offset + 4], |
| 130 | fpc->consts[src.index].vals, |
| 131 | sizeof(uint32_t) * 4); |
| 132 | } |
| 133 | |
| 134 | sr |= (NV30_FP_REG_TYPE_CONST << NV30_FP_REG_TYPE_SHIFT); |
| 135 | break; |
| 136 | case NV30SR_NONE: |
| 137 | sr |= (NV30_FP_REG_TYPE_INPUT << NV30_FP_REG_TYPE_SHIFT); |
| 138 | break; |
| 139 | default: |
| 140 | assert(0); |
| 141 | } |
| 142 | |
| 143 | if (src.negate) |
| 144 | sr |= NV30_FP_REG_NEGATE; |
| 145 | |
| 146 | if (src.abs) |
| 147 | hw[1] |= (1 << (29 + pos)); |
| 148 | |
| 149 | sr |= ((src.swz[0] << NV30_FP_REG_SWZ_X_SHIFT) | |
| 150 | (src.swz[1] << NV30_FP_REG_SWZ_Y_SHIFT) | |
| 151 | (src.swz[2] << NV30_FP_REG_SWZ_Z_SHIFT) | |
| 152 | (src.swz[3] << NV30_FP_REG_SWZ_W_SHIFT)); |
| 153 | |
| 154 | hw[pos + 1] |= sr; |
| 155 | } |
| 156 | |
| 157 | static void |
| 158 | emit_dst(struct nv30_fpc *fpc, struct nv30_sreg dst) |
| 159 | { |
| 160 | struct nv30_fragment_program *fp = fpc->fp; |
| 161 | uint32_t *hw = &fp->insn[fpc->inst_offset]; |
| 162 | |
| 163 | switch (dst.type) { |
| 164 | case NV30SR_TEMP: |
| 165 | if (fpc->num_regs < (dst.index + 1)) |
| 166 | fpc->num_regs = dst.index + 1; |
| 167 | break; |
| 168 | case NV30SR_OUTPUT: |
| 169 | if (dst.index == 1) { |
| 170 | fp->fp_control |= 0xe; |
| 171 | } else { |
| 172 | hw[0] |= NV30_FP_OP_OUT_REG_HALF; |
| 173 | } |
| 174 | break; |
| 175 | case NV30SR_NONE: |
| 176 | hw[0] |= (1 << 30); |
| 177 | break; |
| 178 | default: |
| 179 | assert(0); |
| 180 | } |
| 181 | |
| 182 | hw[0] |= (dst.index << NV30_FP_OP_OUT_REG_SHIFT); |
| 183 | } |
| 184 | |
| 185 | static void |
| 186 | nv30_fp_arith(struct nv30_fpc *fpc, int sat, int op, |
| 187 | struct nv30_sreg dst, int mask, |
| 188 | struct nv30_sreg s0, struct nv30_sreg s1, struct nv30_sreg s2) |
| 189 | { |
| 190 | struct nv30_fragment_program *fp = fpc->fp; |
| 191 | uint32_t *hw; |
| 192 | |
| 193 | fpc->inst_offset = fp->insn_len; |
| 194 | grow_insns(fpc, 4); |
| 195 | hw = &fp->insn[fpc->inst_offset]; |
| 196 | memset(hw, 0, sizeof(uint32_t) * 4); |
| 197 | |
| 198 | if (op == NV30_FP_OP_OPCODE_KIL) |
| 199 | fp->fp_control |= NV34TCL_FP_CONTROL_USES_KIL; |
| 200 | hw[0] |= (op << NV30_FP_OP_OPCODE_SHIFT); |
| 201 | hw[0] |= (mask << NV30_FP_OP_OUTMASK_SHIFT); |
| 202 | hw[2] |= (dst.dst_scale << NV30_FP_OP_DST_SCALE_SHIFT); |
| 203 | |
| 204 | if (sat) |
| 205 | hw[0] |= NV30_FP_OP_OUT_SAT; |
| 206 | |
| 207 | if (dst.cc_update) |
| 208 | hw[0] |= NV30_FP_OP_COND_WRITE_ENABLE; |
| 209 | hw[1] |= (dst.cc_test << NV30_FP_OP_COND_SHIFT); |
| 210 | hw[1] |= ((dst.cc_swz[0] << NV30_FP_OP_COND_SWZ_X_SHIFT) | |
| 211 | (dst.cc_swz[1] << NV30_FP_OP_COND_SWZ_Y_SHIFT) | |
| 212 | (dst.cc_swz[2] << NV30_FP_OP_COND_SWZ_Z_SHIFT) | |
| 213 | (dst.cc_swz[3] << NV30_FP_OP_COND_SWZ_W_SHIFT)); |
| 214 | |
| 215 | emit_dst(fpc, dst); |
| 216 | emit_src(fpc, 0, s0); |
| 217 | emit_src(fpc, 1, s1); |
| 218 | emit_src(fpc, 2, s2); |
| 219 | } |
| 220 | |
| 221 | static void |
| 222 | nv30_fp_tex(struct nv30_fpc *fpc, int sat, int op, int unit, |
| 223 | struct nv30_sreg dst, int mask, |
| 224 | struct nv30_sreg s0, struct nv30_sreg s1, struct nv30_sreg s2) |
| 225 | { |
| 226 | struct nv30_fragment_program *fp = fpc->fp; |
| 227 | |
| 228 | nv30_fp_arith(fpc, sat, op, dst, mask, s0, s1, s2); |
| 229 | |
| 230 | fp->insn[fpc->inst_offset] |= (unit << NV30_FP_OP_TEX_UNIT_SHIFT); |
| 231 | fp->samplers |= (1 << unit); |
| 232 | } |
| 233 | |
| 234 | static INLINE struct nv30_sreg |
| 235 | tgsi_src(struct nv30_fpc *fpc, const struct tgsi_full_src_register *fsrc) |
| 236 | { |
| 237 | struct nv30_sreg src; |
| 238 | |
| 239 | switch (fsrc->SrcRegister.File) { |
| 240 | case TGSI_FILE_INPUT: |
| 241 | src = nv30_sr(NV30SR_INPUT, |
| 242 | fpc->attrib_map[fsrc->SrcRegister.Index]); |
| 243 | break; |
| 244 | case TGSI_FILE_CONSTANT: |
| 245 | src = constant(fpc, fsrc->SrcRegister.Index, NULL); |
| 246 | break; |
| 247 | case TGSI_FILE_IMMEDIATE: |
| 248 | assert(fsrc->SrcRegister.Index < fpc->nr_imm); |
| 249 | src = fpc->imm[fsrc->SrcRegister.Index]; |
| 250 | break; |
| 251 | case TGSI_FILE_TEMPORARY: |
| 252 | src = nv30_sr(NV30SR_TEMP, fsrc->SrcRegister.Index + 1); |
| 253 | if (fpc->high_temp < src.index) |
| 254 | fpc->high_temp = src.index; |
| 255 | break; |
| 256 | /* This is clearly insane, but gallium hands us shaders like this. |
| 257 | * Luckily fragprog results are just temp regs.. |
| 258 | */ |
| 259 | case TGSI_FILE_OUTPUT: |
| 260 | if (fsrc->SrcRegister.Index == fpc->colour_id) |
| 261 | return nv30_sr(NV30SR_OUTPUT, 0); |
| 262 | else |
| 263 | return nv30_sr(NV30SR_OUTPUT, 1); |
| 264 | break; |
| 265 | default: |
| 266 | NOUVEAU_ERR("bad src file\n"); |
| 267 | break; |
| 268 | } |
| 269 | |
| 270 | src.abs = fsrc->SrcRegisterExtMod.Absolute; |
| 271 | src.negate = fsrc->SrcRegister.Negate; |
| 272 | src.swz[0] = fsrc->SrcRegister.SwizzleX; |
| 273 | src.swz[1] = fsrc->SrcRegister.SwizzleY; |
| 274 | src.swz[2] = fsrc->SrcRegister.SwizzleZ; |
| 275 | src.swz[3] = fsrc->SrcRegister.SwizzleW; |
| 276 | return src; |
| 277 | } |
| 278 | |
| 279 | static INLINE struct nv30_sreg |
| 280 | tgsi_dst(struct nv30_fpc *fpc, const struct tgsi_full_dst_register *fdst) { |
| 281 | int idx; |
| 282 | |
| 283 | switch (fdst->DstRegister.File) { |
| 284 | case TGSI_FILE_OUTPUT: |
| 285 | if (fdst->DstRegister.Index == fpc->colour_id) |
| 286 | return nv30_sr(NV30SR_OUTPUT, 0); |
| 287 | else |
| 288 | return nv30_sr(NV30SR_OUTPUT, 1); |
| 289 | break; |
| 290 | case TGSI_FILE_TEMPORARY: |
| 291 | idx = fdst->DstRegister.Index + 1; |
| 292 | if (fpc->high_temp < idx) |
| 293 | fpc->high_temp = idx; |
| 294 | return nv30_sr(NV30SR_TEMP, idx); |
| 295 | case TGSI_FILE_NULL: |
| 296 | return nv30_sr(NV30SR_NONE, 0); |
| 297 | default: |
| 298 | NOUVEAU_ERR("bad dst file %d\n", fdst->DstRegister.File); |
| 299 | return nv30_sr(NV30SR_NONE, 0); |
| 300 | } |
| 301 | } |
| 302 | |
| 303 | static INLINE int |
| 304 | tgsi_mask(uint tgsi) |
| 305 | { |
| 306 | int mask = 0; |
| 307 | |
| 308 | if (tgsi & TGSI_WRITEMASK_X) mask |= MASK_X; |
| 309 | if (tgsi & TGSI_WRITEMASK_Y) mask |= MASK_Y; |
| 310 | if (tgsi & TGSI_WRITEMASK_Z) mask |= MASK_Z; |
| 311 | if (tgsi & TGSI_WRITEMASK_W) mask |= MASK_W; |
| 312 | return mask; |
| 313 | } |
| 314 | |
| 315 | static boolean |
| 316 | src_native_swz(struct nv30_fpc *fpc, const struct tgsi_full_src_register *fsrc, |
| 317 | struct nv30_sreg *src) |
| 318 | { |
| 319 | const struct nv30_sreg none = nv30_sr(NV30SR_NONE, 0); |
| 320 | struct nv30_sreg tgsi = tgsi_src(fpc, fsrc); |
Keith Whitwell | da25331 | 2009-10-23 14:50:02 +0100 | [diff] [blame] | 321 | uint mask = 0; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 322 | uint c; |
| 323 | |
| 324 | for (c = 0; c < 4; c++) { |
Keith Whitwell | b9cb74c | 2009-10-23 14:31:24 +0100 | [diff] [blame] | 325 | switch (tgsi_util_get_full_src_register_swizzle(fsrc, c)) { |
| 326 | case TGSI_SWIZZLE_X: |
| 327 | case TGSI_SWIZZLE_Y: |
| 328 | case TGSI_SWIZZLE_Z: |
| 329 | case TGSI_SWIZZLE_W: |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 330 | mask |= (1 << c); |
| 331 | break; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 332 | default: |
| 333 | assert(0); |
| 334 | } |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 335 | } |
| 336 | |
Keith Whitwell | da25331 | 2009-10-23 14:50:02 +0100 | [diff] [blame] | 337 | if (mask == MASK_ALL) |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 338 | return TRUE; |
| 339 | |
| 340 | *src = temp(fpc); |
| 341 | |
| 342 | if (mask) |
| 343 | arith(fpc, 0, MOV, *src, mask, tgsi, none, none); |
| 344 | |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 345 | return FALSE; |
| 346 | } |
| 347 | |
| 348 | static boolean |
| 349 | nv30_fragprog_parse_instruction(struct nv30_fpc *fpc, |
| 350 | const struct tgsi_full_instruction *finst) |
| 351 | { |
| 352 | const struct nv30_sreg none = nv30_sr(NV30SR_NONE, 0); |
| 353 | struct nv30_sreg src[3], dst, tmp; |
Patrice Mandin | 169912b | 2008-03-11 19:22:02 +0100 | [diff] [blame] | 354 | int mask, sat, unit = 0; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 355 | int ai = -1, ci = -1; |
| 356 | int i; |
| 357 | |
| 358 | if (finst->Instruction.Opcode == TGSI_OPCODE_END) |
| 359 | return TRUE; |
| 360 | |
| 361 | fpc->temp_temp_count = 0; |
| 362 | for (i = 0; i < finst->Instruction.NumSrcRegs; i++) { |
| 363 | const struct tgsi_full_src_register *fsrc; |
| 364 | |
| 365 | fsrc = &finst->FullSrcRegisters[i]; |
| 366 | if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) { |
| 367 | src[i] = tgsi_src(fpc, fsrc); |
| 368 | } |
| 369 | } |
| 370 | |
| 371 | for (i = 0; i < finst->Instruction.NumSrcRegs; i++) { |
| 372 | const struct tgsi_full_src_register *fsrc; |
| 373 | |
| 374 | fsrc = &finst->FullSrcRegisters[i]; |
| 375 | |
| 376 | switch (fsrc->SrcRegister.File) { |
| 377 | case TGSI_FILE_INPUT: |
| 378 | case TGSI_FILE_CONSTANT: |
| 379 | case TGSI_FILE_TEMPORARY: |
| 380 | if (!src_native_swz(fpc, fsrc, &src[i])) |
| 381 | continue; |
| 382 | break; |
| 383 | default: |
| 384 | break; |
| 385 | } |
| 386 | |
| 387 | switch (fsrc->SrcRegister.File) { |
| 388 | case TGSI_FILE_INPUT: |
| 389 | if (ai == -1 || ai == fsrc->SrcRegister.Index) { |
| 390 | ai = fsrc->SrcRegister.Index; |
| 391 | src[i] = tgsi_src(fpc, fsrc); |
| 392 | } else { |
| 393 | NOUVEAU_MSG("extra src attr %d\n", |
| 394 | fsrc->SrcRegister.Index); |
| 395 | src[i] = temp(fpc); |
| 396 | arith(fpc, 0, MOV, src[i], MASK_ALL, |
| 397 | tgsi_src(fpc, fsrc), none, none); |
| 398 | } |
| 399 | break; |
| 400 | case TGSI_FILE_CONSTANT: |
| 401 | case TGSI_FILE_IMMEDIATE: |
| 402 | if (ci == -1 || ci == fsrc->SrcRegister.Index) { |
| 403 | ci = fsrc->SrcRegister.Index; |
| 404 | src[i] = tgsi_src(fpc, fsrc); |
| 405 | } else { |
| 406 | src[i] = temp(fpc); |
| 407 | arith(fpc, 0, MOV, src[i], MASK_ALL, |
| 408 | tgsi_src(fpc, fsrc), none, none); |
| 409 | } |
| 410 | break; |
| 411 | case TGSI_FILE_TEMPORARY: |
| 412 | /* handled above */ |
| 413 | break; |
| 414 | case TGSI_FILE_SAMPLER: |
| 415 | unit = fsrc->SrcRegister.Index; |
| 416 | break; |
| 417 | case TGSI_FILE_OUTPUT: |
| 418 | break; |
| 419 | default: |
| 420 | NOUVEAU_ERR("bad src file\n"); |
| 421 | return FALSE; |
| 422 | } |
| 423 | } |
| 424 | |
| 425 | dst = tgsi_dst(fpc, &finst->FullDstRegisters[0]); |
| 426 | mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask); |
| 427 | sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE); |
| 428 | |
| 429 | switch (finst->Instruction.Opcode) { |
| 430 | case TGSI_OPCODE_ABS: |
| 431 | arith(fpc, sat, MOV, dst, mask, abs(src[0]), none, none); |
| 432 | break; |
| 433 | case TGSI_OPCODE_ADD: |
| 434 | arith(fpc, sat, ADD, dst, mask, src[0], src[1], none); |
| 435 | break; |
| 436 | case TGSI_OPCODE_CMP: |
| 437 | tmp = temp(fpc); |
| 438 | arith(fpc, sat, MOV, dst, mask, src[2], none, none); |
| 439 | tmp.cc_update = 1; |
| 440 | arith(fpc, 0, MOV, tmp, 0xf, src[0], none, none); |
| 441 | dst.cc_test = NV30_VP_INST_COND_LT; |
| 442 | arith(fpc, sat, MOV, dst, mask, src[1], none, none); |
| 443 | break; |
| 444 | case TGSI_OPCODE_COS: |
| 445 | arith(fpc, sat, COS, dst, mask, src[0], none, none); |
| 446 | break; |
| 447 | case TGSI_OPCODE_DP3: |
| 448 | arith(fpc, sat, DP3, dst, mask, src[0], src[1], none); |
| 449 | break; |
| 450 | case TGSI_OPCODE_DP4: |
| 451 | arith(fpc, sat, DP4, dst, mask, src[0], src[1], none); |
| 452 | break; |
| 453 | case TGSI_OPCODE_DPH: |
| 454 | tmp = temp(fpc); |
| 455 | arith(fpc, 0, DP3, tmp, MASK_X, src[0], src[1], none); |
| 456 | arith(fpc, sat, ADD, dst, mask, swz(tmp, X, X, X, X), |
| 457 | swz(src[1], W, W, W, W), none); |
| 458 | break; |
| 459 | case TGSI_OPCODE_DST: |
| 460 | arith(fpc, sat, DST, dst, mask, src[0], src[1], none); |
| 461 | break; |
| 462 | case TGSI_OPCODE_EX2: |
| 463 | arith(fpc, sat, EX2, dst, mask, src[0], none, none); |
| 464 | break; |
| 465 | case TGSI_OPCODE_FLR: |
| 466 | arith(fpc, sat, FLR, dst, mask, src[0], none, none); |
| 467 | break; |
| 468 | case TGSI_OPCODE_FRC: |
| 469 | arith(fpc, sat, FRC, dst, mask, src[0], none, none); |
| 470 | break; |
Ben Skeggs | dbec107 | 2008-08-14 00:22:49 +1000 | [diff] [blame] | 471 | case TGSI_OPCODE_KILP: |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 472 | arith(fpc, 0, KIL, none, 0, none, none, none); |
| 473 | break; |
Ben Skeggs | dbec107 | 2008-08-14 00:22:49 +1000 | [diff] [blame] | 474 | case TGSI_OPCODE_KIL: |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 475 | dst = nv30_sr(NV30SR_NONE, 0); |
| 476 | dst.cc_update = 1; |
| 477 | arith(fpc, 0, MOV, dst, MASK_ALL, src[0], none, none); |
| 478 | dst.cc_update = 0; dst.cc_test = NV30_FP_OP_COND_LT; |
| 479 | arith(fpc, 0, KIL, dst, 0, none, none, none); |
| 480 | break; |
| 481 | case TGSI_OPCODE_LG2: |
| 482 | arith(fpc, sat, LG2, dst, mask, src[0], none, none); |
| 483 | break; |
| 484 | // case TGSI_OPCODE_LIT: |
| 485 | case TGSI_OPCODE_LRP: |
Stephane Marchesin | 28268f7 | 2008-07-08 16:38:27 +0200 | [diff] [blame] | 486 | arith(fpc, sat, LRP, dst, mask, src[0], src[1], src[2]); |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 487 | break; |
| 488 | case TGSI_OPCODE_MAD: |
| 489 | arith(fpc, sat, MAD, dst, mask, src[0], src[1], src[2]); |
| 490 | break; |
| 491 | case TGSI_OPCODE_MAX: |
| 492 | arith(fpc, sat, MAX, dst, mask, src[0], src[1], none); |
| 493 | break; |
| 494 | case TGSI_OPCODE_MIN: |
| 495 | arith(fpc, sat, MIN, dst, mask, src[0], src[1], none); |
| 496 | break; |
| 497 | case TGSI_OPCODE_MOV: |
| 498 | arith(fpc, sat, MOV, dst, mask, src[0], none, none); |
| 499 | break; |
| 500 | case TGSI_OPCODE_MUL: |
| 501 | arith(fpc, sat, MUL, dst, mask, src[0], src[1], none); |
| 502 | break; |
| 503 | case TGSI_OPCODE_POW: |
Stephane Marchesin | 28268f7 | 2008-07-08 16:38:27 +0200 | [diff] [blame] | 504 | arith(fpc, sat, POW, dst, mask, src[0], src[1], none); |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 505 | break; |
| 506 | case TGSI_OPCODE_RCP: |
| 507 | arith(fpc, sat, RCP, dst, mask, src[0], none, none); |
| 508 | break; |
| 509 | case TGSI_OPCODE_RET: |
| 510 | assert(0); |
| 511 | break; |
| 512 | case TGSI_OPCODE_RFL: |
Stephane Marchesin | 28268f7 | 2008-07-08 16:38:27 +0200 | [diff] [blame] | 513 | arith(fpc, 0, RFL, dst, mask, src[0], src[1], none); |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 514 | break; |
| 515 | case TGSI_OPCODE_RSQ: |
Stephane Marchesin | 28268f7 | 2008-07-08 16:38:27 +0200 | [diff] [blame] | 516 | arith(fpc, sat, RSQ, dst, mask, abs(swz(src[0], X, X, X, X)), none, none); |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 517 | break; |
| 518 | case TGSI_OPCODE_SCS: |
| 519 | if (mask & MASK_X) { |
| 520 | arith(fpc, sat, COS, dst, MASK_X, |
| 521 | swz(src[0], X, X, X, X), none, none); |
| 522 | } |
| 523 | if (mask & MASK_Y) { |
| 524 | arith(fpc, sat, SIN, dst, MASK_Y, |
| 525 | swz(src[0], X, X, X, X), none, none); |
| 526 | } |
| 527 | break; |
| 528 | case TGSI_OPCODE_SIN: |
| 529 | arith(fpc, sat, SIN, dst, mask, src[0], none, none); |
| 530 | break; |
| 531 | case TGSI_OPCODE_SGE: |
| 532 | arith(fpc, sat, SGE, dst, mask, src[0], src[1], none); |
| 533 | break; |
Stephane Marchesin | f90e50d | 2008-08-18 03:00:25 +0200 | [diff] [blame] | 534 | case TGSI_OPCODE_SGT: |
| 535 | arith(fpc, sat, SGT, dst, mask, src[0], src[1], none); |
| 536 | break; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 537 | case TGSI_OPCODE_SLT: |
| 538 | arith(fpc, sat, SLT, dst, mask, src[0], src[1], none); |
| 539 | break; |
| 540 | case TGSI_OPCODE_SUB: |
| 541 | arith(fpc, sat, ADD, dst, mask, src[0], neg(src[1]), none); |
| 542 | break; |
| 543 | case TGSI_OPCODE_TEX: |
Ben Skeggs | 9a4938d | 2008-03-13 12:36:35 +1100 | [diff] [blame] | 544 | tex(fpc, sat, TEX, unit, dst, mask, src[0], none, none); |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 545 | break; |
| 546 | case TGSI_OPCODE_TXB: |
| 547 | tex(fpc, sat, TXB, unit, dst, mask, src[0], none, none); |
| 548 | break; |
Ben Skeggs | 9a4938d | 2008-03-13 12:36:35 +1100 | [diff] [blame] | 549 | case TGSI_OPCODE_TXP: |
| 550 | tex(fpc, sat, TXP, unit, dst, mask, src[0], none, none); |
| 551 | break; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 552 | case TGSI_OPCODE_XPD: |
| 553 | tmp = temp(fpc); |
| 554 | arith(fpc, 0, MUL, tmp, mask, |
| 555 | swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none); |
| 556 | arith(fpc, sat, MAD, dst, (mask & ~MASK_W), |
| 557 | swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), |
| 558 | neg(tmp)); |
| 559 | break; |
| 560 | default: |
| 561 | NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode); |
| 562 | return FALSE; |
| 563 | } |
| 564 | |
| 565 | return TRUE; |
| 566 | } |
| 567 | |
| 568 | static boolean |
| 569 | nv30_fragprog_parse_decl_attrib(struct nv30_fpc *fpc, |
| 570 | const struct tgsi_full_declaration *fdec) |
| 571 | { |
| 572 | int hw; |
| 573 | |
| 574 | switch (fdec->Semantic.SemanticName) { |
| 575 | case TGSI_SEMANTIC_POSITION: |
| 576 | hw = NV30_FP_OP_INPUT_SRC_POSITION; |
| 577 | break; |
| 578 | case TGSI_SEMANTIC_COLOR: |
| 579 | if (fdec->Semantic.SemanticIndex == 0) { |
| 580 | hw = NV30_FP_OP_INPUT_SRC_COL0; |
| 581 | } else |
| 582 | if (fdec->Semantic.SemanticIndex == 1) { |
| 583 | hw = NV30_FP_OP_INPUT_SRC_COL1; |
| 584 | } else { |
| 585 | NOUVEAU_ERR("bad colour semantic index\n"); |
| 586 | return FALSE; |
| 587 | } |
| 588 | break; |
| 589 | case TGSI_SEMANTIC_FOG: |
| 590 | hw = NV30_FP_OP_INPUT_SRC_FOGC; |
| 591 | break; |
| 592 | case TGSI_SEMANTIC_GENERIC: |
| 593 | if (fdec->Semantic.SemanticIndex <= 7) { |
| 594 | hw = NV30_FP_OP_INPUT_SRC_TC(fdec->Semantic. |
| 595 | SemanticIndex); |
| 596 | } else { |
| 597 | NOUVEAU_ERR("bad generic semantic index\n"); |
| 598 | return FALSE; |
| 599 | } |
| 600 | break; |
| 601 | default: |
| 602 | NOUVEAU_ERR("bad input semantic\n"); |
| 603 | return FALSE; |
| 604 | } |
| 605 | |
Ben Skeggs | 5a01060 | 2008-06-23 00:14:21 +1000 | [diff] [blame] | 606 | fpc->attrib_map[fdec->DeclarationRange.First] = hw; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 607 | return TRUE; |
| 608 | } |
| 609 | |
| 610 | static boolean |
| 611 | nv30_fragprog_parse_decl_output(struct nv30_fpc *fpc, |
| 612 | const struct tgsi_full_declaration *fdec) |
| 613 | { |
| 614 | switch (fdec->Semantic.SemanticName) { |
| 615 | case TGSI_SEMANTIC_POSITION: |
Ben Skeggs | 5a01060 | 2008-06-23 00:14:21 +1000 | [diff] [blame] | 616 | fpc->depth_id = fdec->DeclarationRange.First; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 617 | break; |
| 618 | case TGSI_SEMANTIC_COLOR: |
Ben Skeggs | 5a01060 | 2008-06-23 00:14:21 +1000 | [diff] [blame] | 619 | fpc->colour_id = fdec->DeclarationRange.First; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 620 | break; |
| 621 | default: |
| 622 | NOUVEAU_ERR("bad output semantic\n"); |
| 623 | return FALSE; |
| 624 | } |
| 625 | |
| 626 | return TRUE; |
| 627 | } |
| 628 | |
Patrice Mandin | 37a418b | 2008-07-11 21:31:24 +0200 | [diff] [blame] | 629 | static boolean |
| 630 | nv30_fragprog_prepare(struct nv30_fpc *fpc) |
| 631 | { |
| 632 | struct tgsi_parse_context p; |
| 633 | /*int high_temp = -1, i;*/ |
| 634 | |
| 635 | tgsi_parse_init(&p, fpc->fp->pipe.tokens); |
| 636 | while (!tgsi_parse_end_of_tokens(&p)) { |
| 637 | const union tgsi_full_token *tok = &p.FullToken; |
| 638 | |
| 639 | tgsi_parse_token(&p); |
| 640 | switch(tok->Token.Type) { |
| 641 | case TGSI_TOKEN_TYPE_DECLARATION: |
| 642 | { |
| 643 | const struct tgsi_full_declaration *fdec; |
| 644 | fdec = &p.FullToken.FullDeclaration; |
| 645 | switch (fdec->Declaration.File) { |
| 646 | case TGSI_FILE_INPUT: |
| 647 | if (!nv30_fragprog_parse_decl_attrib(fpc, fdec)) |
| 648 | goto out_err; |
| 649 | break; |
| 650 | case TGSI_FILE_OUTPUT: |
| 651 | if (!nv30_fragprog_parse_decl_output(fpc, fdec)) |
| 652 | goto out_err; |
| 653 | break; |
| 654 | /*case TGSI_FILE_TEMPORARY: |
| 655 | if (fdec->DeclarationRange.Last > high_temp) { |
| 656 | high_temp = |
| 657 | fdec->DeclarationRange.Last; |
| 658 | } |
| 659 | break;*/ |
| 660 | default: |
| 661 | break; |
| 662 | } |
| 663 | } |
| 664 | break; |
| 665 | case TGSI_TOKEN_TYPE_IMMEDIATE: |
| 666 | { |
| 667 | struct tgsi_full_immediate *imm; |
| 668 | float vals[4]; |
| 669 | |
| 670 | imm = &p.FullToken.FullImmediate; |
| 671 | assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32); |
| 672 | assert(fpc->nr_imm < MAX_IMM); |
| 673 | |
Keith Whitwell | fd31f92 | 2009-07-22 00:39:00 +0100 | [diff] [blame] | 674 | vals[0] = imm->u[0].Float; |
| 675 | vals[1] = imm->u[1].Float; |
| 676 | vals[2] = imm->u[2].Float; |
| 677 | vals[3] = imm->u[3].Float; |
Patrice Mandin | 37a418b | 2008-07-11 21:31:24 +0200 | [diff] [blame] | 678 | fpc->imm[fpc->nr_imm++] = constant(fpc, -1, vals); |
| 679 | } |
| 680 | break; |
| 681 | default: |
| 682 | break; |
| 683 | } |
| 684 | } |
| 685 | tgsi_parse_free(&p); |
| 686 | |
| 687 | /*if (++high_temp) { |
| 688 | fpc->r_temp = CALLOC(high_temp, sizeof(struct nv30_sreg)); |
| 689 | for (i = 0; i < high_temp; i++) |
| 690 | fpc->r_temp[i] = temp(fpc); |
| 691 | fpc->r_temps_discard = 0; |
| 692 | }*/ |
| 693 | |
| 694 | return TRUE; |
| 695 | |
| 696 | out_err: |
| 697 | /*if (fpc->r_temp) |
| 698 | FREE(fpc->r_temp);*/ |
| 699 | tgsi_parse_free(&p); |
| 700 | return FALSE; |
| 701 | } |
| 702 | |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 703 | static void |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 704 | nv30_fragprog_translate(struct nv30_context *nv30, |
| 705 | struct nv30_fragment_program *fp) |
| 706 | { |
| 707 | struct tgsi_parse_context parse; |
| 708 | struct nv30_fpc *fpc = NULL; |
| 709 | |
Stephane Marchesin | f90e50d | 2008-08-18 03:00:25 +0200 | [diff] [blame] | 710 | tgsi_dump(fp->pipe.tokens,0); |
| 711 | |
Stephane Marchesin | 4032ff3 | 2008-02-16 02:54:11 +0100 | [diff] [blame] | 712 | fpc = CALLOC(1, sizeof(struct nv30_fpc)); |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 713 | if (!fpc) |
| 714 | return; |
| 715 | fpc->fp = fp; |
| 716 | fpc->high_temp = -1; |
| 717 | fpc->num_regs = 2; |
| 718 | |
Patrice Mandin | 37a418b | 2008-07-11 21:31:24 +0200 | [diff] [blame] | 719 | if (!nv30_fragprog_prepare(fpc)) { |
| 720 | FREE(fpc); |
| 721 | return; |
| 722 | } |
| 723 | |
Ben Skeggs | 9a4938d | 2008-03-13 12:36:35 +1100 | [diff] [blame] | 724 | tgsi_parse_init(&parse, fp->pipe.tokens); |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 725 | |
| 726 | while (!tgsi_parse_end_of_tokens(&parse)) { |
| 727 | tgsi_parse_token(&parse); |
| 728 | |
| 729 | switch (parse.FullToken.Token.Type) { |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 730 | case TGSI_TOKEN_TYPE_INSTRUCTION: |
| 731 | { |
| 732 | const struct tgsi_full_instruction *finst; |
| 733 | |
| 734 | finst = &parse.FullToken.FullInstruction; |
| 735 | if (!nv30_fragprog_parse_instruction(fpc, finst)) |
| 736 | goto out_err; |
| 737 | } |
| 738 | break; |
| 739 | default: |
| 740 | break; |
| 741 | } |
| 742 | } |
| 743 | |
| 744 | fp->fp_control |= (fpc->num_regs-1)/2; |
| 745 | fp->fp_reg_control = (1<<16)|0x4; |
| 746 | |
| 747 | /* Terminate final instruction */ |
| 748 | fp->insn[fpc->inst_offset] |= 0x00000001; |
| 749 | |
| 750 | /* Append NOP + END instruction, may or may not be necessary. */ |
| 751 | fpc->inst_offset = fp->insn_len; |
| 752 | grow_insns(fpc, 4); |
| 753 | fp->insn[fpc->inst_offset + 0] = 0x00000001; |
| 754 | fp->insn[fpc->inst_offset + 1] = 0x00000000; |
| 755 | fp->insn[fpc->inst_offset + 2] = 0x00000000; |
| 756 | fp->insn[fpc->inst_offset + 3] = 0x00000000; |
| 757 | |
| 758 | fp->translated = TRUE; |
| 759 | fp->on_hw = FALSE; |
| 760 | out_err: |
| 761 | tgsi_parse_free(&parse); |
Patrice Mandin | 7b389f8 | 2008-03-30 21:52:36 +0200 | [diff] [blame] | 762 | FREE(fpc); |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 763 | } |
| 764 | |
Patrice Mandin | b327b06 | 2008-07-11 22:06:12 +0200 | [diff] [blame] | 765 | static void |
| 766 | nv30_fragprog_upload(struct nv30_context *nv30, |
| 767 | struct nv30_fragment_program *fp) |
| 768 | { |
Ben Skeggs | 6b3ca67 | 2009-06-05 11:21:08 +1000 | [diff] [blame] | 769 | struct pipe_screen *pscreen = nv30->pipe.screen; |
Patrice Mandin | b327b06 | 2008-07-11 22:06:12 +0200 | [diff] [blame] | 770 | const uint32_t le = 1; |
| 771 | uint32_t *map; |
| 772 | int i; |
| 773 | |
Ben Skeggs | 6b3ca67 | 2009-06-05 11:21:08 +1000 | [diff] [blame] | 774 | map = pipe_buffer_map(pscreen, fp->buffer, PIPE_BUFFER_USAGE_CPU_WRITE); |
Patrice Mandin | b327b06 | 2008-07-11 22:06:12 +0200 | [diff] [blame] | 775 | |
| 776 | #if 0 |
| 777 | for (i = 0; i < fp->insn_len; i++) { |
| 778 | fflush(stdout); fflush(stderr); |
| 779 | NOUVEAU_ERR("%d 0x%08x\n", i, fp->insn[i]); |
| 780 | fflush(stdout); fflush(stderr); |
| 781 | } |
| 782 | #endif |
| 783 | |
| 784 | if ((*(const uint8_t *)&le)) { |
| 785 | for (i = 0; i < fp->insn_len; i++) { |
| 786 | map[i] = fp->insn[i]; |
| 787 | } |
| 788 | } else { |
| 789 | /* Weird swapping for big-endian chips */ |
| 790 | for (i = 0; i < fp->insn_len; i++) { |
| 791 | map[i] = ((fp->insn[i] & 0xffff) << 16) | |
| 792 | ((fp->insn[i] >> 16) & 0xffff); |
| 793 | } |
| 794 | } |
| 795 | |
Ben Skeggs | 6b3ca67 | 2009-06-05 11:21:08 +1000 | [diff] [blame] | 796 | pipe_buffer_unmap(pscreen, fp->buffer); |
Patrice Mandin | b327b06 | 2008-07-11 22:06:12 +0200 | [diff] [blame] | 797 | } |
| 798 | |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 799 | static boolean |
| 800 | nv30_fragprog_validate(struct nv30_context *nv30) |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 801 | { |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 802 | struct nv30_fragment_program *fp = nv30->fragprog; |
Patrice Mandin | c708627 | 2008-07-11 23:17:47 +0200 | [diff] [blame] | 803 | struct pipe_buffer *constbuf = |
| 804 | nv30->constbuf[PIPE_SHADER_FRAGMENT]; |
Ben Skeggs | 6b3ca67 | 2009-06-05 11:21:08 +1000 | [diff] [blame] | 805 | struct pipe_screen *pscreen = nv30->pipe.screen; |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 806 | struct nouveau_stateobj *so; |
| 807 | boolean new_consts = FALSE; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 808 | int i; |
| 809 | |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 810 | if (fp->translated) |
| 811 | goto update_constants; |
| 812 | |
| 813 | /*nv30->fallback_swrast &= ~NV30_NEW_FRAGPROG;*/ |
| 814 | nv30_fragprog_translate(nv30, fp); |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 815 | if (!fp->translated) { |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 816 | /*nv30->fallback_swrast |= NV30_NEW_FRAGPROG;*/ |
| 817 | return FALSE; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 818 | } |
| 819 | |
Ben Skeggs | 6b3ca67 | 2009-06-05 11:21:08 +1000 | [diff] [blame] | 820 | fp->buffer = pscreen->buffer_create(pscreen, 0x100, 0, fp->insn_len * 4); |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 821 | nv30_fragprog_upload(nv30, fp); |
| 822 | |
Patrice Mandin | 0c47bd0 | 2008-08-31 11:10:08 +0200 | [diff] [blame] | 823 | so = so_new(8, 1); |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 824 | so_method(so, nv30->screen->rankine, NV34TCL_FP_ACTIVE_PROGRAM, 1); |
Ben Skeggs | 072fdc1 | 2009-06-04 16:13:56 +1000 | [diff] [blame] | 825 | so_reloc (so, nouveau_bo(fp->buffer), 0, NOUVEAU_BO_VRAM | |
| 826 | NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW | |
| 827 | NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0, |
| 828 | NV34TCL_FP_ACTIVE_PROGRAM_DMA1); |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 829 | so_method(so, nv30->screen->rankine, NV34TCL_FP_CONTROL, 1); |
| 830 | so_data (so, fp->fp_control); |
Patrice Mandin | 9489de9 | 2008-07-12 10:13:58 +0200 | [diff] [blame] | 831 | so_method(so, nv30->screen->rankine, NV34TCL_FP_REG_CONTROL, 1); |
| 832 | so_data (so, fp->fp_reg_control); |
Patrice Mandin | 0c47bd0 | 2008-08-31 11:10:08 +0200 | [diff] [blame] | 833 | so_method(so, nv30->screen->rankine, NV34TCL_TX_UNITS_ENABLE, 1); |
| 834 | so_data (so, fp->samplers); |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 835 | so_ref(so, &fp->so); |
Ben Skeggs | ca95d71 | 2009-03-07 17:14:24 +1000 | [diff] [blame] | 836 | so_ref(NULL, &so); |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 837 | |
| 838 | update_constants: |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 839 | if (fp->nr_consts) { |
Patrice Mandin | c708627 | 2008-07-11 23:17:47 +0200 | [diff] [blame] | 840 | float *map; |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 841 | |
Ben Skeggs | 6b3ca67 | 2009-06-05 11:21:08 +1000 | [diff] [blame] | 842 | map = pipe_buffer_map(pscreen, constbuf, |
| 843 | PIPE_BUFFER_USAGE_CPU_READ); |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 844 | for (i = 0; i < fp->nr_consts; i++) { |
| 845 | struct nv30_fragment_program_data *fpd = &fp->consts[i]; |
| 846 | uint32_t *p = &fp->insn[fpd->offset]; |
| 847 | uint32_t *cb = (uint32_t *)&map[fpd->index * 4]; |
| 848 | |
| 849 | if (!memcmp(p, cb, 4 * sizeof(float))) |
| 850 | continue; |
| 851 | memcpy(p, cb, 4 * sizeof(float)); |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 852 | new_consts = TRUE; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 853 | } |
Ben Skeggs | 6b3ca67 | 2009-06-05 11:21:08 +1000 | [diff] [blame] | 854 | pipe_buffer_unmap(pscreen, constbuf); |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 855 | |
| 856 | if (new_consts) |
| 857 | nv30_fragprog_upload(nv30, fp); |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 858 | } |
| 859 | |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 860 | if (new_consts || fp->so != nv30->state.hw[NV30_STATE_FRAGPROG]) { |
| 861 | so_ref(fp->so, &nv30->state.hw[NV30_STATE_FRAGPROG]); |
| 862 | return TRUE; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 863 | } |
| 864 | |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 865 | return FALSE; |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 866 | } |
| 867 | |
| 868 | void |
| 869 | nv30_fragprog_destroy(struct nv30_context *nv30, |
| 870 | struct nv30_fragment_program *fp) |
| 871 | { |
| 872 | if (fp->insn_len) |
Patrice Mandin | 7b389f8 | 2008-03-30 21:52:36 +0200 | [diff] [blame] | 873 | FREE(fp->insn); |
Stephane Marchesin | 583f424 | 2008-02-15 02:36:28 +0100 | [diff] [blame] | 874 | } |
| 875 | |
Patrice Mandin | 58737dc | 2008-07-12 00:48:26 +0200 | [diff] [blame] | 876 | struct nv30_state_entry nv30_state_fragprog = { |
| 877 | .validate = nv30_fragprog_validate, |
| 878 | .dirty = { |
| 879 | .pipe = NV30_NEW_FRAGPROG, |
| 880 | .hw = NV30_STATE_FRAGPROG |
| 881 | } |
| 882 | }; |